549 lines
14 KiB
C
549 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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* Copyright (C) 2023 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/uaccess.h>
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#include <linux/kvm_host.h>
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#include <asm/cacheflush.h>
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#include <asm/hwcap.h>
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#include <asm/kvm_vcpu_vector.h>
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#include <asm/vector.h>
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#define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0)
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#define KVM_ISA_EXT_ARR(ext) \
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[KVM_RISCV_ISA_EXT_##ext] = RISCV_ISA_EXT_##ext
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/* Mapping between KVM ISA Extension ID & Host ISA extension ID */
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static const unsigned long kvm_isa_ext_arr[] = {
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[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
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[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
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[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
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[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
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[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
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[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
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[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
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[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
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KVM_ISA_EXT_ARR(SSAIA),
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KVM_ISA_EXT_ARR(SSTC),
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KVM_ISA_EXT_ARR(SVINVAL),
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KVM_ISA_EXT_ARR(SVNAPOT),
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KVM_ISA_EXT_ARR(SVPBMT),
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KVM_ISA_EXT_ARR(ZBB),
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KVM_ISA_EXT_ARR(ZIHINTPAUSE),
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KVM_ISA_EXT_ARR(ZICBOM),
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KVM_ISA_EXT_ARR(ZICBOZ),
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};
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static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
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{
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unsigned long i;
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for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
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if (kvm_isa_ext_arr[i] == base_ext)
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return i;
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}
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return KVM_RISCV_ISA_EXT_MAX;
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}
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static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_H:
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return false;
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case KVM_RISCV_ISA_EXT_V:
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return riscv_v_vstate_ctrl_user_allowed();
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default:
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break;
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}
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return true;
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}
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static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_A:
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case KVM_RISCV_ISA_EXT_C:
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case KVM_RISCV_ISA_EXT_I:
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case KVM_RISCV_ISA_EXT_M:
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case KVM_RISCV_ISA_EXT_SSAIA:
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case KVM_RISCV_ISA_EXT_SSTC:
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case KVM_RISCV_ISA_EXT_SVINVAL:
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case KVM_RISCV_ISA_EXT_SVNAPOT:
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case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
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case KVM_RISCV_ISA_EXT_ZBB:
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return false;
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default:
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break;
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}
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return true;
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}
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void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu)
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{
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unsigned long host_isa, i;
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for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
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host_isa = kvm_isa_ext_arr[i];
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if (__riscv_isa_extension_available(NULL, host_isa) &&
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kvm_riscv_vcpu_isa_enable_allowed(i))
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set_bit(host_isa, vcpu->arch.isa);
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}
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}
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static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
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return -EINVAL;
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reg_val = riscv_cbom_block_size;
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
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return -EINVAL;
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reg_val = riscv_cboz_block_size;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mvendorid):
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reg_val = vcpu->arch.mvendorid;
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break;
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case KVM_REG_RISCV_CONFIG_REG(marchid):
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reg_val = vcpu->arch.marchid;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mimpid):
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reg_val = vcpu->arch.mimpid;
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break;
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default:
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return -EINVAL;
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}
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long i, isa_ext, reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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/*
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* This ONE REG interface is only defined for
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* single letter extensions.
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*/
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if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
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return -EINVAL;
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if (!vcpu->arch.ran_atleast_once) {
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/* Ignore the enable/disable request for certain extensions */
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for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
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isa_ext = kvm_riscv_vcpu_base2isa_ext(i);
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if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) {
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reg_val &= ~BIT(i);
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continue;
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}
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if (!kvm_riscv_vcpu_isa_enable_allowed(isa_ext))
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if (reg_val & BIT(i))
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reg_val &= ~BIT(i);
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if (!kvm_riscv_vcpu_isa_disable_allowed(isa_ext))
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if (!(reg_val & BIT(i)))
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reg_val |= BIT(i);
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}
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reg_val &= riscv_isa_extension_base(NULL);
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/* Do not modify anything beyond single letter extensions */
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reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |
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(reg_val & KVM_RISCV_BASE_ISA_MASK);
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vcpu->arch.isa[0] = reg_val;
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kvm_riscv_vcpu_fp_reset(vcpu);
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} else {
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return -EOPNOTSUPP;
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}
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
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return -EOPNOTSUPP;
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case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
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return -EOPNOTSUPP;
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case KVM_REG_RISCV_CONFIG_REG(mvendorid):
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.mvendorid = reg_val;
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else
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return -EBUSY;
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break;
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case KVM_REG_RISCV_CONFIG_REG(marchid):
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.marchid = reg_val;
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else
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return -EBUSY;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mimpid):
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.mimpid = reg_val;
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else
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return -EBUSY;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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return -EINVAL;
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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reg_val = cntx->sepc;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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reg_val = ((unsigned long *)cntx)[reg_num];
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
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reg_val = (cntx->sstatus & SR_SPP) ?
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KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
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else
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return -EINVAL;
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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cntx->sepc = reg_val;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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((unsigned long *)cntx)[reg_num] = reg_val;
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
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if (reg_val == KVM_RISCV_MODE_S)
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cntx->sstatus |= SR_SPP;
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else
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cntx->sstatus &= ~SR_SPP;
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} else
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return -EINVAL;
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return 0;
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}
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static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu,
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unsigned long reg_num,
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unsigned long *out_val)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
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return -EINVAL;
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if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
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kvm_riscv_vcpu_flush_interrupts(vcpu);
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*out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
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*out_val |= csr->hvip & ~IRQ_LOCAL_MASK;
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} else
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*out_val = ((unsigned long *)csr)[reg_num];
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return 0;
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}
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static int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu,
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unsigned long reg_num,
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unsigned long reg_val)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
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return -EINVAL;
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if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
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reg_val &= VSIP_VALID_MASK;
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reg_val <<= VSIP_TO_HVIP_SHIFT;
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}
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((unsigned long *)csr)[reg_num] = reg_val;
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if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
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WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0);
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
|
||
|
|
const struct kvm_one_reg *reg)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
unsigned long __user *uaddr =
|
||
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
||
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
||
|
|
KVM_REG_SIZE_MASK |
|
||
|
|
KVM_REG_RISCV_CSR);
|
||
|
|
unsigned long reg_val, reg_subtype;
|
||
|
|
|
||
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
|
||
|
|
reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
|
||
|
|
switch (reg_subtype) {
|
||
|
|
case KVM_REG_RISCV_CSR_GENERAL:
|
||
|
|
rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, ®_val);
|
||
|
|
break;
|
||
|
|
case KVM_REG_RISCV_CSR_AIA:
|
||
|
|
rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, ®_val);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
rc = -EINVAL;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (rc)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
|
||
|
|
const struct kvm_one_reg *reg)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
unsigned long __user *uaddr =
|
||
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
||
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
||
|
|
KVM_REG_SIZE_MASK |
|
||
|
|
KVM_REG_RISCV_CSR);
|
||
|
|
unsigned long reg_val, reg_subtype;
|
||
|
|
|
||
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
|
||
|
|
reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
|
||
|
|
switch (reg_subtype) {
|
||
|
|
case KVM_REG_RISCV_CSR_GENERAL:
|
||
|
|
rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);
|
||
|
|
break;
|
||
|
|
case KVM_REG_RISCV_CSR_AIA:
|
||
|
|
rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
rc = -EINVAL;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (rc)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
|
||
|
|
const struct kvm_one_reg *reg)
|
||
|
|
{
|
||
|
|
unsigned long __user *uaddr =
|
||
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
||
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
||
|
|
KVM_REG_SIZE_MASK |
|
||
|
|
KVM_REG_RISCV_ISA_EXT);
|
||
|
|
unsigned long reg_val = 0;
|
||
|
|
unsigned long host_isa_ext;
|
||
|
|
|
||
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
|
||
|
|
reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
host_isa_ext = kvm_isa_ext_arr[reg_num];
|
||
|
|
if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext))
|
||
|
|
reg_val = 1; /* Mark the given extension as available */
|
||
|
|
|
||
|
|
if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
|
||
|
|
const struct kvm_one_reg *reg)
|
||
|
|
{
|
||
|
|
unsigned long __user *uaddr =
|
||
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
||
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
||
|
|
KVM_REG_SIZE_MASK |
|
||
|
|
KVM_REG_RISCV_ISA_EXT);
|
||
|
|
unsigned long reg_val;
|
||
|
|
unsigned long host_isa_ext;
|
||
|
|
|
||
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
|
||
|
|
reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
||
|
|
return -EFAULT;
|
||
|
|
|
||
|
|
host_isa_ext = kvm_isa_ext_arr[reg_num];
|
||
|
|
if (!__riscv_isa_extension_available(NULL, host_isa_ext))
|
||
|
|
return -EOPNOTSUPP;
|
||
|
|
|
||
|
|
if (!vcpu->arch.ran_atleast_once) {
|
||
|
|
/*
|
||
|
|
* All multi-letter extension and a few single letter
|
||
|
|
* extension can be disabled
|
||
|
|
*/
|
||
|
|
if (reg_val == 1 &&
|
||
|
|
kvm_riscv_vcpu_isa_enable_allowed(reg_num))
|
||
|
|
set_bit(host_isa_ext, vcpu->arch.isa);
|
||
|
|
else if (!reg_val &&
|
||
|
|
kvm_riscv_vcpu_isa_disable_allowed(reg_num))
|
||
|
|
clear_bit(host_isa_ext, vcpu->arch.isa);
|
||
|
|
else
|
||
|
|
return -EINVAL;
|
||
|
|
kvm_riscv_vcpu_fp_reset(vcpu);
|
||
|
|
} else {
|
||
|
|
return -EOPNOTSUPP;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
|
||
|
|
const struct kvm_one_reg *reg)
|
||
|
|
{
|
||
|
|
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
|
||
|
|
case KVM_REG_RISCV_CONFIG:
|
||
|
|
return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_CORE:
|
||
|
|
return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_CSR:
|
||
|
|
return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_TIMER:
|
||
|
|
return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_FP_F:
|
||
|
|
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
|
||
|
|
KVM_REG_RISCV_FP_F);
|
||
|
|
case KVM_REG_RISCV_FP_D:
|
||
|
|
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
|
||
|
|
KVM_REG_RISCV_FP_D);
|
||
|
|
case KVM_REG_RISCV_ISA_EXT:
|
||
|
|
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_SBI_EXT:
|
||
|
|
return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_VECTOR:
|
||
|
|
return kvm_riscv_vcpu_set_reg_vector(vcpu, reg,
|
||
|
|
KVM_REG_RISCV_VECTOR);
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
|
||
|
|
const struct kvm_one_reg *reg)
|
||
|
|
{
|
||
|
|
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
|
||
|
|
case KVM_REG_RISCV_CONFIG:
|
||
|
|
return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_CORE:
|
||
|
|
return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_CSR:
|
||
|
|
return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_TIMER:
|
||
|
|
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_FP_F:
|
||
|
|
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
|
||
|
|
KVM_REG_RISCV_FP_F);
|
||
|
|
case KVM_REG_RISCV_FP_D:
|
||
|
|
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
|
||
|
|
KVM_REG_RISCV_FP_D);
|
||
|
|
case KVM_REG_RISCV_ISA_EXT:
|
||
|
|
return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_SBI_EXT:
|
||
|
|
return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg);
|
||
|
|
case KVM_REG_RISCV_VECTOR:
|
||
|
|
return kvm_riscv_vcpu_get_reg_vector(vcpu, reg,
|
||
|
|
KVM_REG_RISCV_VECTOR);
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return -EINVAL;
|
||
|
|
}
|