2009-06-05 20:42:42 +08:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __RADEON_OBJECT_H__
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#define __RADEON_OBJECT_H__
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2009-11-20 21:29:23 +08:00
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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2009-06-05 20:42:42 +08:00
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2009-11-20 21:29:23 +08:00
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/**
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* radeon_mem_type_to_domain - return domain corresponding to mem_type
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* @mem_type: ttm memory type
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*
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* Returns corresponding domain of the ttm mem_type
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*/
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static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
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{
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switch (mem_type) {
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case TTM_PL_VRAM:
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return RADEON_GEM_DOMAIN_VRAM;
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case TTM_PL_TT:
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return RADEON_GEM_DOMAIN_GTT;
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case TTM_PL_SYSTEM:
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return RADEON_GEM_DOMAIN_CPU;
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default:
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break;
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}
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return 0;
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}
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2011-10-14 07:08:47 +08:00
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int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait);
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2009-11-20 21:29:23 +08:00
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static inline void radeon_bo_unreserve(struct radeon_bo *bo)
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{
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ttm_bo_unreserve(&bo->tbo);
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}
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/**
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* radeon_bo_gpu_offset - return GPU offset of bo
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* @bo: radeon object for which we query the offset
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*
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* Returns current GPU offset of the object.
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*
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* Note: object should either be pinned or reserved when calling this
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2011-03-31 09:57:33 +08:00
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* function, it might be useful to add check for this for debugging.
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2009-11-20 21:29:23 +08:00
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*/
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static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
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{
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return bo->tbo.offset;
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}
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static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
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{
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return bo->tbo.num_pages << PAGE_SHIFT;
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}
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static inline bool radeon_bo_is_reserved(struct radeon_bo *bo)
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{
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return !!atomic_read(&bo->tbo.reserved);
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}
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drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 11:11:05 +08:00
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static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
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{
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return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
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}
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static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
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{
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return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
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}
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2009-11-20 21:29:23 +08:00
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/**
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* radeon_bo_mmap_offset - return mmap offset of bo
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* @bo: radeon object for which we query the offset
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*
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* Returns mmap offset of the object.
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*
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* Note: addr_space_offset is constant after ttm bo init thus isn't protected
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* by any lock.
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2009-06-05 20:42:42 +08:00
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*/
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2009-11-20 21:29:23 +08:00
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static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
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{
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return bo->tbo.addr_space_offset;
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}
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2011-10-14 07:08:47 +08:00
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extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
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2011-10-28 00:15:10 +08:00
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bool no_wait);
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2009-11-20 21:29:23 +08:00
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extern int radeon_bo_create(struct radeon_device *rdev,
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2011-02-19 00:59:16 +08:00
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unsigned long size, int byte_align,
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bool kernel, u32 domain,
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struct radeon_bo **bo_ptr);
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2009-11-20 21:29:23 +08:00
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extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
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extern void radeon_bo_kunmap(struct radeon_bo *bo);
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extern void radeon_bo_unref(struct radeon_bo **bo);
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extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
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2012-03-15 00:12:41 +08:00
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extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
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u64 max_offset, u64 *gpu_addr);
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2009-11-20 21:29:23 +08:00
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extern int radeon_bo_unpin(struct radeon_bo *bo);
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extern int radeon_bo_evict_vram(struct radeon_device *rdev);
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extern void radeon_bo_force_delete(struct radeon_device *rdev);
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extern int radeon_bo_init(struct radeon_device *rdev);
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extern void radeon_bo_fini(struct radeon_device *rdev);
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extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
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struct list_head *head);
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2010-02-16 04:36:33 +08:00
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extern int radeon_bo_list_validate(struct list_head *head);
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2009-11-20 21:29:23 +08:00
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extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
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struct vm_area_struct *vma);
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extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
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u32 tiling_flags, u32 pitch);
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extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
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u32 *tiling_flags, u32 *pitch);
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extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
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bool force_drop);
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extern void radeon_bo_move_notify(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *mem);
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2010-04-09 20:39:24 +08:00
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extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
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2009-12-09 12:15:38 +08:00
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extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
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drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06 11:11:05 +08:00
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extern struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo,
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struct radeon_vm *vm);
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drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
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/*
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* sub allocation
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*/
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2012-05-09 21:34:49 +08:00
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static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
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{
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2012-05-09 21:34:52 +08:00
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return sa_bo->manager->gpu_addr + sa_bo->soffset;
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2012-05-09 21:34:49 +08:00
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}
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static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
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{
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2012-05-09 21:34:52 +08:00
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return sa_bo->manager->cpu_ptr + sa_bo->soffset;
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2012-05-09 21:34:49 +08:00
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}
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drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
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extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
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struct radeon_sa_manager *sa_manager,
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unsigned size, u32 domain);
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extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
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struct radeon_sa_manager *sa_manager);
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extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
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struct radeon_sa_manager *sa_manager);
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extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
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struct radeon_sa_manager *sa_manager);
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extern int radeon_sa_bo_new(struct radeon_device *rdev,
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struct radeon_sa_manager *sa_manager,
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struct radeon_sa_bo *sa_bo,
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unsigned size, unsigned align);
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extern void radeon_sa_bo_free(struct radeon_device *rdev,
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struct radeon_sa_bo *sa_bo);
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2012-05-09 21:34:51 +08:00
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#if defined(CONFIG_DEBUG_FS)
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extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
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struct seq_file *m);
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#endif
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drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation
for command buffer not only for current cs ioctl but for future command
submission ioctl as well. Patch also convert current ib pool to use
the sub allocator. Idea is that ib poll buffer can be share with other
command buffer submission not having 64K granularity.
v2 Harmonize pool handling and add suspend/resume callback to pin/unpin
sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman,
rs480, rs690, rs880)
v3 Simplify allocator
v4 Fix radeon_ib_get error path to properly free fence
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-16 00:48:34 +08:00
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2009-06-05 20:42:42 +08:00
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|
|
#endif
|