2013-08-28 04:40:56 +08:00
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Shobhit Kumar <shobhit.kumar@intel.com>
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* Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
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*/
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#include <linux/kernel.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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#include "intel_dsi.h"
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2016-03-15 22:40:02 +08:00
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static const u16 lfsr_converts[] = {
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2013-08-28 04:40:56 +08:00
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426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
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461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
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2015-07-01 20:58:51 +08:00
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106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
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71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
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2013-08-28 04:40:56 +08:00
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};
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2013-12-10 14:44:56 +08:00
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/* Get DSI clock from pixel clock */
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2016-03-16 18:21:40 +08:00
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static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
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int lane_count)
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2013-08-28 04:40:56 +08:00
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{
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2013-12-10 14:44:56 +08:00
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u32 dsi_clk_khz;
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2016-03-16 18:21:40 +08:00
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u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
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2013-08-28 04:40:56 +08:00
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2013-12-10 14:44:56 +08:00
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/* DSI data rate = pixel clock * bits per pixel / lane count
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pixel clock is converted from KHz to Hz */
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2014-07-30 23:04:57 +08:00
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dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
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2013-08-28 04:40:56 +08:00
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2013-12-10 14:44:56 +08:00
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return dsi_clk_khz;
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2013-08-28 04:40:56 +08:00
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}
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2015-07-01 20:58:52 +08:00
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static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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2016-04-13 03:14:35 +08:00
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struct intel_crtc_state *config,
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int target_dsi_clk)
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2013-08-28 04:40:56 +08:00
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{
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2015-07-01 20:58:52 +08:00
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unsigned int m_min, m_max, p_min = 2, p_max = 6;
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unsigned int m, n, p;
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2016-07-02 22:36:04 +08:00
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unsigned int calc_m, calc_p;
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int delta, ref_clk;
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2013-08-28 04:40:56 +08:00
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2015-05-12 20:23:09 +08:00
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/* target_dsi_clk is expected in kHz */
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if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
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2013-08-28 04:40:56 +08:00
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DRM_ERROR("DSI CLK Out of Range\n");
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return -ECHRNG;
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}
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2015-07-01 20:58:52 +08:00
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if (IS_CHERRYVIEW(dev_priv)) {
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ref_clk = 100000;
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n = 4;
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m_min = 70;
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m_max = 96;
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} else {
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ref_clk = 25000;
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n = 1;
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m_min = 62;
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m_max = 92;
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}
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2016-07-02 22:36:04 +08:00
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calc_p = p_min;
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calc_m = m_min;
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delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
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2015-07-01 20:58:52 +08:00
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for (m = m_min; m <= m_max && delta; m++) {
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for (p = p_min; p <= p_max && delta; p++) {
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2015-05-12 20:23:09 +08:00
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/*
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* Find the optimal m and p divisors with minimal delta
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* +/- the required clock
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*/
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2015-05-13 15:35:25 +08:00
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int calc_dsi_clk = (m * ref_clk) / (p * n);
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2015-05-12 20:23:09 +08:00
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int d = abs(target_dsi_clk - calc_dsi_clk);
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if (d < delta) {
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delta = d;
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2013-12-10 14:44:57 +08:00
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calc_m = m;
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calc_p = p;
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2013-08-28 04:40:56 +08:00
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}
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}
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}
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2015-05-13 15:35:25 +08:00
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/* register has log2(N1), this works fine for powers of two */
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2016-04-13 03:14:35 +08:00
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config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
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2016-07-02 22:36:04 +08:00
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config->dsi_pll.div =
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(ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
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(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
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2013-08-28 04:40:56 +08:00
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return 0;
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}
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/*
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* XXX: The muxing and gating is hard coded for now. Need to add support for
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* sharing PLLs with two DSI outputs.
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*/
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2016-04-13 03:14:35 +08:00
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static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
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struct intel_crtc_state *config)
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2013-08-28 04:40:56 +08:00
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{
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2016-07-04 18:34:36 +08:00
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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2013-08-28 04:40:56 +08:00
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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int ret;
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u32 dsi_clk;
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2014-07-30 23:04:57 +08:00
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dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
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2014-07-31 04:34:27 +08:00
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intel_dsi->lane_count);
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2013-08-28 04:40:56 +08:00
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2016-04-13 03:14:35 +08:00
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ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
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2013-08-28 04:40:56 +08:00
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if (ret) {
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DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
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2016-04-13 03:14:35 +08:00
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return ret;
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2013-08-28 04:40:56 +08:00
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}
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2014-12-09 13:27:00 +08:00
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if (intel_dsi->ports & (1 << PORT_A))
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2016-04-13 03:14:35 +08:00
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config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
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2013-08-28 04:40:56 +08:00
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2014-12-09 13:27:00 +08:00
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if (intel_dsi->ports & (1 << PORT_C))
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2016-04-13 03:14:35 +08:00
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config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
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config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
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2014-12-04 13:28:52 +08:00
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2013-08-28 04:40:56 +08:00
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DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
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2016-04-13 03:14:35 +08:00
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config->dsi_pll.div, config->dsi_pll.ctrl);
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return 0;
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}
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static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
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const struct intel_crtc_state *config)
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2013-08-28 04:40:56 +08:00
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{
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2016-04-13 03:14:35 +08:00
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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2013-08-28 04:40:56 +08:00
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DRM_DEBUG_KMS("\n");
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2015-05-27 01:42:30 +08:00
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mutex_lock(&dev_priv->sb_lock);
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2013-08-28 04:40:56 +08:00
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2016-04-13 03:14:36 +08:00
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
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config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
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2013-08-28 04:40:56 +08:00
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2016-12-16 09:59:38 +08:00
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/* wait at least 0.5 us after ungating before enabling VCO,
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* allow hrtimer subsystem optimization by relaxing timing
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*/
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usleep_range(10, 50);
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2013-08-28 04:40:56 +08:00
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2016-04-13 03:14:35 +08:00
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
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2013-08-28 04:40:56 +08:00
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2014-12-05 16:46:58 +08:00
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if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
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DSI_PLL_LOCK, 20)) {
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2013-08-28 04:40:56 +08:00
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2015-05-27 01:42:30 +08:00
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mutex_unlock(&dev_priv->sb_lock);
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2013-08-28 04:40:56 +08:00
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DRM_ERROR("DSI PLL lock failed\n");
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return;
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}
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2015-05-27 01:42:30 +08:00
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mutex_unlock(&dev_priv->sb_lock);
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2013-08-28 04:40:56 +08:00
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DRM_DEBUG_KMS("DSI PLL locked\n");
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}
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2015-09-01 22:11:39 +08:00
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static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
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2013-08-28 04:40:56 +08:00
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{
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2016-04-13 03:14:35 +08:00
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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2013-08-28 04:40:56 +08:00
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u32 tmp;
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DRM_DEBUG_KMS("\n");
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2015-05-27 01:42:30 +08:00
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mutex_lock(&dev_priv->sb_lock);
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2013-08-28 04:40:56 +08:00
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tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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tmp &= ~DSI_PLL_VCO_EN;
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tmp |= DSI_PLL_LDO_GATE;
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
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2015-05-27 01:42:30 +08:00
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mutex_unlock(&dev_priv->sb_lock);
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2013-08-28 04:40:56 +08:00
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}
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2014-07-30 23:02:37 +08:00
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2016-03-24 18:41:40 +08:00
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static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
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{
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bool enabled;
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u32 val;
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u32 mask;
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mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
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val = I915_READ(BXT_DSI_PLL_ENABLE);
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enabled = (val & mask) == mask;
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if (!enabled)
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return false;
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/*
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2017-02-17 20:43:35 +08:00
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* Dividers must be programmed with valid values. As per BSEPC, for
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* GEMINLAKE only PORT A divider values are checked while for BXT
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* both divider values are validated. Check this here for
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2016-03-24 18:41:40 +08:00
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* paranoia, since BIOS is known to misconfigure PLLs in this way at
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* times, and since accessing DSI registers with invalid dividers
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* causes a system hang.
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*/
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val = I915_READ(BXT_DSI_PLL_CTL);
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2017-02-17 20:43:35 +08:00
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if (IS_GEMINILAKE(dev_priv)) {
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if (!(val & BXT_DSIA_16X_MASK)) {
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DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
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enabled = false;
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}
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} else {
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if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
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DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
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enabled = false;
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}
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2016-03-24 18:41:40 +08:00
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}
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return enabled;
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}
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2015-09-01 22:11:39 +08:00
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static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
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{
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2016-04-13 03:14:35 +08:00
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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2015-09-01 22:11:39 +08:00
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u32 val;
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DRM_DEBUG_KMS("\n");
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val = I915_READ(BXT_DSI_PLL_ENABLE);
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val &= ~BXT_DSI_PLL_DO_ENABLE;
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I915_WRITE(BXT_DSI_PLL_ENABLE, val);
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/*
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* PLL lock should deassert within 200us.
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* Wait up to 1ms before timing out.
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*/
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2016-06-30 22:33:19 +08:00
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if (intel_wait_for_register(dev_priv,
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BXT_DSI_PLL_ENABLE,
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BXT_DSI_PLL_LOCKED,
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0,
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1))
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2015-09-01 22:11:39 +08:00
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DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
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}
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2016-03-16 18:21:40 +08:00
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static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
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2014-07-30 23:02:37 +08:00
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{
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2016-03-16 18:21:40 +08:00
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int bpp = mipi_dsi_pixel_format_to_bpp(fmt);
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2014-07-30 23:02:37 +08:00
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WARN(bpp != pipe_bpp,
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2014-07-31 04:34:27 +08:00
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"bpp match assertion failure (expected %d, current %d)\n",
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bpp, pipe_bpp);
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2014-07-30 23:02:37 +08:00
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}
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2016-04-13 03:14:35 +08:00
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static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
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struct intel_crtc_state *config)
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2014-07-30 23:02:37 +08:00
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{
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2016-04-13 03:14:35 +08:00
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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2014-07-30 23:02:37 +08:00
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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u32 dsi_clock, pclk;
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u32 pll_ctl, pll_div;
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2015-05-13 15:35:25 +08:00
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u32 m = 0, p = 0, n;
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2016-03-15 22:40:05 +08:00
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int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
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2014-07-30 23:02:37 +08:00
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int i;
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DRM_DEBUG_KMS("\n");
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2015-05-27 01:42:30 +08:00
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mutex_lock(&dev_priv->sb_lock);
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2014-07-30 23:02:37 +08:00
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|
|
pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
|
|
|
|
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
|
2015-05-27 01:42:30 +08:00
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
2014-07-30 23:02:37 +08:00
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
|
|
|
|
config->dsi_pll.div = pll_div;
|
|
|
|
|
2014-07-30 23:02:37 +08:00
|
|
|
/* mask out other bits and extract the P1 divisor */
|
|
|
|
pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
|
|
|
|
pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
|
|
|
|
|
2015-05-13 15:35:25 +08:00
|
|
|
/* N1 divisor */
|
|
|
|
n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
|
|
|
|
n = 1 << n; /* register has log2(N1) */
|
|
|
|
|
2014-07-30 23:02:37 +08:00
|
|
|
/* mask out the other bits and extract the M1 divisor */
|
|
|
|
pll_div &= DSI_PLL_M1_DIV_MASK;
|
|
|
|
pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
|
|
|
|
|
|
|
|
while (pll_ctl) {
|
|
|
|
pll_ctl = pll_ctl >> 1;
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
p--;
|
|
|
|
|
|
|
|
if (!p) {
|
|
|
|
DRM_ERROR("wrong P1 divisor\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
|
|
|
|
if (lfsr_converts[i] == pll_div)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == ARRAY_SIZE(lfsr_converts)) {
|
|
|
|
DRM_ERROR("wrong m_seed programmed\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
m = i + 62;
|
|
|
|
|
2015-05-13 15:35:25 +08:00
|
|
|
dsi_clock = (m * refclk) / (p * n);
|
2014-07-30 23:02:37 +08:00
|
|
|
|
|
|
|
/* pixel_format and pipe_bpp should agree */
|
|
|
|
assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
|
|
|
|
|
|
|
|
pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
|
|
|
|
|
|
|
|
return pclk;
|
|
|
|
}
|
2015-09-01 22:11:38 +08:00
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
|
|
|
|
struct intel_crtc_state *config)
|
2015-09-01 22:11:46 +08:00
|
|
|
{
|
|
|
|
u32 pclk;
|
|
|
|
u32 dsi_clk;
|
|
|
|
u32 dsi_ratio;
|
|
|
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-01 22:11:46 +08:00
|
|
|
|
|
|
|
/* Divide by zero */
|
|
|
|
if (!pipe_bpp) {
|
|
|
|
DRM_ERROR("Invalid BPP(0)\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
|
2015-09-01 22:11:46 +08:00
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
|
2015-09-01 22:11:46 +08:00
|
|
|
|
|
|
|
dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
|
|
|
|
|
|
|
|
/* pixel_format and pipe_bpp should agree */
|
|
|
|
assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
|
|
|
|
|
|
|
|
pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
|
|
|
|
return pclk;
|
|
|
|
}
|
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
|
|
|
|
struct intel_crtc_state *config)
|
2016-01-08 18:45:39 +08:00
|
|
|
{
|
2016-12-02 16:23:49 +08:00
|
|
|
if (IS_GEN9_LP(to_i915(encoder->base.dev)))
|
2016-04-13 03:14:35 +08:00
|
|
|
return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
|
2016-01-08 18:45:39 +08:00
|
|
|
else
|
2016-04-13 03:14:35 +08:00
|
|
|
return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
|
2016-01-08 18:45:39 +08:00
|
|
|
}
|
|
|
|
|
2015-10-05 16:21:11 +08:00
|
|
|
static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
|
2015-09-01 22:11:44 +08:00
|
|
|
{
|
|
|
|
u32 temp;
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-01 22:11:44 +08:00
|
|
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
|
|
|
|
|
|
|
temp = I915_READ(MIPI_CTRL(port));
|
|
|
|
temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
|
|
|
|
I915_WRITE(MIPI_CTRL(port), temp |
|
|
|
|
intel_dsi->escape_clk_div <<
|
|
|
|
ESCAPE_CLOCK_DIVIDER_SHIFT);
|
|
|
|
}
|
|
|
|
|
2017-02-17 20:43:34 +08:00
|
|
|
static void glk_dsi_program_esc_clock(struct drm_device *dev,
|
|
|
|
const struct intel_crtc_state *config)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
u32 dsi_rate = 0;
|
|
|
|
u32 pll_ratio = 0;
|
|
|
|
u32 ddr_clk = 0;
|
|
|
|
u32 div1_value = 0;
|
|
|
|
u32 div2_value = 0;
|
|
|
|
u32 txesc1_div = 0;
|
|
|
|
u32 txesc2_div = 0;
|
|
|
|
|
|
|
|
pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
|
|
|
|
|
|
|
|
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
|
|
|
|
|
|
|
|
ddr_clk = dsi_rate / 2;
|
|
|
|
|
|
|
|
/* Variable divider value */
|
|
|
|
div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
|
|
|
|
|
|
|
|
/* Calculate TXESC1 divider */
|
|
|
|
if (div1_value <= 10)
|
|
|
|
txesc1_div = div1_value;
|
|
|
|
else if ((div1_value > 10) && (div1_value <= 20))
|
|
|
|
txesc1_div = DIV_ROUND_UP(div1_value, 2);
|
|
|
|
else if ((div1_value > 20) && (div1_value <= 30))
|
|
|
|
txesc1_div = DIV_ROUND_UP(div1_value, 4);
|
|
|
|
else if ((div1_value > 30) && (div1_value <= 40))
|
|
|
|
txesc1_div = DIV_ROUND_UP(div1_value, 6);
|
|
|
|
else if ((div1_value > 40) && (div1_value <= 50))
|
|
|
|
txesc1_div = DIV_ROUND_UP(div1_value, 8);
|
|
|
|
else
|
|
|
|
txesc1_div = 10;
|
|
|
|
|
|
|
|
/* Calculate TXESC2 divider */
|
|
|
|
div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
|
|
|
|
|
|
|
|
if (div2_value < 10)
|
|
|
|
txesc2_div = div2_value;
|
|
|
|
else
|
|
|
|
txesc2_div = 10;
|
|
|
|
|
|
|
|
I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
|
|
|
|
I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
|
|
|
|
}
|
|
|
|
|
2015-09-24 01:57:17 +08:00
|
|
|
/* Program BXT Mipi clocks and dividers */
|
2016-04-13 03:14:35 +08:00
|
|
|
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
|
|
|
|
const struct intel_crtc_state *config)
|
2015-09-24 01:57:17 +08:00
|
|
|
{
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-02-16 01:13:57 +08:00
|
|
|
u32 tmp;
|
|
|
|
u32 dsi_rate = 0;
|
|
|
|
u32 pll_ratio = 0;
|
|
|
|
u32 rx_div;
|
|
|
|
u32 tx_div;
|
|
|
|
u32 rx_div_upper;
|
|
|
|
u32 rx_div_lower;
|
|
|
|
u32 mipi_8by3_divider;
|
2015-09-24 01:57:17 +08:00
|
|
|
|
|
|
|
/* Clear old configurations */
|
|
|
|
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
|
|
|
|
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
|
2016-02-16 01:13:57 +08:00
|
|
|
tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
|
|
|
|
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
|
|
|
|
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
|
2015-09-24 01:57:17 +08:00
|
|
|
|
|
|
|
/* Get the current DSI rate(actual) */
|
2016-04-13 03:14:35 +08:00
|
|
|
pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
|
2015-09-24 01:57:17 +08:00
|
|
|
dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
|
|
|
|
|
2016-02-16 01:13:57 +08:00
|
|
|
/*
|
|
|
|
* tx clock should be <= 20MHz and the div value must be
|
|
|
|
* subtracted by 1 as per bspec
|
|
|
|
*/
|
|
|
|
tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
|
|
|
|
/*
|
|
|
|
* rx clock should be <= 150MHz and the div value must be
|
|
|
|
* subtracted by 1 as per bspec
|
|
|
|
*/
|
|
|
|
rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
|
2015-09-24 01:57:17 +08:00
|
|
|
|
|
|
|
/*
|
2016-02-16 01:13:57 +08:00
|
|
|
* rx divider value needs to be updated in the
|
|
|
|
* two differnt bit fields in the register hence splitting the
|
|
|
|
* rx divider value accordingly
|
2015-09-24 01:57:17 +08:00
|
|
|
*/
|
2016-02-16 01:13:57 +08:00
|
|
|
rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
|
|
|
|
rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
|
|
|
|
|
2017-02-08 18:50:51 +08:00
|
|
|
mipi_8by3_divider = 0x2;
|
2015-09-24 01:57:17 +08:00
|
|
|
|
2016-02-16 01:13:57 +08:00
|
|
|
tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
|
|
|
|
tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
|
|
|
|
tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
|
|
|
|
tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
|
2015-09-24 01:57:17 +08:00
|
|
|
|
|
|
|
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
|
|
|
|
}
|
|
|
|
|
2017-02-17 20:43:32 +08:00
|
|
|
static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
|
2016-04-13 03:14:35 +08:00
|
|
|
struct intel_crtc_state *config)
|
2015-09-01 22:11:38 +08:00
|
|
|
{
|
2017-02-17 20:43:32 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-01 22:11:38 +08:00
|
|
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
2017-02-17 20:43:32 +08:00
|
|
|
u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
|
2015-09-01 22:11:38 +08:00
|
|
|
u32 dsi_clk;
|
|
|
|
|
|
|
|
dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
|
2016-04-13 03:14:35 +08:00
|
|
|
intel_dsi->lane_count);
|
2015-09-01 22:11:38 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* From clock diagram, to get PLL ratio divider, divide double of DSI
|
|
|
|
* link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
|
|
|
|
* round 'up' the result
|
|
|
|
*/
|
|
|
|
dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
|
2017-02-17 20:43:32 +08:00
|
|
|
|
|
|
|
if (IS_BROXTON(dev_priv)) {
|
|
|
|
dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
|
|
|
|
dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
|
|
|
|
} else {
|
|
|
|
dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
|
|
|
|
dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
|
2015-09-01 22:11:38 +08:00
|
|
|
DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
|
2016-04-13 03:14:35 +08:00
|
|
|
return -ECHRNG;
|
2017-02-17 20:43:32 +08:00
|
|
|
} else
|
|
|
|
DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
|
2015-09-01 22:11:38 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
|
|
|
|
* Spec says both have to be programmed, even if one is not getting
|
|
|
|
* used. Configure MIPI_CLOCK_CTL dividers in modeset
|
|
|
|
*/
|
2016-04-13 03:14:35 +08:00
|
|
|
config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
|
2015-09-01 22:11:38 +08:00
|
|
|
|
|
|
|
/* As per recommendation from hardware team,
|
|
|
|
* Prog PVD ratio =1 if dsi ratio <= 50
|
|
|
|
*/
|
2017-02-17 20:43:32 +08:00
|
|
|
if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
|
2016-04-13 03:14:35 +08:00
|
|
|
config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
|
2015-09-01 22:11:38 +08:00
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2015-09-01 22:11:38 +08:00
|
|
|
|
2017-02-17 20:43:34 +08:00
|
|
|
static void gen9lp_enable_dsi_pll(struct intel_encoder *encoder,
|
2016-04-13 03:14:35 +08:00
|
|
|
const struct intel_crtc_state *config)
|
2015-09-01 22:11:38 +08:00
|
|
|
{
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-24 01:57:17 +08:00
|
|
|
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
|
|
|
|
enum port port;
|
2015-09-01 22:11:38 +08:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
|
|
|
|
/* Configure PLL vales */
|
2016-04-13 03:14:36 +08:00
|
|
|
I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
|
|
|
|
POSTING_READ(BXT_DSI_PLL_CTL);
|
2015-09-01 22:11:38 +08:00
|
|
|
|
2015-09-24 01:57:17 +08:00
|
|
|
/* Program TX, RX, Dphy clocks */
|
2017-02-17 20:43:33 +08:00
|
|
|
if (IS_BROXTON(dev_priv)) {
|
|
|
|
for_each_dsi_port(port, intel_dsi->ports)
|
|
|
|
bxt_dsi_program_clocks(encoder->base.dev, port, config);
|
2017-02-17 20:43:34 +08:00
|
|
|
} else {
|
|
|
|
glk_dsi_program_esc_clock(encoder->base.dev, config);
|
2017-02-17 20:43:33 +08:00
|
|
|
}
|
2015-09-24 01:57:17 +08:00
|
|
|
|
2015-09-01 22:11:38 +08:00
|
|
|
/* Enable DSI PLL */
|
|
|
|
val = I915_READ(BXT_DSI_PLL_ENABLE);
|
|
|
|
val |= BXT_DSI_PLL_DO_ENABLE;
|
|
|
|
I915_WRITE(BXT_DSI_PLL_ENABLE, val);
|
|
|
|
|
|
|
|
/* Timeout and fail if PLL not locked */
|
2016-06-30 22:33:20 +08:00
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
BXT_DSI_PLL_ENABLE,
|
|
|
|
BXT_DSI_PLL_LOCKED,
|
|
|
|
BXT_DSI_PLL_LOCKED,
|
|
|
|
1)) {
|
2015-09-01 22:11:38 +08:00
|
|
|
DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("DSI PLL locked\n");
|
|
|
|
}
|
|
|
|
|
2016-03-24 18:41:40 +08:00
|
|
|
bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2016-12-02 16:23:49 +08:00
|
|
|
if (IS_GEN9_LP(dev_priv))
|
2016-03-24 18:41:40 +08:00
|
|
|
return bxt_dsi_pll_is_enabled(dev_priv);
|
|
|
|
|
|
|
|
MISSING_CASE(INTEL_DEVID(dev_priv));
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-04-13 03:14:35 +08:00
|
|
|
int intel_compute_dsi_pll(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *config)
|
|
|
|
{
|
2016-10-13 18:03:04 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2016-04-13 03:14:35 +08:00
|
|
|
|
2016-10-13 18:03:04 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2016-04-13 03:14:35 +08:00
|
|
|
return vlv_compute_dsi_pll(encoder, config);
|
2016-12-02 16:23:49 +08:00
|
|
|
else if (IS_GEN9_LP(dev_priv))
|
2017-02-17 20:43:32 +08:00
|
|
|
return gen9lp_compute_dsi_pll(encoder, config);
|
2016-04-13 03:14:35 +08:00
|
|
|
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_enable_dsi_pll(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *config)
|
2015-09-01 22:11:38 +08:00
|
|
|
{
|
2016-10-13 18:03:04 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-01 22:11:38 +08:00
|
|
|
|
2016-10-13 18:03:04 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2016-04-13 03:14:35 +08:00
|
|
|
vlv_enable_dsi_pll(encoder, config);
|
2016-12-02 16:23:49 +08:00
|
|
|
else if (IS_GEN9_LP(dev_priv))
|
2017-02-17 20:43:34 +08:00
|
|
|
gen9lp_enable_dsi_pll(encoder, config);
|
2015-09-01 22:11:38 +08:00
|
|
|
}
|
2015-09-01 22:11:39 +08:00
|
|
|
|
|
|
|
void intel_disable_dsi_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
2016-10-13 18:03:04 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-01 22:11:39 +08:00
|
|
|
|
2016-10-13 18:03:04 +08:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2015-09-01 22:11:39 +08:00
|
|
|
vlv_disable_dsi_pll(encoder);
|
2016-12-02 16:23:49 +08:00
|
|
|
else if (IS_GEN9_LP(dev_priv))
|
2015-09-01 22:11:39 +08:00
|
|
|
bxt_disable_dsi_pll(encoder);
|
|
|
|
}
|
2015-09-01 22:11:44 +08:00
|
|
|
|
2017-02-17 20:43:33 +08:00
|
|
|
static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
|
|
|
|
enum port port)
|
2015-09-01 22:11:44 +08:00
|
|
|
{
|
|
|
|
u32 tmp;
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 18:34:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-09-01 22:11:44 +08:00
|
|
|
|
|
|
|
/* Clear old configurations */
|
2017-02-17 20:43:33 +08:00
|
|
|
if (IS_BROXTON(dev_priv)) {
|
|
|
|
tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
|
|
|
|
tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
|
|
|
|
tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
|
|
|
|
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
|
|
|
|
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
|
|
|
|
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
|
2017-02-17 20:43:34 +08:00
|
|
|
} else {
|
|
|
|
tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
|
|
|
|
tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
|
|
|
|
I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
|
|
|
|
|
|
|
|
tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
|
|
|
|
tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
|
|
|
|
I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
|
2017-02-17 20:43:33 +08:00
|
|
|
}
|
2015-09-01 22:11:44 +08:00
|
|
|
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
|
|
|
|
{
|
2016-10-13 18:03:04 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-09-01 22:11:44 +08:00
|
|
|
|
2016-12-02 16:23:49 +08:00
|
|
|
if (IS_GEN9_LP(dev_priv))
|
2017-02-17 20:43:33 +08:00
|
|
|
gen9lp_dsi_reset_clocks(encoder, port);
|
2016-10-13 18:03:04 +08:00
|
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2015-09-01 22:11:44 +08:00
|
|
|
vlv_dsi_reset_clocks(encoder, port);
|
|
|
|
}
|