2011-04-04 14:10:00 +08:00
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/*
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2012-07-20 06:17:34 +08:00
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* Copyright 2012 Red Hat Inc.
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2011-04-04 14:10:00 +08:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2015-01-14 13:29:56 +08:00
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#include <engine/mpeg.h>
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2011-04-04 14:10:00 +08:00
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2012-07-20 06:17:34 +08:00
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#include <subdev/timer.h>
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2011-04-04 14:10:00 +08:00
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2012-07-20 06:17:34 +08:00
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struct nv50_mpeg_chan {
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2015-01-14 13:29:56 +08:00
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struct nvkm_mpeg_chan base;
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2012-07-20 06:17:34 +08:00
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};
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/*******************************************************************************
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* MPEG object classes
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******************************************************************************/
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2011-04-12 13:20:22 +08:00
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2011-04-04 14:10:00 +08:00
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static int
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2015-01-14 13:29:56 +08:00
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nv50_mpeg_object_ctor(struct nvkm_object *parent,
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struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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2011-04-04 14:10:00 +08:00
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{
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2015-01-14 13:29:56 +08:00
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struct nvkm_gpuobj *obj;
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2011-04-04 14:10:00 +08:00
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int ret;
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2015-01-14 13:29:56 +08:00
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ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
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16, 16, 0, &obj);
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2012-07-20 06:17:34 +08:00
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*pobject = nv_object(obj);
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2011-04-04 14:10:00 +08:00
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if (ret)
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return ret;
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2015-08-20 12:54:14 +08:00
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nvkm_kmap(obj);
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nvkm_wo32(obj, 0x00, nv_mclass(obj));
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nvkm_wo32(obj, 0x04, 0x00000000);
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nvkm_wo32(obj, 0x08, 0x00000000);
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nvkm_wo32(obj, 0x0c, 0x00000000);
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nvkm_done(obj);
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2011-04-04 14:10:00 +08:00
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return 0;
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}
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2015-01-14 13:29:56 +08:00
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struct nvkm_ofuncs
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2012-07-20 06:17:34 +08:00
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nv50_mpeg_ofuncs = {
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.ctor = nv50_mpeg_object_ctor,
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2015-01-14 13:29:56 +08:00
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.dtor = _nvkm_gpuobj_dtor,
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.init = _nvkm_gpuobj_init,
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.fini = _nvkm_gpuobj_fini,
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.rd32 = _nvkm_gpuobj_rd32,
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.wr32 = _nvkm_gpuobj_wr32,
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2012-07-20 06:17:34 +08:00
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};
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2011-04-04 14:10:00 +08:00
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2015-01-14 13:29:56 +08:00
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static struct nvkm_oclass
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2012-07-20 06:17:34 +08:00
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nv50_mpeg_sclass[] = {
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{ 0x3174, &nv50_mpeg_ofuncs },
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{}
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};
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2012-05-01 14:46:28 +08:00
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2012-07-20 06:17:34 +08:00
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/*******************************************************************************
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* PMPEG context
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******************************************************************************/
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2011-04-04 14:10:00 +08:00
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2012-07-20 06:17:34 +08:00
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int
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2015-01-14 13:29:56 +08:00
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nv50_mpeg_context_ctor(struct nvkm_object *parent,
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struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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2011-04-04 14:10:00 +08:00
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{
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2012-07-20 06:17:34 +08:00
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struct nv50_mpeg_chan *chan;
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2015-08-20 12:54:14 +08:00
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struct nvkm_gpuobj *image;
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2011-04-04 14:10:00 +08:00
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int ret;
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2015-01-14 13:29:56 +08:00
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ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4,
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0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
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2012-07-20 06:17:34 +08:00
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*pobject = nv_object(chan);
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2011-04-04 14:10:00 +08:00
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if (ret)
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return ret;
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2015-08-20 12:54:14 +08:00
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image = &chan->base.base.gpuobj;
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nvkm_kmap(image);
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nvkm_wo32(image, 0x0070, 0x00801ec1);
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nvkm_wo32(image, 0x007c, 0x0000037c);
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nvkm_done(image);
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2012-07-20 06:17:34 +08:00
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return 0;
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2011-04-04 14:10:00 +08:00
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}
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2015-01-14 13:29:56 +08:00
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static struct nvkm_oclass
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2012-07-20 06:17:34 +08:00
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nv50_mpeg_cclass = {
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.handle = NV_ENGCTX(MPEG, 0x50),
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2015-01-14 13:29:56 +08:00
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.ofuncs = &(struct nvkm_ofuncs) {
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2012-07-20 06:17:34 +08:00
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.ctor = nv50_mpeg_context_ctor,
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2015-01-14 13:29:56 +08:00
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.dtor = _nvkm_mpeg_context_dtor,
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.init = _nvkm_mpeg_context_init,
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.fini = _nvkm_mpeg_context_fini,
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.rd32 = _nvkm_mpeg_context_rd32,
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.wr32 = _nvkm_mpeg_context_wr32,
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2012-07-20 06:17:34 +08:00
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},
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};
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2011-04-04 14:10:00 +08:00
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2012-07-20 06:17:34 +08:00
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/*******************************************************************************
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* PMPEG engine/subdev functions
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******************************************************************************/
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2011-04-04 14:10:00 +08:00
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2012-07-20 06:17:34 +08:00
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void
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2015-01-14 13:29:56 +08:00
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nv50_mpeg_intr(struct nvkm_subdev *subdev)
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2011-04-04 14:10:00 +08:00
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{
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2015-08-20 12:54:08 +08:00
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struct nvkm_mpeg *mpeg = (void *)subdev;
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2015-08-20 12:54:10 +08:00
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struct nvkm_device *device = mpeg->engine.subdev.device;
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u32 stat = nvkm_rd32(device, 0x00b100);
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u32 type = nvkm_rd32(device, 0x00b230);
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u32 mthd = nvkm_rd32(device, 0x00b234);
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u32 data = nvkm_rd32(device, 0x00b238);
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2011-04-04 14:10:00 +08:00
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u32 show = stat;
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if (stat & 0x01000000) {
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/* happens on initial binding of the object */
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if (type == 0x00000020 && mthd == 0x0000) {
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2015-08-20 12:54:10 +08:00
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nvkm_wr32(device, 0x00b308, 0x00000100);
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2011-04-04 14:10:00 +08:00
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show &= ~0x01000000;
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}
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}
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2012-07-20 06:17:34 +08:00
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if (show) {
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2015-08-20 12:54:13 +08:00
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nvkm_info(subdev, "%08x %08x %08x %08x\n",
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stat, type, mthd, data);
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2011-04-04 14:10:00 +08:00
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}
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2015-08-20 12:54:10 +08:00
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nvkm_wr32(device, 0x00b100, stat);
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nvkm_wr32(device, 0x00b230, 0x00000001);
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2011-04-04 14:10:00 +08:00
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}
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2011-04-12 13:20:22 +08:00
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static void
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2015-01-14 13:29:56 +08:00
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nv50_vpe_intr(struct nvkm_subdev *subdev)
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2011-04-12 13:20:22 +08:00
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{
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2015-08-20 12:54:13 +08:00
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struct nvkm_device *device = subdev->device;
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2011-04-12 13:20:22 +08:00
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2015-08-20 12:54:10 +08:00
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if (nvkm_rd32(device, 0x00b100))
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2012-07-20 06:17:34 +08:00
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nv50_mpeg_intr(subdev);
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2015-08-20 12:54:10 +08:00
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if (nvkm_rd32(device, 0x00b800)) {
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u32 stat = nvkm_rd32(device, 0x00b800);
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2015-08-20 12:54:13 +08:00
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nvkm_info(subdev, "PMSRCH: %08x\n", stat);
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2015-08-20 12:54:10 +08:00
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nvkm_wr32(device, 0xb800, stat);
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2011-04-12 13:20:22 +08:00
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}
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}
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2012-07-20 06:17:34 +08:00
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static int
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2015-01-14 13:29:56 +08:00
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nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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2011-04-04 14:10:00 +08:00
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{
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2015-08-20 12:54:08 +08:00
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struct nvkm_mpeg *mpeg;
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2012-07-20 06:17:34 +08:00
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int ret;
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2011-04-04 14:10:00 +08:00
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2015-08-20 12:54:08 +08:00
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ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
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*pobject = nv_object(mpeg);
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2012-07-20 06:17:34 +08:00
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if (ret)
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return ret;
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2011-04-04 14:10:00 +08:00
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2015-08-20 12:54:08 +08:00
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nv_subdev(mpeg)->unit = 0x00400002;
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nv_subdev(mpeg)->intr = nv50_vpe_intr;
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nv_engine(mpeg)->cclass = &nv50_mpeg_cclass;
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nv_engine(mpeg)->sclass = nv50_mpeg_sclass;
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2012-07-20 06:17:34 +08:00
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return 0;
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2011-04-04 14:10:00 +08:00
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}
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int
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2015-01-14 13:29:56 +08:00
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nv50_mpeg_init(struct nvkm_object *object)
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2011-04-04 14:10:00 +08:00
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{
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2015-08-20 12:54:08 +08:00
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struct nvkm_mpeg *mpeg = (void *)object;
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2015-08-20 12:54:13 +08:00
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struct nvkm_subdev *subdev = &mpeg->engine.subdev;
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struct nvkm_device *device = subdev->device;
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2012-07-20 06:17:34 +08:00
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int ret;
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2015-08-20 12:54:08 +08:00
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ret = nvkm_mpeg_init(mpeg);
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2012-07-20 06:17:34 +08:00
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if (ret)
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return ret;
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2015-08-20 12:54:10 +08:00
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nvkm_wr32(device, 0x00b32c, 0x00000000);
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nvkm_wr32(device, 0x00b314, 0x00000100);
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nvkm_wr32(device, 0x00b0e0, 0x0000001a);
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2012-07-20 06:17:34 +08:00
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2015-08-20 12:54:10 +08:00
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nvkm_wr32(device, 0x00b220, 0x00000044);
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nvkm_wr32(device, 0x00b300, 0x00801ec1);
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nvkm_wr32(device, 0x00b390, 0x00000000);
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nvkm_wr32(device, 0x00b394, 0x00000000);
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nvkm_wr32(device, 0x00b398, 0x00000000);
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nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001);
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2012-07-20 06:17:34 +08:00
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2015-08-20 12:54:10 +08:00
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nvkm_wr32(device, 0x00b100, 0xffffffff);
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nvkm_wr32(device, 0x00b140, 0xffffffff);
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2012-07-20 06:17:34 +08:00
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2015-08-20 12:54:11 +08:00
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x00b200) & 0x00000001))
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break;
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) < 0) {
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2015-08-20 12:54:13 +08:00
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nvkm_error(subdev, "timeout %08x\n",
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nvkm_rd32(device, 0x00b200));
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2012-07-20 06:17:34 +08:00
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return -EBUSY;
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2011-04-12 13:20:22 +08:00
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}
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2011-04-04 14:10:00 +08:00
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return 0;
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}
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2012-07-20 06:17:34 +08:00
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2015-01-14 13:29:56 +08:00
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struct nvkm_oclass
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2012-07-20 06:17:34 +08:00
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nv50_mpeg_oclass = {
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.handle = NV_ENGINE(MPEG, 0x50),
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2015-01-14 13:29:56 +08:00
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.ofuncs = &(struct nvkm_ofuncs) {
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2012-07-20 06:17:34 +08:00
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.ctor = nv50_mpeg_ctor,
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2015-01-14 13:29:56 +08:00
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.dtor = _nvkm_mpeg_dtor,
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2012-07-20 06:17:34 +08:00
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.init = nv50_mpeg_init,
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2015-01-14 13:29:56 +08:00
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.fini = _nvkm_mpeg_fini,
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2012-07-20 06:17:34 +08:00
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},
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};
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