2015-06-14 06:41:25 +08:00
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/*
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* Xtensa Performance Monitor Module driver
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* See Tensilica Debug User's Guide for PMU registers documentation.
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*
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* Copyright (C) 2015 Cadence Design Systems Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <asm/processor.h>
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#include <asm/stacktrace.h>
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/* Global control/status for all perf counters */
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#define XTENSA_PMU_PMG 0x1000
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/* Perf counter values */
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#define XTENSA_PMU_PM(i) (0x1080 + (i) * 4)
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/* Perf counter control registers */
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#define XTENSA_PMU_PMCTRL(i) (0x1100 + (i) * 4)
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/* Perf counter status registers */
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#define XTENSA_PMU_PMSTAT(i) (0x1180 + (i) * 4)
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#define XTENSA_PMU_PMG_PMEN 0x1
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#define XTENSA_PMU_COUNTER_MASK 0xffffffffULL
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#define XTENSA_PMU_COUNTER_MAX 0x7fffffff
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#define XTENSA_PMU_PMCTRL_INTEN 0x00000001
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#define XTENSA_PMU_PMCTRL_KRNLCNT 0x00000008
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#define XTENSA_PMU_PMCTRL_TRACELEVEL 0x000000f0
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#define XTENSA_PMU_PMCTRL_SELECT_SHIFT 8
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#define XTENSA_PMU_PMCTRL_SELECT 0x00001f00
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#define XTENSA_PMU_PMCTRL_MASK_SHIFT 16
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#define XTENSA_PMU_PMCTRL_MASK 0xffff0000
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#define XTENSA_PMU_MASK(select, mask) \
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(((select) << XTENSA_PMU_PMCTRL_SELECT_SHIFT) | \
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((mask) << XTENSA_PMU_PMCTRL_MASK_SHIFT) | \
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XTENSA_PMU_PMCTRL_TRACELEVEL | \
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XTENSA_PMU_PMCTRL_INTEN)
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#define XTENSA_PMU_PMSTAT_OVFL 0x00000001
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#define XTENSA_PMU_PMSTAT_INTASRT 0x00000010
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struct xtensa_pmu_events {
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/* Array of events currently on this core */
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struct perf_event *event[XCHAL_NUM_PERF_COUNTERS];
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/* Bitmap of used hardware counters */
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unsigned long used_mask[BITS_TO_LONGS(XCHAL_NUM_PERF_COUNTERS)];
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};
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static DEFINE_PER_CPU(struct xtensa_pmu_events, xtensa_pmu_events);
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static const u32 xtensa_hw_ctl[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = XTENSA_PMU_MASK(0, 0x1),
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[PERF_COUNT_HW_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0xffff),
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[PERF_COUNT_HW_CACHE_REFERENCES] = XTENSA_PMU_MASK(10, 0x1),
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[PERF_COUNT_HW_CACHE_MISSES] = XTENSA_PMU_MASK(12, 0x1),
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/* Taken and non-taken branches + taken loop ends */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0x490),
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/* Instruction-related + other global stall cycles */
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XTENSA_PMU_MASK(4, 0x1ff),
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/* Data-related global stall cycles */
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = XTENSA_PMU_MASK(3, 0x1ff),
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};
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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static const u32 xtensa_cache_ctl[][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(10, 0x1),
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[C(RESULT_MISS)] = XTENSA_PMU_MASK(10, 0x2),
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(11, 0x1),
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[C(RESULT_MISS)] = XTENSA_PMU_MASK(11, 0x2),
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(8, 0x1),
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[C(RESULT_MISS)] = XTENSA_PMU_MASK(8, 0x2),
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(9, 0x1),
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[C(RESULT_MISS)] = XTENSA_PMU_MASK(9, 0x8),
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = XTENSA_PMU_MASK(7, 0x1),
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[C(RESULT_MISS)] = XTENSA_PMU_MASK(7, 0x8),
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},
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},
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};
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static int xtensa_pmu_cache_event(u64 config)
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{
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unsigned int cache_type, cache_op, cache_result;
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int ret;
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cache_type = (config >> 0) & 0xff;
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cache_op = (config >> 8) & 0xff;
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cache_result = (config >> 16) & 0xff;
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if (cache_type >= ARRAY_SIZE(xtensa_cache_ctl) ||
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cache_op >= C(OP_MAX) ||
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cache_result >= C(RESULT_MAX))
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return -EINVAL;
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ret = xtensa_cache_ctl[cache_type][cache_op][cache_result];
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if (ret == 0)
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return -EINVAL;
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return ret;
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}
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static inline uint32_t xtensa_pmu_read_counter(int idx)
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{
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return get_er(XTENSA_PMU_PM(idx));
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}
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static inline void xtensa_pmu_write_counter(int idx, uint32_t v)
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{
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set_er(v, XTENSA_PMU_PM(idx));
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}
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static void xtensa_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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uint64_t prev_raw_count, new_raw_count;
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int64_t delta;
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do {
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = xtensa_pmu_read_counter(event->hw.idx);
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} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count);
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delta = (new_raw_count - prev_raw_count) & XTENSA_PMU_COUNTER_MASK;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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}
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static bool xtensa_perf_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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bool rc = false;
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s64 left;
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if (!is_sampling_event(event)) {
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left = XTENSA_PMU_COUNTER_MAX;
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} else {
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s64 period = hwc->sample_period;
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left = local64_read(&hwc->period_left);
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if (left <= -period) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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rc = true;
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} else if (left <= 0) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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rc = true;
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}
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if (left > XTENSA_PMU_COUNTER_MAX)
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left = XTENSA_PMU_COUNTER_MAX;
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}
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local64_set(&hwc->prev_count, -left);
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xtensa_pmu_write_counter(idx, -left);
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perf_event_update_userpage(event);
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return rc;
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}
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static void xtensa_pmu_enable(struct pmu *pmu)
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{
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set_er(get_er(XTENSA_PMU_PMG) | XTENSA_PMU_PMG_PMEN, XTENSA_PMU_PMG);
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}
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static void xtensa_pmu_disable(struct pmu *pmu)
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{
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set_er(get_er(XTENSA_PMU_PMG) & ~XTENSA_PMU_PMG_PMEN, XTENSA_PMU_PMG);
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}
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static int xtensa_pmu_event_init(struct perf_event *event)
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{
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int ret;
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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if (event->attr.config >= ARRAY_SIZE(xtensa_hw_ctl) ||
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xtensa_hw_ctl[event->attr.config] == 0)
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return -EINVAL;
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event->hw.config = xtensa_hw_ctl[event->attr.config];
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return 0;
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case PERF_TYPE_HW_CACHE:
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ret = xtensa_pmu_cache_event(event->attr.config);
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if (ret < 0)
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return ret;
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event->hw.config = ret;
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return 0;
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case PERF_TYPE_RAW:
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/* Not 'previous counter' select */
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if ((event->attr.config & XTENSA_PMU_PMCTRL_SELECT) ==
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(1 << XTENSA_PMU_PMCTRL_SELECT_SHIFT))
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return -EINVAL;
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event->hw.config = (event->attr.config &
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(XTENSA_PMU_PMCTRL_KRNLCNT |
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XTENSA_PMU_PMCTRL_TRACELEVEL |
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XTENSA_PMU_PMCTRL_SELECT |
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XTENSA_PMU_PMCTRL_MASK)) |
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XTENSA_PMU_PMCTRL_INTEN;
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return 0;
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default:
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return -ENOENT;
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}
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}
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/*
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* Starts/Stops a counter present on the PMU. The PMI handler
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* should stop the counter when perf_event_overflow() returns
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* !0. ->start() will be used to continue.
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*/
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static void xtensa_pmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (WARN_ON_ONCE(idx == -1))
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return;
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if (flags & PERF_EF_RELOAD) {
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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xtensa_perf_event_set_period(event, hwc, idx);
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}
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hwc->state = 0;
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set_er(hwc->config, XTENSA_PMU_PMCTRL(idx));
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}
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static void xtensa_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (!(hwc->state & PERF_HES_STOPPED)) {
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set_er(0, XTENSA_PMU_PMCTRL(idx));
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set_er(get_er(XTENSA_PMU_PMSTAT(idx)),
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XTENSA_PMU_PMSTAT(idx));
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hwc->state |= PERF_HES_STOPPED;
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}
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if ((flags & PERF_EF_UPDATE) &&
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!(event->hw.state & PERF_HES_UPTODATE)) {
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xtensa_perf_event_update(event, &event->hw, idx);
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event->hw.state |= PERF_HES_UPTODATE;
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}
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}
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/*
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* Adds/Removes a counter to/from the PMU, can be done inside
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* a transaction, see the ->*_txn() methods.
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*/
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static int xtensa_pmu_add(struct perf_event *event, int flags)
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{
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struct xtensa_pmu_events *ev = this_cpu_ptr(&xtensa_pmu_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (__test_and_set_bit(idx, ev->used_mask)) {
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idx = find_first_zero_bit(ev->used_mask,
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XCHAL_NUM_PERF_COUNTERS);
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if (idx == XCHAL_NUM_PERF_COUNTERS)
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return -EAGAIN;
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__set_bit(idx, ev->used_mask);
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hwc->idx = idx;
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}
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ev->event[idx] = event;
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (flags & PERF_EF_START)
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xtensa_pmu_start(event, PERF_EF_RELOAD);
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perf_event_update_userpage(event);
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return 0;
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}
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static void xtensa_pmu_del(struct perf_event *event, int flags)
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{
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struct xtensa_pmu_events *ev = this_cpu_ptr(&xtensa_pmu_events);
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xtensa_pmu_stop(event, PERF_EF_UPDATE);
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__clear_bit(event->hw.idx, ev->used_mask);
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perf_event_update_userpage(event);
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}
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static void xtensa_pmu_read(struct perf_event *event)
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{
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xtensa_perf_event_update(event, &event->hw, event->hw.idx);
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}
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static int callchain_trace(struct stackframe *frame, void *data)
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{
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struct perf_callchain_entry *entry = data;
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perf_callchain_store(entry, frame->pc);
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return 0;
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}
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void perf_callchain_kernel(struct perf_callchain_entry *entry,
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struct pt_regs *regs)
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{
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xtensa_backtrace_kernel(regs, PERF_MAX_STACK_DEPTH,
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callchain_trace, NULL, entry);
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}
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void perf_callchain_user(struct perf_callchain_entry *entry,
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struct pt_regs *regs)
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{
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xtensa_backtrace_user(regs, PERF_MAX_STACK_DEPTH,
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callchain_trace, entry);
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}
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void perf_event_print_debug(void)
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{
|
|
|
|
unsigned long flags;
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
pr_info("CPU#%d: PMG: 0x%08lx\n", smp_processor_id(),
|
|
|
|
get_er(XTENSA_PMU_PMG));
|
|
|
|
for (i = 0; i < XCHAL_NUM_PERF_COUNTERS; ++i)
|
|
|
|
pr_info("PM%d: 0x%08lx, PMCTRL%d: 0x%08lx, PMSTAT%d: 0x%08lx\n",
|
|
|
|
i, get_er(XTENSA_PMU_PM(i)),
|
|
|
|
i, get_er(XTENSA_PMU_PMCTRL(i)),
|
|
|
|
i, get_er(XTENSA_PMU_PMSTAT(i)));
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
2015-07-16 15:37:31 +08:00
|
|
|
irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_id)
|
2015-06-14 06:41:25 +08:00
|
|
|
{
|
|
|
|
irqreturn_t rc = IRQ_NONE;
|
|
|
|
struct xtensa_pmu_events *ev = this_cpu_ptr(&xtensa_pmu_events);
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = find_first_bit(ev->used_mask, XCHAL_NUM_PERF_COUNTERS);
|
|
|
|
i < XCHAL_NUM_PERF_COUNTERS;
|
|
|
|
i = find_next_bit(ev->used_mask, XCHAL_NUM_PERF_COUNTERS, i + 1)) {
|
|
|
|
uint32_t v = get_er(XTENSA_PMU_PMSTAT(i));
|
|
|
|
struct perf_event *event = ev->event[i];
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
u64 last_period;
|
|
|
|
|
|
|
|
if (!(v & XTENSA_PMU_PMSTAT_OVFL))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
set_er(v, XTENSA_PMU_PMSTAT(i));
|
|
|
|
xtensa_perf_event_update(event, hwc, i);
|
|
|
|
last_period = hwc->last_period;
|
|
|
|
if (xtensa_perf_event_set_period(event, hwc, i)) {
|
|
|
|
struct perf_sample_data data;
|
|
|
|
struct pt_regs *regs = get_irq_regs();
|
|
|
|
|
|
|
|
perf_sample_data_init(&data, 0, last_period);
|
|
|
|
if (perf_event_overflow(event, &data, regs))
|
|
|
|
xtensa_pmu_stop(event, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pmu xtensa_pmu = {
|
|
|
|
.pmu_enable = xtensa_pmu_enable,
|
|
|
|
.pmu_disable = xtensa_pmu_disable,
|
|
|
|
.event_init = xtensa_pmu_event_init,
|
|
|
|
.add = xtensa_pmu_add,
|
|
|
|
.del = xtensa_pmu_del,
|
|
|
|
.start = xtensa_pmu_start,
|
|
|
|
.stop = xtensa_pmu_stop,
|
|
|
|
.read = xtensa_pmu_read,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void xtensa_pmu_setup(void)
|
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
set_er(0, XTENSA_PMU_PMG);
|
|
|
|
for (i = 0; i < XCHAL_NUM_PERF_COUNTERS; ++i) {
|
|
|
|
set_er(0, XTENSA_PMU_PMCTRL(i));
|
|
|
|
set_er(get_er(XTENSA_PMU_PMSTAT(i)), XTENSA_PMU_PMSTAT(i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int xtensa_pmu_notifier(struct notifier_block *self,
|
|
|
|
unsigned long action, void *data)
|
|
|
|
{
|
|
|
|
switch (action & ~CPU_TASKS_FROZEN) {
|
|
|
|
case CPU_STARTING:
|
|
|
|
xtensa_pmu_setup();
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init xtensa_pmu_init(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int irq = irq_create_mapping(NULL, XCHAL_PROFILING_INTERRUPT);
|
|
|
|
|
|
|
|
perf_cpu_notifier(xtensa_pmu_notifier);
|
2015-07-16 15:37:31 +08:00
|
|
|
#if XTENSA_FAKE_NMI
|
|
|
|
enable_irq(irq);
|
|
|
|
#else
|
2015-06-14 06:41:25 +08:00
|
|
|
ret = request_irq(irq, xtensa_pmu_irq_handler, IRQF_PERCPU,
|
|
|
|
"pmu", NULL);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2015-07-16 15:37:31 +08:00
|
|
|
#endif
|
2015-06-14 06:41:25 +08:00
|
|
|
|
|
|
|
ret = perf_pmu_register(&xtensa_pmu, "cpu", PERF_TYPE_RAW);
|
|
|
|
if (ret)
|
|
|
|
free_irq(irq, NULL);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
early_initcall(xtensa_pmu_init);
|