2005-04-17 06:20:36 +08:00
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/*
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* linux/arch/x86_64/nmi.c
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*
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* NMI watchdog support on APIC systems
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*
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* Started by Ingo Molnar <mingo@redhat.com>
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*
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* Fixes:
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* Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
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* Mikael Pettersson : Power Management for local APIC NMI watchdog.
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* Pavel Machek and
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* Mikael Pettersson : PM converted to driver model. Disable/enable API.
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*/
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#include <linux/config.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/mc146818rtc.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/sysdev.h>
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#include <linux/nmi.h>
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#include <linux/sysctl.h>
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2006-02-04 04:50:41 +08:00
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#include <linux/kprobes.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/smp.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/nmi.h>
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#include <asm/msr.h>
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#include <asm/proto.h>
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#include <asm/kdebug.h>
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2005-05-17 12:53:34 +08:00
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#include <asm/local.h>
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2005-04-17 06:20:36 +08:00
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/*
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* lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
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* - it may be reserved by some other driver, or not
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* - when not reserved by some other driver, it may be used for
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* the NMI watchdog, or not
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*
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* This is maintained separately from nmi_active because the NMI
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* watchdog may also be driven from the I/O APIC timer.
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*/
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static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
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static unsigned int lapic_nmi_owner;
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#define LAPIC_NMI_WATCHDOG (1<<0)
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#define LAPIC_NMI_RESERVED (1<<1)
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/* nmi_active:
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* +1: the lapic NMI watchdog is active, but can be disabled
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* 0: the lapic NMI watchdog has not been set up, and cannot
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* be enabled
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* -1: the lapic NMI watchdog is disabled, but can be enabled
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*/
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int nmi_active; /* oprofile uses this */
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int panic_on_timeout;
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unsigned int nmi_watchdog = NMI_DEFAULT;
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static unsigned int nmi_hz = HZ;
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2005-05-17 12:53:34 +08:00
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static unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
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static unsigned int nmi_p4_cccr_val;
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2005-04-17 06:20:36 +08:00
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/* Note that these events don't tick when the CPU idles. This means
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the frequency varies with CPU load. */
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#define K7_EVNTSEL_ENABLE (1 << 22)
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#define K7_EVNTSEL_INT (1 << 20)
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#define K7_EVNTSEL_OS (1 << 17)
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#define K7_EVNTSEL_USR (1 << 16)
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#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
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#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
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2005-05-17 12:53:34 +08:00
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#define MSR_P4_MISC_ENABLE 0x1A0
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#define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
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#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
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#define MSR_P4_PERFCTR0 0x300
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#define MSR_P4_CCCR0 0x360
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#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
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#define P4_ESCR_OS (1<<3)
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#define P4_ESCR_USR (1<<2)
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#define P4_CCCR_OVF_PMI0 (1<<26)
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#define P4_CCCR_OVF_PMI1 (1<<27)
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#define P4_CCCR_THRESHOLD(N) ((N)<<20)
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#define P4_CCCR_COMPLEMENT (1<<19)
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#define P4_CCCR_COMPARE (1<<18)
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#define P4_CCCR_REQUIRED (3<<16)
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#define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
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#define P4_CCCR_ENABLE (1<<12)
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/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
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CRU_ESCR0 (with any non-null event selector) through a complemented
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max threshold. [IA32-Vol3, Section 14.9.9] */
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#define MSR_P4_IQ_COUNTER0 0x30C
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#define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
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#define P4_NMI_IQ_CCCR0 \
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(P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
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P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
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[PATCH] x86_64: Change init sections for CPU hotplug support
This patch adds __cpuinit and __cpuinitdata sections that need to exist past
boot to support cpu hotplug.
Caveat: This is done *only* for EM64T CPU Hotplug support, on request from
Andi Kleen. Much of the generic hotplug code in kernel, and none of the other
archs that support CPU hotplug today, i386, ia64, ppc64, s390 and parisc dont
mark sections with __cpuinit, but only mark them as __devinit, and
__devinitdata.
If someone is motivated to change generic code, we need to make sure all
existing hotplug code does not break, on other arch's that dont use __cpuinit,
and __cpudevinit.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Andi Kleen <ak@muc.de>
Acked-by: Zwane Mwaikambo <zwane@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-26 05:54:58 +08:00
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static __cpuinit inline int nmi_known_cpu(void)
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2005-05-17 12:53:34 +08:00
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{
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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return boot_cpu_data.x86 == 15;
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case X86_VENDOR_INTEL:
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return boot_cpu_data.x86 == 15;
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}
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return 0;
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}
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2005-04-17 06:20:36 +08:00
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/* Run after command line and cpu_init init, but before all other checks */
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[PATCH] x86_64: Change init sections for CPU hotplug support
This patch adds __cpuinit and __cpuinitdata sections that need to exist past
boot to support cpu hotplug.
Caveat: This is done *only* for EM64T CPU Hotplug support, on request from
Andi Kleen. Much of the generic hotplug code in kernel, and none of the other
archs that support CPU hotplug today, i386, ia64, ppc64, s390 and parisc dont
mark sections with __cpuinit, but only mark them as __devinit, and
__devinitdata.
If someone is motivated to change generic code, we need to make sure all
existing hotplug code does not break, on other arch's that dont use __cpuinit,
and __cpudevinit.
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Acked-by: Andi Kleen <ak@muc.de>
Acked-by: Zwane Mwaikambo <zwane@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-26 05:54:58 +08:00
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void __cpuinit nmi_watchdog_default(void)
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2005-04-17 06:20:36 +08:00
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{
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if (nmi_watchdog != NMI_DEFAULT)
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return;
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2005-05-17 12:53:34 +08:00
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if (nmi_known_cpu())
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nmi_watchdog = NMI_LOCAL_APIC;
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else
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2005-04-17 06:20:36 +08:00
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nmi_watchdog = NMI_IO_APIC;
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}
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2005-05-17 12:53:34 +08:00
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#ifdef CONFIG_SMP
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/* The performance counters used by NMI_LOCAL_APIC don't trigger when
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* the CPU is idle. To make sure the NMI watchdog really ticks on all
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* CPUs during the test make them busy.
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*/
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static __init void nmi_cpu_busy(void *data)
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2005-04-17 06:20:36 +08:00
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{
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2005-05-17 12:53:34 +08:00
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volatile int *endflag = data;
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local_irq_enable();
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/* Intentionally don't use cpu_relax here. This is
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to make sure that the performance counter really ticks,
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even if there is a simulator or similar that catches the
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pause instruction. On a real HT machine this is fine because
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all other CPUs are busy with "useless" delay loops and don't
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care if they get somewhat less cycles. */
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while (*endflag == 0)
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barrier();
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2005-04-17 06:20:36 +08:00
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}
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2005-05-17 12:53:34 +08:00
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#endif
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2005-04-17 06:20:36 +08:00
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2005-05-17 12:53:34 +08:00
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int __init check_nmi_watchdog (void)
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2005-04-17 06:20:36 +08:00
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{
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2005-05-17 12:53:34 +08:00
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volatile int endflag = 0;
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2005-05-17 12:53:19 +08:00
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int *counts;
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2005-04-17 06:20:36 +08:00
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int cpu;
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2005-05-17 12:53:34 +08:00
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counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
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if (!counts)
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return -1;
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2005-04-17 06:20:36 +08:00
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2005-05-17 12:53:34 +08:00
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printk(KERN_INFO "testing NMI watchdog ... ");
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2005-05-17 12:53:19 +08:00
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2006-01-12 05:45:45 +08:00
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#ifdef CONFIG_SMP
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2005-05-17 12:53:34 +08:00
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if (nmi_watchdog == NMI_LOCAL_APIC)
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smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
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2006-01-12 05:45:45 +08:00
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#endif
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2005-04-17 06:20:36 +08:00
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for (cpu = 0; cpu < NR_CPUS; cpu++)
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2006-01-12 05:45:39 +08:00
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counts[cpu] = cpu_pda(cpu)->__nmi_count;
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2005-04-17 06:20:36 +08:00
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local_irq_enable();
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mdelay((10*1000)/nmi_hz); // wait 10 ticks
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for (cpu = 0; cpu < NR_CPUS; cpu++) {
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2005-05-17 12:53:34 +08:00
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if (!cpu_online(cpu))
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continue;
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2006-01-12 05:45:39 +08:00
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if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
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2005-05-17 12:53:34 +08:00
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endflag = 1;
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printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
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2005-04-17 06:20:36 +08:00
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cpu,
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2005-05-17 12:53:34 +08:00
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counts[cpu],
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2006-01-12 05:45:39 +08:00
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cpu_pda(cpu)->__nmi_count);
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2005-04-17 06:20:36 +08:00
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nmi_active = 0;
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lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
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2005-05-17 12:53:34 +08:00
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nmi_perfctr_msr = 0;
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2005-05-17 12:53:19 +08:00
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kfree(counts);
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2005-04-17 06:20:36 +08:00
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return -1;
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}
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}
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2005-05-17 12:53:34 +08:00
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endflag = 1;
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2005-04-17 06:20:36 +08:00
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printk("OK.\n");
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/* now that we know it works we can reduce NMI frequency to
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something more reasonable; makes a difference in some configs */
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if (nmi_watchdog == NMI_LOCAL_APIC)
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nmi_hz = 1;
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2005-05-17 12:53:19 +08:00
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kfree(counts);
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2005-04-17 06:20:36 +08:00
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return 0;
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}
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int __init setup_nmi_watchdog(char *str)
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{
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int nmi;
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if (!strncmp(str,"panic",5)) {
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panic_on_timeout = 1;
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str = strchr(str, ',');
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if (!str)
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return 1;
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++str;
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}
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get_option(&str, &nmi);
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if (nmi >= NMI_INVALID)
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return 0;
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2005-05-17 12:53:34 +08:00
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nmi_watchdog = nmi;
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2005-04-17 06:20:36 +08:00
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return 1;
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}
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__setup("nmi_watchdog=", setup_nmi_watchdog);
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static void disable_lapic_nmi_watchdog(void)
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{
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if (nmi_active <= 0)
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return;
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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wrmsr(MSR_K7_EVNTSEL0, 0, 0);
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break;
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case X86_VENDOR_INTEL:
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2005-05-17 12:53:34 +08:00
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if (boot_cpu_data.x86 == 15) {
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wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
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wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
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}
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2005-04-17 06:20:36 +08:00
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break;
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}
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nmi_active = -1;
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/* tell do_nmi() and others that we're not active any more */
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nmi_watchdog = 0;
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}
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static void enable_lapic_nmi_watchdog(void)
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{
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if (nmi_active < 0) {
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nmi_watchdog = NMI_LOCAL_APIC;
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setup_apic_nmi_watchdog();
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}
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}
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int reserve_lapic_nmi(void)
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{
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unsigned int old_owner;
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spin_lock(&lapic_nmi_owner_lock);
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old_owner = lapic_nmi_owner;
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lapic_nmi_owner |= LAPIC_NMI_RESERVED;
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spin_unlock(&lapic_nmi_owner_lock);
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if (old_owner & LAPIC_NMI_RESERVED)
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return -EBUSY;
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if (old_owner & LAPIC_NMI_WATCHDOG)
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disable_lapic_nmi_watchdog();
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return 0;
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}
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void release_lapic_nmi(void)
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{
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unsigned int new_owner;
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spin_lock(&lapic_nmi_owner_lock);
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new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
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lapic_nmi_owner = new_owner;
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spin_unlock(&lapic_nmi_owner_lock);
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if (new_owner & LAPIC_NMI_WATCHDOG)
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enable_lapic_nmi_watchdog();
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}
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void disable_timer_nmi_watchdog(void)
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{
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if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
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return;
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disable_irq(0);
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unset_nmi_callback();
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nmi_active = -1;
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nmi_watchdog = NMI_NONE;
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}
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void enable_timer_nmi_watchdog(void)
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{
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if (nmi_active < 0) {
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nmi_watchdog = NMI_IO_APIC;
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touch_nmi_watchdog();
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nmi_active = 1;
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enable_irq(0);
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}
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}
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#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static int nmi_pm_active; /* nmi_active before suspend */
|
|
|
|
|
2005-09-04 06:56:56 +08:00
|
|
|
static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
nmi_pm_active = nmi_active;
|
|
|
|
disable_lapic_nmi_watchdog();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int lapic_nmi_resume(struct sys_device *dev)
|
|
|
|
{
|
|
|
|
if (nmi_pm_active > 0)
|
|
|
|
enable_lapic_nmi_watchdog();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct sysdev_class nmi_sysclass = {
|
|
|
|
set_kset_name("lapic_nmi"),
|
|
|
|
.resume = lapic_nmi_resume,
|
|
|
|
.suspend = lapic_nmi_suspend,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct sys_device device_lapic_nmi = {
|
|
|
|
.id = 0,
|
|
|
|
.cls = &nmi_sysclass,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init init_lapic_nmi_sysfs(void)
|
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error = sysdev_class_register(&nmi_sysclass);
|
|
|
|
if (!error)
|
|
|
|
error = sysdev_register(&device_lapic_nmi);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
/* must come after the local APIC's device_initcall() */
|
|
|
|
late_initcall(init_lapic_nmi_sysfs);
|
|
|
|
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Activate the NMI watchdog via the local APIC.
|
|
|
|
* Original code written by Keith Owens.
|
|
|
|
*/
|
|
|
|
|
2005-05-17 12:53:34 +08:00
|
|
|
static void clear_msr_range(unsigned int base, unsigned int n)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for(i = 0; i < n; ++i)
|
|
|
|
wrmsr(base+i, 0, 0);
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static void setup_k7_watchdog(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
unsigned int evntsel;
|
|
|
|
|
|
|
|
nmi_perfctr_msr = MSR_K7_PERFCTR0;
|
|
|
|
|
|
|
|
for(i = 0; i < 4; ++i) {
|
|
|
|
/* Simulator may not support it */
|
2005-05-17 12:53:34 +08:00
|
|
|
if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
|
|
|
|
nmi_perfctr_msr = 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
return;
|
2005-05-17 12:53:34 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
|
|
|
|
}
|
|
|
|
|
|
|
|
evntsel = K7_EVNTSEL_INT
|
|
|
|
| K7_EVNTSEL_OS
|
|
|
|
| K7_EVNTSEL_USR
|
|
|
|
| K7_NMI_EVENT;
|
|
|
|
|
|
|
|
wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
|
2005-09-13 16:25:51 +08:00
|
|
|
wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
|
2005-04-17 06:20:36 +08:00
|
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
|
|
|
evntsel |= K7_EVNTSEL_ENABLE;
|
|
|
|
wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
|
|
|
|
}
|
|
|
|
|
2005-05-17 12:53:34 +08:00
|
|
|
|
|
|
|
static int setup_p4_watchdog(void)
|
|
|
|
{
|
|
|
|
unsigned int misc_enable, dummy;
|
|
|
|
|
|
|
|
rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
|
|
|
|
if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
|
|
|
|
nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
if (smp_num_siblings == 2)
|
|
|
|
nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
|
|
|
|
clear_msr_range(0x3F1, 2);
|
|
|
|
/* MSR 0x3F0 seems to have a default value of 0xFC00, but current
|
|
|
|
docs doesn't fully define it, so leave it alone for now. */
|
|
|
|
if (boot_cpu_data.x86_model >= 0x3) {
|
|
|
|
/* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
|
|
|
|
clear_msr_range(0x3A0, 26);
|
|
|
|
clear_msr_range(0x3BC, 3);
|
|
|
|
} else {
|
|
|
|
clear_msr_range(0x3A0, 31);
|
|
|
|
}
|
|
|
|
clear_msr_range(0x3C0, 6);
|
|
|
|
clear_msr_range(0x3C8, 6);
|
|
|
|
clear_msr_range(0x3E0, 2);
|
|
|
|
clear_msr_range(MSR_P4_CCCR0, 18);
|
|
|
|
clear_msr_range(MSR_P4_PERFCTR0, 18);
|
|
|
|
|
|
|
|
wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
|
|
|
|
wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
|
2005-09-13 16:25:51 +08:00
|
|
|
Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
|
|
|
|
wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
|
2005-05-17 12:53:34 +08:00
|
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
|
|
|
wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
void setup_apic_nmi_watchdog(void)
|
|
|
|
{
|
|
|
|
switch (boot_cpu_data.x86_vendor) {
|
|
|
|
case X86_VENDOR_AMD:
|
2005-04-17 06:25:07 +08:00
|
|
|
if (boot_cpu_data.x86 != 15)
|
2005-04-17 06:20:36 +08:00
|
|
|
return;
|
|
|
|
if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
|
|
|
|
return;
|
|
|
|
setup_k7_watchdog();
|
|
|
|
break;
|
2005-05-17 12:53:34 +08:00
|
|
|
case X86_VENDOR_INTEL:
|
|
|
|
if (boot_cpu_data.x86 != 15)
|
|
|
|
return;
|
|
|
|
if (!setup_p4_watchdog())
|
|
|
|
return;
|
|
|
|
break;
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
|
|
|
|
nmi_active = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* the best way to detect whether a CPU has a 'hard lockup' problem
|
|
|
|
* is to check it's local APIC timer IRQ counts. If they are not
|
|
|
|
* changing then that CPU has some problem.
|
|
|
|
*
|
|
|
|
* as these watchdog NMI IRQs are generated on every CPU, we only
|
|
|
|
* have to check the current processor.
|
|
|
|
*/
|
|
|
|
|
2005-05-17 12:53:34 +08:00
|
|
|
static DEFINE_PER_CPU(unsigned, last_irq_sum);
|
|
|
|
static DEFINE_PER_CPU(local_t, alert_counter);
|
|
|
|
static DEFINE_PER_CPU(int, nmi_touch);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
void touch_nmi_watchdog (void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
2005-05-17 12:53:34 +08:00
|
|
|
* Tell other CPUs to reset their alert counters. We cannot
|
|
|
|
* do it ourselves because the alert count increase is not
|
|
|
|
* atomic.
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
|
|
|
|
for (i = 0; i < NR_CPUS; i++)
|
2005-05-17 12:53:34 +08:00
|
|
|
per_cpu(nmi_touch, i) = 1;
|
2005-09-07 06:16:27 +08:00
|
|
|
|
|
|
|
touch_softlockup_watchdog();
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2006-02-04 04:50:41 +08:00
|
|
|
void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2005-05-17 12:53:34 +08:00
|
|
|
int sum;
|
|
|
|
int touched = 0;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
sum = read_pda(apic_timer_irqs);
|
2005-05-17 12:53:34 +08:00
|
|
|
if (__get_cpu_var(nmi_touch)) {
|
|
|
|
__get_cpu_var(nmi_touch) = 0;
|
|
|
|
touched = 1;
|
|
|
|
}
|
|
|
|
if (!touched && __get_cpu_var(last_irq_sum) == sum) {
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
* Ayiee, looks like this CPU is stuck ...
|
|
|
|
* wait a few IRQs (5 seconds) before doing the oops ...
|
|
|
|
*/
|
2005-05-17 12:53:34 +08:00
|
|
|
local_inc(&__get_cpu_var(alert_counter));
|
|
|
|
if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
|
2005-04-17 06:20:36 +08:00
|
|
|
if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
|
|
|
|
== NOTIFY_STOP) {
|
2005-05-17 12:53:34 +08:00
|
|
|
local_set(&__get_cpu_var(alert_counter), 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
return;
|
2005-09-13 00:49:24 +08:00
|
|
|
}
|
|
|
|
die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
} else {
|
2005-05-17 12:53:34 +08:00
|
|
|
__get_cpu_var(last_irq_sum) = sum;
|
|
|
|
local_set(&__get_cpu_var(alert_counter), 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2005-05-17 12:53:34 +08:00
|
|
|
if (nmi_perfctr_msr) {
|
|
|
|
if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
|
|
|
|
/*
|
|
|
|
* P4 quirks:
|
|
|
|
* - An overflown perfctr will assert its interrupt
|
|
|
|
* until the OVF flag in its CCCR is cleared.
|
|
|
|
* - LVTPC is masked on interrupt and must be
|
|
|
|
* unmasked by the LVTPC handler.
|
|
|
|
*/
|
|
|
|
wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
|
|
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
|
|
|
}
|
2005-09-13 16:25:51 +08:00
|
|
|
wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
|
2005-05-17 12:53:34 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2006-02-04 04:50:41 +08:00
|
|
|
static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static nmi_callback_t nmi_callback = dummy_nmi_callback;
|
|
|
|
|
2006-02-04 04:50:41 +08:00
|
|
|
asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
|
|
|
int cpu = safe_smp_processor_id();
|
|
|
|
|
|
|
|
nmi_enter();
|
|
|
|
add_pda(__nmi_count,1);
|
2005-09-07 06:16:35 +08:00
|
|
|
if (!rcu_dereference(nmi_callback)(regs, cpu))
|
2005-04-17 06:20:36 +08:00
|
|
|
default_do_nmi(regs);
|
|
|
|
nmi_exit();
|
|
|
|
}
|
|
|
|
|
|
|
|
void set_nmi_callback(nmi_callback_t callback)
|
|
|
|
{
|
2005-09-07 06:16:35 +08:00
|
|
|
rcu_assign_pointer(nmi_callback, callback);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void unset_nmi_callback(void)
|
|
|
|
{
|
|
|
|
nmi_callback = dummy_nmi_callback;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYSCTL
|
|
|
|
|
|
|
|
static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
|
|
|
|
{
|
|
|
|
unsigned char reason = get_nmi_reason();
|
|
|
|
char buf[64];
|
|
|
|
|
|
|
|
if (!(reason & 0xc0)) {
|
|
|
|
sprintf(buf, "NMI received for unknown reason %02x\n", reason);
|
|
|
|
die_nmi(buf,regs);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* proc handler for /proc/sys/kernel/unknown_nmi_panic
|
|
|
|
*/
|
|
|
|
int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
|
|
|
|
void __user *buffer, size_t *length, loff_t *ppos)
|
|
|
|
{
|
|
|
|
int old_state;
|
|
|
|
|
|
|
|
old_state = unknown_nmi_panic;
|
|
|
|
proc_dointvec(table, write, file, buffer, length, ppos);
|
|
|
|
if (!!old_state == !!unknown_nmi_panic)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (unknown_nmi_panic) {
|
|
|
|
if (reserve_lapic_nmi() < 0) {
|
|
|
|
unknown_nmi_panic = 0;
|
|
|
|
return -EBUSY;
|
|
|
|
} else {
|
|
|
|
set_nmi_callback(unknown_nmi_panic_callback);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
release_lapic_nmi();
|
|
|
|
unset_nmi_callback();
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(nmi_active);
|
|
|
|
EXPORT_SYMBOL(nmi_watchdog);
|
|
|
|
EXPORT_SYMBOL(reserve_lapic_nmi);
|
|
|
|
EXPORT_SYMBOL(release_lapic_nmi);
|
|
|
|
EXPORT_SYMBOL(disable_timer_nmi_watchdog);
|
|
|
|
EXPORT_SYMBOL(enable_timer_nmi_watchdog);
|
|
|
|
EXPORT_SYMBOL(touch_nmi_watchdog);
|