2018-07-02 14:25:11 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (C) 2013, Analog Devices Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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2013-04-16 01:19:50 +08:00
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/dmaengine.h>
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#include <linux/slab.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/dma-mapping.h>
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#include <linux/of.h>
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#include <sound/dmaengine_pcm.h>
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2021-09-23 18:50:46 +08:00
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static unsigned int prealloc_buffer_size_kbytes = 512;
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module_param(prealloc_buffer_size_kbytes, uint, 0444);
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MODULE_PARM_DESC(prealloc_buffer_size_kbytes, "Preallocate DMA buffer size (KB).");
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2015-04-27 18:44:25 +08:00
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/*
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* The platforms dmaengine driver does not support reporting the amount of
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* bytes that are still left to transfer.
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*/
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#define SND_DMAENGINE_PCM_FLAG_NO_RESIDUE BIT(31)
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2013-10-08 21:07:59 +08:00
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static struct device *dmaengine_dma_dev(struct dmaengine_pcm *pcm,
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struct snd_pcm_substream *substream)
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{
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if (!pcm->chan[substream->stream])
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return NULL;
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return pcm->chan[substream->stream]->device->dev;
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}
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2013-04-16 01:19:50 +08:00
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/**
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* snd_dmaengine_pcm_prepare_slave_config() - Generic prepare_slave_config callback
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* @substream: PCM substream
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* @params: hw_params
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* @slave_config: DMA slave config to prepare
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*
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* This function can be used as a generic prepare_slave_config callback for
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* platforms which make use of the snd_dmaengine_dai_dma_data struct for their
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* DAI DMA data. Internally the function will first call
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* snd_hwparams_to_dma_slave_config to fill in the slave config based on the
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2023-09-23 00:15:47 +08:00
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* hw_params, followed by snd_dmaengine_pcm_set_config_from_dai_data to fill in
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* the remaining fields based on the DAI DMA data.
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2013-04-16 01:19:50 +08:00
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*/
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int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct dma_slave_config *slave_config)
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{
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2020-07-20 09:17:39 +08:00
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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2013-04-16 01:19:50 +08:00
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struct snd_dmaengine_dai_dma_data *dma_data;
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int ret;
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2022-09-20 14:32:16 +08:00
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if (rtd->dai_link->num_cpus > 1) {
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2020-02-25 21:39:16 +08:00
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dev_err(rtd->dev,
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"%s doesn't support Multi CPU yet\n", __func__);
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return -EINVAL;
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}
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2020-03-30 09:47:37 +08:00
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dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
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2013-04-16 01:19:50 +08:00
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ret = snd_hwparams_to_dma_slave_config(substream, params, slave_config);
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if (ret)
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return ret;
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snd_dmaengine_pcm_set_config_from_dai_data(substream, dma_data,
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slave_config);
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return 0;
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}
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EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_prepare_slave_config);
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2019-10-02 13:35:00 +08:00
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static int dmaengine_pcm_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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2013-04-16 01:19:50 +08:00
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{
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2018-01-29 10:41:09 +08:00
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struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
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2013-04-16 01:19:50 +08:00
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struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
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struct dma_slave_config slave_config;
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2022-05-02 21:13:35 +08:00
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int ret;
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2013-04-16 01:19:50 +08:00
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2022-05-02 21:13:35 +08:00
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if (!pcm->config->prepare_slave_config)
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return 0;
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2013-10-08 21:08:00 +08:00
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2022-05-02 21:13:35 +08:00
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memset(&slave_config, 0, sizeof(slave_config));
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2013-04-16 01:19:50 +08:00
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2022-05-02 21:13:35 +08:00
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ret = pcm->config->prepare_slave_config(substream, params, &slave_config);
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if (ret)
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return ret;
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2013-04-16 01:19:50 +08:00
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2022-05-02 21:13:35 +08:00
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return dmaengine_slave_config(chan, &slave_config);
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2013-04-16 01:19:50 +08:00
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}
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2019-10-02 13:35:00 +08:00
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static int
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dmaengine_pcm_set_runtime_hwparams(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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2013-04-16 01:19:50 +08:00
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{
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2020-07-20 09:17:39 +08:00
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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2018-01-29 10:41:09 +08:00
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struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
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2013-10-08 21:07:59 +08:00
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struct device *dma_dev = dmaengine_dma_dev(pcm, substream);
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2013-04-16 01:19:50 +08:00
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struct dma_chan *chan = pcm->chan[substream->stream];
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2013-10-08 21:07:59 +08:00
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struct snd_dmaengine_dai_dma_data *dma_data;
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struct snd_pcm_hardware hw;
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2013-04-16 01:19:50 +08:00
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2022-09-20 14:32:16 +08:00
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if (rtd->dai_link->num_cpus > 1) {
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2020-02-25 21:39:16 +08:00
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dev_err(rtd->dev,
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"%s doesn't support Multi CPU yet\n", __func__);
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return -EINVAL;
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}
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2022-05-02 21:13:35 +08:00
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if (pcm->config->pcm_hardware)
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2013-10-08 21:07:59 +08:00
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return snd_soc_set_runtime_hwparams(substream,
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2013-04-16 01:19:50 +08:00
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pcm->config->pcm_hardware);
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2020-03-30 09:47:37 +08:00
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dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
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2013-10-08 21:07:59 +08:00
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memset(&hw, 0, sizeof(hw));
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hw.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED;
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hw.periods_min = 2;
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hw.periods_max = UINT_MAX;
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2022-03-01 19:34:46 +08:00
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hw.period_bytes_min = dma_data->maxburst * DMA_SLAVE_BUSWIDTH_8_BYTES;
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if (!hw.period_bytes_min)
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hw.period_bytes_min = 256;
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2013-10-08 21:07:59 +08:00
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hw.period_bytes_max = dma_get_max_seg_size(dma_dev);
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hw.buffer_bytes_max = SIZE_MAX;
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hw.fifo_size = dma_data->fifo_size;
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2013-12-01 01:00:45 +08:00
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if (pcm->flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
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hw.info |= SNDRV_PCM_INFO_BATCH;
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2020-01-20 15:28:06 +08:00
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/**
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* FIXME: Remove the return value check to align with the code
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* before adding snd_dmaengine_pcm_refine_runtime_hwparams
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* function.
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*/
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snd_dmaengine_pcm_refine_runtime_hwparams(substream,
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dma_data,
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&hw,
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chan);
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2013-10-08 21:07:59 +08:00
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return snd_soc_set_runtime_hwparams(substream, &hw);
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2013-04-16 01:19:50 +08:00
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}
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2019-10-02 13:35:00 +08:00
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static int dmaengine_pcm_open(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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2013-04-16 01:19:50 +08:00
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{
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2018-01-29 10:41:09 +08:00
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struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
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2013-10-08 21:07:59 +08:00
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struct dma_chan *chan = pcm->chan[substream->stream];
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int ret;
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2013-04-16 01:19:50 +08:00
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2019-10-02 13:35:00 +08:00
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ret = dmaengine_pcm_set_runtime_hwparams(component, substream);
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2013-10-08 21:07:59 +08:00
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if (ret)
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return ret;
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return snd_dmaengine_pcm_open(substream, chan);
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2013-04-16 01:19:50 +08:00
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}
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2019-10-02 13:35:00 +08:00
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static int dmaengine_pcm_close(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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return snd_dmaengine_pcm_close(substream);
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}
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static int dmaengine_pcm_trigger(struct snd_soc_component *component,
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struct snd_pcm_substream *substream, int cmd)
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{
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return snd_dmaengine_pcm_trigger(substream, cmd);
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}
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2013-04-16 01:19:51 +08:00
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static struct dma_chan *dmaengine_pcm_compat_request_channel(
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2019-10-02 13:35:00 +08:00
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struct snd_soc_component *component,
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2013-04-16 01:19:51 +08:00
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struct snd_soc_pcm_runtime *rtd,
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struct snd_pcm_substream *substream)
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{
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2018-01-29 10:41:09 +08:00
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struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
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2013-10-20 04:38:26 +08:00
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struct snd_dmaengine_dai_dma_data *dma_data;
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2022-09-20 14:32:16 +08:00
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if (rtd->dai_link->num_cpus > 1) {
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2020-02-25 21:39:16 +08:00
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dev_err(rtd->dev,
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"%s doesn't support Multi CPU yet\n", __func__);
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return NULL;
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}
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2020-03-30 09:47:37 +08:00
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dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
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2013-04-16 01:19:51 +08:00
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2013-04-21 01:29:00 +08:00
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if ((pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX) && pcm->chan[0])
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return pcm->chan[0];
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2022-05-02 21:13:35 +08:00
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if (pcm->config->compat_request_channel)
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2013-04-16 01:19:51 +08:00
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return pcm->config->compat_request_channel(rtd, substream);
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2022-05-02 21:13:35 +08:00
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return snd_dmaengine_pcm_request_channel(pcm->config->compat_filter_fn,
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dma_data->filter_data);
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2013-04-16 01:19:51 +08:00
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}
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2015-04-27 18:44:25 +08:00
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static bool dmaengine_pcm_can_report_residue(struct device *dev,
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struct dma_chan *chan)
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2014-01-11 21:02:19 +08:00
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{
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struct dma_slave_caps dma_caps;
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int ret;
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ret = dma_get_slave_caps(chan, &dma_caps);
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2015-04-27 18:44:25 +08:00
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if (ret != 0) {
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dev_warn(dev, "Failed to get DMA channel capabilities, falling back to period counting: %d\n",
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ret);
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return false;
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}
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2014-01-11 21:02:19 +08:00
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if (dma_caps.residue_granularity == DMA_RESIDUE_GRANULARITY_DESCRIPTOR)
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return false;
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return true;
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}
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2019-10-02 13:35:00 +08:00
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static int dmaengine_pcm_new(struct snd_soc_component *component,
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struct snd_soc_pcm_runtime *rtd)
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2013-04-16 01:19:50 +08:00
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{
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2018-01-29 10:41:09 +08:00
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struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
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2013-04-16 01:19:50 +08:00
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const struct snd_dmaengine_pcm_config *config = pcm->config;
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2018-01-29 10:41:09 +08:00
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struct device *dev = component->dev;
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2013-10-08 21:08:00 +08:00
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size_t prealloc_buffer_size;
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size_t max_buffer_size;
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2013-04-16 01:19:50 +08:00
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unsigned int i;
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2022-05-02 21:13:35 +08:00
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if (config->prealloc_buffer_size)
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2013-10-08 21:08:00 +08:00
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prealloc_buffer_size = config->prealloc_buffer_size;
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2022-01-20 10:44:02 +08:00
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else
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2021-09-23 18:50:46 +08:00
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prealloc_buffer_size = prealloc_buffer_size_kbytes * 1024;
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2022-01-20 10:44:02 +08:00
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2022-05-02 21:13:35 +08:00
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if (config->pcm_hardware && config->pcm_hardware->buffer_bytes_max)
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2022-01-20 10:44:02 +08:00
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max_buffer_size = config->pcm_hardware->buffer_bytes_max;
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else
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2013-10-08 21:08:00 +08:00
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max_buffer_size = SIZE_MAX;
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2020-02-17 16:28:32 +08:00
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for_each_pcm_streams(i) {
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2021-08-16 12:55:51 +08:00
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struct snd_pcm_substream *substream = rtd->pcm->streams[i].substream;
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2013-04-16 01:19:50 +08:00
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if (!substream)
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continue;
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2022-05-02 21:13:35 +08:00
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if (!pcm->chan[i] && config->chan_names[i])
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2017-01-17 21:16:41 +08:00
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pcm->chan[i] = dma_request_slave_channel(dev,
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2019-02-14 23:45:55 +08:00
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config->chan_names[i]);
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2017-01-17 21:16:41 +08:00
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2013-04-21 01:29:00 +08:00
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if (!pcm->chan[i] && (pcm->flags & SND_DMAENGINE_PCM_FLAG_COMPAT)) {
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2019-10-02 13:35:00 +08:00
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pcm->chan[i] = dmaengine_pcm_compat_request_channel(
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component, rtd, substream);
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2013-04-16 01:19:51 +08:00
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}
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2013-04-16 01:19:50 +08:00
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if (!pcm->chan[i]) {
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2018-01-29 10:41:09 +08:00
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dev_err(component->dev,
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2013-04-16 01:19:50 +08:00
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"Missing dma channel for stream: %d\n", i);
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2015-01-02 20:56:07 +08:00
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return -EINVAL;
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2013-04-16 01:19:50 +08:00
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}
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2019-12-10 22:26:01 +08:00
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snd_pcm_set_managed_buffer(substream,
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2013-11-07 14:45:16 +08:00
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SNDRV_DMA_TYPE_DEV_IRAM,
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2013-04-16 01:19:50 +08:00
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dmaengine_dma_dev(pcm, substream),
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2013-10-08 21:08:00 +08:00
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prealloc_buffer_size,
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max_buffer_size);
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2014-01-11 21:02:19 +08:00
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2015-04-27 18:44:25 +08:00
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if (!dmaengine_pcm_can_report_residue(dev, pcm->chan[i]))
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2014-01-11 21:02:19 +08:00
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pcm->flags |= SND_DMAENGINE_PCM_FLAG_NO_RESIDUE;
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2019-09-06 13:55:24 +08:00
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if (rtd->pcm->streams[i].pcm->name[0] == '\0') {
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2019-09-11 16:33:31 +08:00
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strscpy_pad(rtd->pcm->streams[i].pcm->name,
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rtd->pcm->streams[i].pcm->id,
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sizeof(rtd->pcm->streams[i].pcm->name));
|
2019-09-06 13:55:24 +08:00
|
|
|
}
|
2013-04-16 01:19:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-01-11 21:02:18 +08:00
|
|
|
static snd_pcm_uframes_t dmaengine_pcm_pointer(
|
2019-10-02 13:35:00 +08:00
|
|
|
struct snd_soc_component *component,
|
2014-01-11 21:02:18 +08:00
|
|
|
struct snd_pcm_substream *substream)
|
|
|
|
{
|
2018-01-29 10:41:09 +08:00
|
|
|
struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
|
2014-01-11 21:02:18 +08:00
|
|
|
|
|
|
|
if (pcm->flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
|
|
|
|
return snd_dmaengine_pcm_pointer_no_residue(substream);
|
|
|
|
else
|
|
|
|
return snd_dmaengine_pcm_pointer(substream);
|
|
|
|
}
|
|
|
|
|
2023-08-16 03:01:32 +08:00
|
|
|
static int dmaengine_copy(struct snd_soc_component *component,
|
|
|
|
struct snd_pcm_substream *substream,
|
|
|
|
int channel, unsigned long hwoff,
|
2023-08-31 21:04:57 +08:00
|
|
|
struct iov_iter *iter, unsigned long bytes)
|
2018-02-19 23:00:36 +08:00
|
|
|
{
|
|
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
|
|
struct dmaengine_pcm *pcm = soc_component_to_pcm(component);
|
|
|
|
int (*process)(struct snd_pcm_substream *substream,
|
|
|
|
int channel, unsigned long hwoff,
|
2023-08-31 21:04:56 +08:00
|
|
|
unsigned long bytes) = pcm->config->process;
|
2018-02-19 23:00:36 +08:00
|
|
|
bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
|
|
|
void *dma_ptr = runtime->dma_area + hwoff +
|
|
|
|
channel * (runtime->dma_bytes / runtime->channels);
|
|
|
|
|
|
|
|
if (is_playback)
|
2023-08-31 21:04:57 +08:00
|
|
|
if (copy_from_iter(dma_ptr, bytes, iter) != bytes)
|
2018-02-19 23:00:36 +08:00
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
if (process) {
|
2023-08-31 21:04:56 +08:00
|
|
|
int ret = process(substream, channel, hwoff, bytes);
|
2018-02-19 23:00:36 +08:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!is_playback)
|
2023-08-31 21:04:57 +08:00
|
|
|
if (copy_to_iter(dma_ptr, bytes, iter) != bytes)
|
2018-02-19 23:00:36 +08:00
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-10-02 13:35:00 +08:00
|
|
|
static const struct snd_soc_component_driver dmaengine_pcm_component = {
|
|
|
|
.name = SND_DMAENGINE_PCM_DRV_NAME,
|
|
|
|
.probe_order = SND_SOC_COMP_ORDER_LATE,
|
2013-04-16 01:19:50 +08:00
|
|
|
.open = dmaengine_pcm_open,
|
2019-10-02 13:35:00 +08:00
|
|
|
.close = dmaengine_pcm_close,
|
2013-04-16 01:19:50 +08:00
|
|
|
.hw_params = dmaengine_pcm_hw_params,
|
2019-10-02 13:35:00 +08:00
|
|
|
.trigger = dmaengine_pcm_trigger,
|
2014-01-11 21:02:18 +08:00
|
|
|
.pointer = dmaengine_pcm_pointer,
|
2019-10-02 13:35:00 +08:00
|
|
|
.pcm_construct = dmaengine_pcm_new,
|
2013-04-16 01:19:50 +08:00
|
|
|
};
|
|
|
|
|
2019-10-02 13:35:00 +08:00
|
|
|
static const struct snd_soc_component_driver dmaengine_pcm_component_process = {
|
|
|
|
.name = SND_DMAENGINE_PCM_DRV_NAME,
|
|
|
|
.probe_order = SND_SOC_COMP_ORDER_LATE,
|
2018-02-19 23:00:36 +08:00
|
|
|
.open = dmaengine_pcm_open,
|
2019-10-02 13:35:00 +08:00
|
|
|
.close = dmaengine_pcm_close,
|
2018-02-19 23:00:36 +08:00
|
|
|
.hw_params = dmaengine_pcm_hw_params,
|
2019-10-02 13:35:00 +08:00
|
|
|
.trigger = dmaengine_pcm_trigger,
|
2018-02-19 23:00:36 +08:00
|
|
|
.pointer = dmaengine_pcm_pointer,
|
2023-08-16 03:01:32 +08:00
|
|
|
.copy = dmaengine_copy,
|
2019-10-02 13:35:00 +08:00
|
|
|
.pcm_construct = dmaengine_pcm_new,
|
2018-02-19 23:00:36 +08:00
|
|
|
};
|
|
|
|
|
2013-04-16 01:19:50 +08:00
|
|
|
static const char * const dmaengine_pcm_dma_channel_names[] = {
|
|
|
|
[SNDRV_PCM_STREAM_PLAYBACK] = "tx",
|
|
|
|
[SNDRV_PCM_STREAM_CAPTURE] = "rx",
|
|
|
|
};
|
|
|
|
|
2013-12-11 02:11:02 +08:00
|
|
|
static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
|
ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
Add fields to struct snd_dmaengine_pcm_config to allow custom:
- DMA channel names.
This is useful when the default "tx" and "rx" channel names don't
apply, for example if a HW module supports multiple channels, each
having different DMA channel names. This is the case with the FIFOs
in Tegra's AHUB. This new facility can replace
SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.
- DMA device
This allows requesting DMA channels for a device other than the device
which is registering the "PCM" driver. This is quite unusual, but is
currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
module contains its own FIFOs which DMA writes to. However, in Tegra30,
the DMA FIFOs were split out AHUB HW module, which then routes the data
through a cross-bar, and into the DAI HW modules. However, the current
ASoC driver structure does not expose this detail, and acts as if the
FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
driver is registered with the DAI HW module, yet the DMA channels must
be looked up in the AHUB HW module's device tree node. This new config
field allows that to happen. Eventually, the Tegra drivers will be
reworked to fully expose the AHUB, and this config field can be
removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-04 05:26:34 +08:00
|
|
|
struct device *dev, const struct snd_dmaengine_pcm_config *config)
|
2013-04-21 01:29:00 +08:00
|
|
|
{
|
|
|
|
unsigned int i;
|
2013-12-04 05:26:32 +08:00
|
|
|
const char *name;
|
2013-12-11 02:11:02 +08:00
|
|
|
struct dma_chan *chan;
|
2013-04-21 01:29:00 +08:00
|
|
|
|
2019-02-14 23:45:55 +08:00
|
|
|
if ((pcm->flags & SND_DMAENGINE_PCM_FLAG_NO_DT) || (!dev->of_node &&
|
2022-05-02 21:13:35 +08:00
|
|
|
!(config->dma_dev && config->dma_dev->of_node)))
|
2013-12-11 02:11:02 +08:00
|
|
|
return 0;
|
2013-04-21 01:29:00 +08:00
|
|
|
|
2022-05-02 21:13:35 +08:00
|
|
|
if (config->dma_dev) {
|
ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
Add fields to struct snd_dmaengine_pcm_config to allow custom:
- DMA channel names.
This is useful when the default "tx" and "rx" channel names don't
apply, for example if a HW module supports multiple channels, each
having different DMA channel names. This is the case with the FIFOs
in Tegra's AHUB. This new facility can replace
SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.
- DMA device
This allows requesting DMA channels for a device other than the device
which is registering the "PCM" driver. This is quite unusual, but is
currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
module contains its own FIFOs which DMA writes to. However, in Tegra30,
the DMA FIFOs were split out AHUB HW module, which then routes the data
through a cross-bar, and into the DAI HW modules. However, the current
ASoC driver structure does not expose this detail, and acts as if the
FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
driver is registered with the DAI HW module, yet the DMA channels must
be looked up in the AHUB HW module's device tree node. This new config
field allows that to happen. Eventually, the Tegra drivers will be
reworked to fully expose the AHUB, and this config field can be
removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-04 05:26:34 +08:00
|
|
|
/*
|
|
|
|
* If this warning is seen, it probably means that your Linux
|
|
|
|
* device structure does not match your HW device structure.
|
|
|
|
* It would be best to refactor the Linux device structure to
|
|
|
|
* correctly match the HW structure.
|
|
|
|
*/
|
|
|
|
dev_warn(dev, "DMA channels sourced from device %s",
|
|
|
|
dev_name(config->dma_dev));
|
|
|
|
dev = config->dma_dev;
|
|
|
|
}
|
|
|
|
|
2020-02-17 16:28:32 +08:00
|
|
|
for_each_pcm_streams(i) {
|
2013-12-04 05:26:32 +08:00
|
|
|
if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
|
|
|
|
name = "rx-tx";
|
|
|
|
else
|
|
|
|
name = dmaengine_pcm_dma_channel_names[i];
|
2022-05-02 21:13:35 +08:00
|
|
|
if (config->chan_names[i])
|
ASoC: dmaengine: add custom DMA config to snd_dmaengine_pcm_config
Add fields to struct snd_dmaengine_pcm_config to allow custom:
- DMA channel names.
This is useful when the default "tx" and "rx" channel names don't
apply, for example if a HW module supports multiple channels, each
having different DMA channel names. This is the case with the FIFOs
in Tegra's AHUB. This new facility can replace
SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME.
- DMA device
This allows requesting DMA channels for a device other than the device
which is registering the "PCM" driver. This is quite unusual, but is
currently useful on Tegra. In much HW, and in Tegra20, each DAI HW
module contains its own FIFOs which DMA writes to. However, in Tegra30,
the DMA FIFOs were split out AHUB HW module, which then routes the data
through a cross-bar, and into the DAI HW modules. However, the current
ASoC driver structure does not expose this detail, and acts as if the
FIFOs are still part of the DAI HW modules. Consequently, the "PCM"
driver is registered with the DAI HW module, yet the DMA channels must
be looked up in the AHUB HW module's device tree node. This new config
field allows that to happen. Eventually, the Tegra drivers will be
reworked to fully expose the AHUB, and this config field can be
removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
2013-12-04 05:26:34 +08:00
|
|
|
name = config->chan_names[i];
|
2019-11-13 17:54:44 +08:00
|
|
|
chan = dma_request_chan(dev, name);
|
2013-12-11 02:11:02 +08:00
|
|
|
if (IS_ERR(chan)) {
|
2020-10-09 00:11:05 +08:00
|
|
|
/*
|
|
|
|
* Only report probe deferral errors, channels
|
|
|
|
* might not be present for devices that
|
|
|
|
* support only TX or only RX.
|
|
|
|
*/
|
2013-12-12 02:20:50 +08:00
|
|
|
if (PTR_ERR(chan) == -EPROBE_DEFER)
|
2013-12-11 02:11:02 +08:00
|
|
|
return -EPROBE_DEFER;
|
|
|
|
pcm->chan[i] = NULL;
|
|
|
|
} else {
|
|
|
|
pcm->chan[i] = chan;
|
|
|
|
}
|
2013-12-04 05:26:32 +08:00
|
|
|
if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
|
|
|
|
break;
|
2013-04-21 01:29:00 +08:00
|
|
|
}
|
2013-12-04 05:26:32 +08:00
|
|
|
|
|
|
|
if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
|
|
|
|
pcm->chan[1] = pcm->chan[0];
|
2013-12-11 02:11:02 +08:00
|
|
|
|
|
|
|
return 0;
|
2013-04-21 01:29:00 +08:00
|
|
|
}
|
|
|
|
|
2013-12-04 05:26:33 +08:00
|
|
|
static void dmaengine_pcm_release_chan(struct dmaengine_pcm *pcm)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
2020-02-17 16:28:32 +08:00
|
|
|
for_each_pcm_streams(i) {
|
2013-12-04 05:26:33 +08:00
|
|
|
if (!pcm->chan[i])
|
|
|
|
continue;
|
|
|
|
dma_release_channel(pcm->chan[i]);
|
|
|
|
if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-05-02 21:13:35 +08:00
|
|
|
static const struct snd_dmaengine_pcm_config snd_dmaengine_pcm_default_config = {
|
|
|
|
.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
|
|
|
|
};
|
|
|
|
|
2013-04-16 01:19:50 +08:00
|
|
|
/**
|
|
|
|
* snd_dmaengine_pcm_register - Register a dmaengine based PCM device
|
|
|
|
* @dev: The parent device for the PCM device
|
|
|
|
* @config: Platform specific PCM configuration
|
|
|
|
* @flags: Platform specific quirks
|
|
|
|
*/
|
|
|
|
int snd_dmaengine_pcm_register(struct device *dev,
|
|
|
|
const struct snd_dmaengine_pcm_config *config, unsigned int flags)
|
|
|
|
{
|
2020-07-31 22:41:46 +08:00
|
|
|
const struct snd_soc_component_driver *driver;
|
2013-04-16 01:19:50 +08:00
|
|
|
struct dmaengine_pcm *pcm;
|
2013-12-04 05:26:33 +08:00
|
|
|
int ret;
|
2013-04-16 01:19:50 +08:00
|
|
|
|
|
|
|
pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
|
|
|
|
if (!pcm)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2018-02-22 01:57:33 +08:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
pcm->component.debugfs_prefix = "dma";
|
|
|
|
#endif
|
2022-05-02 21:13:35 +08:00
|
|
|
if (!config)
|
|
|
|
config = &snd_dmaengine_pcm_default_config;
|
2013-04-16 01:19:50 +08:00
|
|
|
pcm->config = config;
|
2013-04-21 01:29:00 +08:00
|
|
|
pcm->flags = flags;
|
2013-04-16 01:19:50 +08:00
|
|
|
|
2013-12-11 02:11:02 +08:00
|
|
|
ret = dmaengine_pcm_request_chan_of(pcm, dev, config);
|
|
|
|
if (ret)
|
2018-02-27 02:55:25 +08:00
|
|
|
goto err_free_dma;
|
2013-04-16 01:19:50 +08:00
|
|
|
|
2022-05-02 21:13:35 +08:00
|
|
|
if (config->process)
|
2020-07-31 22:41:46 +08:00
|
|
|
driver = &dmaengine_pcm_component_process;
|
2018-02-19 23:00:36 +08:00
|
|
|
else
|
2020-07-31 22:41:46 +08:00
|
|
|
driver = &dmaengine_pcm_component;
|
|
|
|
|
|
|
|
ret = snd_soc_component_initialize(&pcm->component, driver, dev);
|
|
|
|
if (ret)
|
|
|
|
goto err_free_dma;
|
|
|
|
|
|
|
|
ret = snd_soc_add_component(&pcm->component, NULL, 0);
|
2013-12-04 05:26:33 +08:00
|
|
|
if (ret)
|
|
|
|
goto err_free_dma;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_free_dma:
|
|
|
|
dmaengine_pcm_release_chan(pcm);
|
|
|
|
kfree(pcm);
|
|
|
|
return ret;
|
2013-04-16 01:19:50 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* snd_dmaengine_pcm_unregister - Removes a dmaengine based PCM device
|
|
|
|
* @dev: Parent device the PCM was register with
|
|
|
|
*
|
|
|
|
* Removes a dmaengine based PCM device previously registered with
|
|
|
|
* snd_dmaengine_pcm_register.
|
|
|
|
*/
|
|
|
|
void snd_dmaengine_pcm_unregister(struct device *dev)
|
|
|
|
{
|
2018-01-29 10:41:09 +08:00
|
|
|
struct snd_soc_component *component;
|
2013-04-16 01:19:50 +08:00
|
|
|
struct dmaengine_pcm *pcm;
|
|
|
|
|
2018-01-29 10:41:09 +08:00
|
|
|
component = snd_soc_lookup_component(dev, SND_DMAENGINE_PCM_DRV_NAME);
|
|
|
|
if (!component)
|
2013-04-16 01:19:50 +08:00
|
|
|
return;
|
|
|
|
|
2018-01-29 10:41:09 +08:00
|
|
|
pcm = soc_component_to_pcm(component);
|
2013-04-16 01:19:50 +08:00
|
|
|
|
2020-07-07 15:42:37 +08:00
|
|
|
snd_soc_unregister_component_by_driver(dev, component->driver);
|
2013-12-04 05:26:33 +08:00
|
|
|
dmaengine_pcm_release_chan(pcm);
|
2013-04-16 01:19:50 +08:00
|
|
|
kfree(pcm);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_unregister);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|