2019-05-29 00:57:21 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-08-27 21:45:50 +08:00
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/*
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* Clocks for ux500 platforms
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*
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* Copyright (C) 2012 ST-Ericsson SA
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* Author: Ulf Hansson <ulf.hansson@linaro.org>
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*/
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#ifndef __UX500_CLK_H
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#define __UX500_CLK_H
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2013-04-03 20:26:57 +08:00
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#include <linux/device.h>
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2013-04-23 02:46:10 +08:00
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#include <linux/types.h>
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2012-08-27 21:45:50 +08:00
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2015-06-20 06:00:46 +08:00
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struct clk;
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2012-08-27 21:45:50 +08:00
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struct clk *clk_reg_prcc_pclk(const char *name,
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const char *parent_name,
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2013-04-23 02:46:10 +08:00
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resource_size_t phy_base,
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2012-08-27 21:45:50 +08:00
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u32 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcc_kclk(const char *name,
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const char *parent_name,
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2013-04-23 02:46:10 +08:00
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resource_size_t phy_base,
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2012-08-27 21:45:50 +08:00
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u32 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_scalable(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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struct clk *clk_reg_prcmu_gate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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2012-10-10 19:42:27 +08:00
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struct clk *clk_reg_prcmu_scalable_rate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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2012-08-31 20:21:29 +08:00
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struct clk *clk_reg_prcmu_rate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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2012-08-27 21:45:50 +08:00
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struct clk *clk_reg_prcmu_opp_gate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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2012-09-24 22:43:18 +08:00
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struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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2013-04-03 20:26:57 +08:00
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struct clk *clk_reg_sysctrl_gate(struct device *dev,
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const char *name,
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const char *parent_name,
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u16 reg_sel,
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u8 reg_mask,
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u8 reg_bits,
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unsigned long enable_delay_us,
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unsigned long flags);
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struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
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const char *name,
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const char *parent_name,
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u16 reg_sel,
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u8 reg_mask,
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u8 reg_bits,
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unsigned long rate,
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unsigned long enable_delay_us,
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unsigned long flags);
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struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
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const char *name,
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const char **parent_names,
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u8 num_parents,
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u16 *reg_sel,
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u8 *reg_mask,
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u8 *reg_bits,
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unsigned long flags);
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2012-08-27 21:45:50 +08:00
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#endif /* __UX500_CLK_H */
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