2019-07-26 20:51:24 +08:00
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==============
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2011-06-05 03:45:16 +08:00
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OpenRISC Linux
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==============
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This is a port of Linux to the OpenRISC class of microprocessors; the initial
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target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
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For information about OpenRISC processors and ongoing development:
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2019-07-26 20:51:24 +08:00
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======= =============================
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2020-07-10 14:20:19 +08:00
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website https://openrisc.io
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2017-10-21 21:39:09 +08:00
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email openrisc@lists.librecores.org
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2019-07-26 20:51:24 +08:00
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======= =============================
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2011-06-05 03:45:16 +08:00
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---------------------------------------------------------------------
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Build instructions for OpenRISC toolchain and Linux
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===================================================
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In order to build and run Linux for OpenRISC, you'll need at least a basic
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toolchain and, perhaps, the architectural simulator. Steps to get these bits
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in place are outlined here.
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2017-10-21 21:39:09 +08:00
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1) Toolchain
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Toolchain binaries can be obtained from openrisc.io or our github releases page.
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Instructions for building the different toolchains can be found on openrisc.io
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or Stafford's toolchain build and release scripts.
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2019-07-26 20:51:24 +08:00
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========== =================================================
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2017-10-21 21:39:09 +08:00
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binaries https://github.com/openrisc/or1k-gcc/releases
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toolchains https://openrisc.io/software
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building https://github.com/stffrdhrn/or1k-toolchain-build
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2019-07-26 20:51:24 +08:00
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========== =================================================
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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2) Building
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2011-06-05 03:45:16 +08:00
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2019-07-26 20:51:24 +08:00
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Build the Linux kernel as usual::
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2011-06-05 03:45:16 +08:00
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2020-01-31 16:28:33 +08:00
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make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig
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make ARCH=openrisc CROSS_COMPILE="or1k-linux-"
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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3) Running on FPGA (optional)
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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The OpenRISC community typically uses FuseSoC to manage building and programming
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an SoC into an FPGA. The below is an example of programming a De0 Nano
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development board with the OpenRISC SoC. During the build FPGA RTL is code
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downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
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tools. Binaries are loaded onto the board with openocd.
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2011-06-05 03:45:16 +08:00
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2019-07-26 20:51:24 +08:00
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::
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2017-10-21 21:39:09 +08:00
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git clone https://github.com/olofk/fusesoc
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cd fusesoc
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sudo pip install -e .
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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fusesoc init
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fusesoc build de0_nano
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fusesoc pgm de0_nano
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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openocd -f interface/altera-usb-blaster.cfg \
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-f board/or1k_generic.cfg
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telnet localhost 4444
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> init
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> halt; load_image vmlinux ; reset
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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4) Running on a Simulator (optional)
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2011-06-05 03:45:16 +08:00
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2017-10-21 21:39:09 +08:00
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QEMU is a processor emulator which we recommend for simulating the OpenRISC
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platform. Please follow the OpenRISC instructions on the QEMU website to get
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Linux running on QEMU. You can build QEMU yourself, but your Linux distribution
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likely provides binary packages to support OpenRISC.
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2011-06-05 03:45:16 +08:00
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2019-07-26 20:51:24 +08:00
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============= ======================================================
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2017-10-21 21:39:09 +08:00
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qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC
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2019-07-26 20:51:24 +08:00
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============= ======================================================
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2011-06-05 03:45:16 +08:00
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---------------------------------------------------------------------
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Terminology
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===========
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In the code, the following particles are used on symbols to limit the scope
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to more or less specific processor implementations:
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2019-07-26 20:51:24 +08:00
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========= =======================================
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2011-06-05 03:45:16 +08:00
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openrisc: the OpenRISC class of processors
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or1k: the OpenRISC 1000 family of processors
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or1200: the OpenRISC 1200 processor
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2019-07-26 20:51:24 +08:00
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========= =======================================
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2011-06-05 03:45:16 +08:00
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---------------------------------------------------------------------
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History
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========
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2019-07-26 20:51:24 +08:00
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18-11-2003 Matjaz Breskvar (phoenix@bsemi.com)
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2011-06-05 03:45:16 +08:00
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initial port of linux to OpenRISC/or32 architecture.
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all the core stuff is implemented and seams usable.
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2019-07-26 20:51:24 +08:00
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08-12-2003 Matjaz Breskvar (phoenix@bsemi.com)
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2011-06-05 03:45:16 +08:00
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complete change of TLB miss handling.
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rewrite of exceptions handling.
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fully functional sash-3.6 in default initrd.
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a much improved version with changes all around.
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2019-07-26 20:51:24 +08:00
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10-04-2004 Matjaz Breskvar (phoenix@bsemi.com)
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2011-06-05 03:45:16 +08:00
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alot of bugfixes all over.
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ethernet support, functional http and telnet servers.
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running many standard linux apps.
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2019-07-26 20:51:24 +08:00
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26-06-2004 Matjaz Breskvar (phoenix@bsemi.com)
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2011-06-05 03:45:16 +08:00
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port to 2.6.x
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2019-07-26 20:51:24 +08:00
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30-11-2004 Matjaz Breskvar (phoenix@bsemi.com)
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2011-06-05 03:45:16 +08:00
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lots of bugfixes and enhancments.
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added opencores framebuffer driver.
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2019-07-26 20:51:24 +08:00
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09-10-2010 Jonas Bonn (jonas@southpole.se)
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2011-06-05 03:45:16 +08:00
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major rewrite to bring up to par with upstream Linux 2.6.36
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