OpenCloudOS-Kernel/drivers/phy/cadence/Makefile

# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_CADENCE_DP)	+= phy-cadence-dp.o
obj-$(CONFIG_PHY_CADENCE_DPHY)	+= cdns-dphy.o
obj-$(CONFIG_PHY_CADENCE_SIERRA)	+= phy-cadence-sierra.o
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19 20:07:45 +08:00			`# SPDX-License-Identifier: GPL-2.0-only`
phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP DisplayPort Tx controller. Integration with the MHDP driver will be the subject of another commit. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 2018-08-09 18:30:30 +08:00			`obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o`
phy: Add Cadence D-PHY support Cadence has designed a D-PHY that can be used by the, currently in tree, DSI bridge (DRM), CSI Transceiver and CSI Receiver (v4l2) drivers. Only the DSI driver has an ad-hoc driver for that phy at the moment, while the v4l2 drivers are completely missing any phy support. In order to make that phy support available to all these drivers, without having to duplicate that code three times, let's create a generic phy framework driver. Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 2019-01-21 23:45:53 +08:00			`obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o`
phy: cadence: Add driver for Sierra PHY Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 2018-11-13 00:42:16 +08:00			`obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o`