2019-01-22 02:08:49 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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2018-04-19 10:05:18 +08:00
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/* Driver for Asix PHYs
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*
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* Author: Michael Schmitz <schmitzmic@gmail.com>
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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2021-06-07 16:27:22 +08:00
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#define PHY_ID_ASIX_AX88772A 0x003b1861
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#define PHY_ID_ASIX_AX88772C 0x003b1881
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2018-04-19 10:05:18 +08:00
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#define PHY_ID_ASIX_AX88796B 0x003b1841
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MODULE_DESCRIPTION("Asix PHY driver");
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MODULE_AUTHOR("Michael Schmitz <schmitzmic@gmail.com>");
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MODULE_LICENSE("GPL");
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/**
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* asix_soft_reset - software reset the PHY via BMCR_RESET bit
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* @phydev: target phy_device struct
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*
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* Description: Perform a software PHY reset using the standard
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* BMCR_RESET bit and poll for the reset bit to be cleared.
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* Toggle BMCR_RESET bit off to accommodate broken AX8796B PHY implementation
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* such as used on the Individual Computers' X-Surf 100 Zorro card.
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*
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* Returns: 0 on success, < 0 on failure
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*/
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static int asix_soft_reset(struct phy_device *phydev)
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{
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int ret;
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/* Asix PHY won't reset unless reset bit toggles */
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ret = phy_write(phydev, MII_BMCR, 0);
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if (ret < 0)
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return ret;
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return genphy_soft_reset(phydev);
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}
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2021-06-07 16:27:22 +08:00
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/* AX88772A is not working properly with some old switches (NETGEAR EN 108TP):
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* after autoneg is done and the link status is reported as active, the MII_LPA
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* register is 0. This issue is not reproducible on AX88772C.
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*/
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static int asix_ax88772a_read_status(struct phy_device *phydev)
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{
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int ret, val;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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if (!phydev->link)
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return 0;
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/* If MII_LPA is 0, phy_resolve_aneg_linkmode() will fail to resolve
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* linkmode so use MII_BMCR as default values.
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*/
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val = phy_read(phydev, MII_BMCR);
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if (val < 0)
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return val;
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if (val & BMCR_SPEED100)
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phydev->speed = SPEED_100;
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else
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phydev->speed = SPEED_10;
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if (val & BMCR_FULLDPLX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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ret = genphy_read_lpa(phydev);
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if (ret < 0)
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return ret;
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if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
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phy_resolve_aneg_linkmode(phydev);
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return 0;
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}
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static void asix_ax88772a_link_change_notify(struct phy_device *phydev)
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{
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/* Reset PHY, otherwise MII_LPA will provide outdated information.
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* This issue is reproducible only with some link partner PHYs
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*/
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if (phydev->state == PHY_NOLINK && phydev->drv->soft_reset)
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phydev->drv->soft_reset(phydev);
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}
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static struct phy_driver asix_driver[] = {
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{
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PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772A),
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.name = "Asix Electronics AX88772A",
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.flags = PHY_IS_INTERNAL,
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.read_status = asix_ax88772a_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.soft_reset = asix_soft_reset,
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.link_change_notify = asix_ax88772a_link_change_notify,
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}, {
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PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772C),
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.name = "Asix Electronics AX88772C",
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.flags = PHY_IS_INTERNAL,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.soft_reset = asix_soft_reset,
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}, {
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2018-04-19 10:05:18 +08:00
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.phy_id = PHY_ID_ASIX_AX88796B,
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.name = "Asix Electronics AX88796B",
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.phy_id_mask = 0xfffffff0,
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2019-04-13 02:47:03 +08:00
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/* PHY_BASIC_FEATURES */
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2018-04-19 10:05:18 +08:00
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.soft_reset = asix_soft_reset,
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} };
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module_phy_driver(asix_driver);
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static struct mdio_device_id __maybe_unused asix_tbl[] = {
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2021-06-07 16:27:22 +08:00
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{ PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772A) },
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{ PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772C) },
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2018-04-19 10:05:18 +08:00
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{ PHY_ID_ASIX_AX88796B, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, asix_tbl);
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