284 lines
8.1 KiB
C
284 lines
8.1 KiB
C
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/*
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* Performance counter support for POWER6 processors.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/perf_counter.h>
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#include <asm/reg.h>
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/*
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* Bits in event code for POWER6
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*/
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#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0x7
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#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
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#define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */
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#define PM_UNIT_MSK 0xf
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#define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH)
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#define PM_LLAV 0x8000 /* Load lookahead match value */
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#define PM_LLA 0x4000 /* Load lookahead match enable */
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#define PM_BYTE_SH 12 /* Byte of event bus to use */
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#define PM_BYTE_MSK 3
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#define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */
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#define PM_SUBUNIT_MSK 7
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#define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
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#define PM_PMCSEL_MSK 0xff /* PMCxSEL value */
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#define PM_BUSEVENT_MSK 0xf3700
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/*
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* Bits in MMCR1 for POWER6
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*/
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#define MMCR1_TTM0SEL_SH 60
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#define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
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#define MMCR1_TTMSEL_MSK 0xf
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#define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
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#define MMCR1_NESTSEL_SH 45
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#define MMCR1_NESTSEL_MSK 0x7
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#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
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#define MMCR1_PMC1_LLA ((u64)1 << 44)
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#define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39)
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#define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35)
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#define MMCR1_PMC1SEL_SH 24
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#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
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#define MMCR1_PMCSEL_MSK 0xff
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/*
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* Assign PMC numbers and compute MMCR1 value for a set of events
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*/
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static int p6_compute_mmcr(unsigned int event[], int n_ev,
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unsigned int hwc[], u64 mmcr[])
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{
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u64 mmcr1 = 0;
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int i;
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unsigned int pmc, ev, b, u, s, psel;
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unsigned int ttmset = 0;
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unsigned int pmc_inuse = 0;
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if (n_ev > 4)
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return -1;
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc_inuse & (1 << (pmc - 1)))
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return -1; /* collision! */
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pmc_inuse |= 1 << (pmc - 1);
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}
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}
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for (i = 0; i < n_ev; ++i) {
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ev = event[i];
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pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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--pmc;
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} else {
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/* can go on any PMC; find a free one */
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for (pmc = 0; pmc < 4; ++pmc)
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if (!(pmc_inuse & (1 << pmc)))
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break;
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pmc_inuse |= 1 << pmc;
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}
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hwc[i] = pmc;
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psel = ev & PM_PMCSEL_MSK;
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if (ev & PM_BUSEVENT_MSK) {
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/* this event uses the event bus */
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b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
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u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
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/* check for conflict on this byte of event bus */
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if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
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return -1;
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mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b);
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ttmset |= 1 << b;
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if (u == 5) {
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/* Nest events have a further mux */
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s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
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if ((ttmset & 0x10) &&
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MMCR1_NESTSEL(mmcr1) != s)
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return -1;
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ttmset |= 0x10;
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mmcr1 |= (u64)s << MMCR1_NESTSEL_SH;
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}
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if (0x30 <= psel && psel <= 0x3d) {
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/* these need the PMCx_ADDR_SEL bits */
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if (b >= 2)
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mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
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}
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/* bus select values are different for PMC3/4 */
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if (pmc >= 2 && (psel & 0x90) == 0x80)
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psel ^= 0x20;
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}
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if (ev & PM_LLA) {
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mmcr1 |= MMCR1_PMC1_LLA >> pmc;
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if (ev & PM_LLAV)
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mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
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}
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mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc);
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}
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mmcr[0] = 0;
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if (pmc_inuse & 1)
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mmcr[0] = MMCR0_PMC1CE;
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if (pmc_inuse & 0xe)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr[1] = mmcr1;
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mmcr[2] = 0;
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return 0;
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}
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/*
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* Layout of constraint bits:
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*
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* 0-1 add field: number of uses of PMC1 (max 1)
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* 2-3, 4-5, 6-7: ditto for PMC2, 3, 4
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* 8-10 select field: nest (subunit) event selector
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* 16-19 select field: unit on byte 0 of event bus
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* 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
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*/
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static int p6_get_constraint(unsigned int event, u64 *maskp, u64 *valp)
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{
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int pmc, byte, sh;
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unsigned int mask = 0, value = 0;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 4)
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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}
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if (event & PM_BUSEVENT_MSK) {
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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sh = byte * 4;
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mask |= PM_UNIT_MSKS << sh;
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value |= (event & PM_UNIT_MSKS) << sh;
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if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
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mask |= PM_SUBUNIT_MSKS;
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value |= event & PM_SUBUNIT_MSKS;
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}
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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#define MAX_ALT 4 /* at most 4 alternatives for any event */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */
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{ 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
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{ 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */
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{ 0x10000a, 0x2000f4 }, /* PM_RUN_CYC */
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{ 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */
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{ 0x10000e, 0x400010 }, /* PM_PURR */
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{ 0x100010, 0x4000f8 }, /* PM_FLUSH */
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{ 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */
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{ 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */
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{ 0x100054, 0x2000f0 }, /* PM_ST_FIN */
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{ 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */
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{ 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */
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{ 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */
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{ 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */
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{ 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */
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{ 0x200012, 0x300012 }, /* PM_INST_DISP */
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{ 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */
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{ 0x2000f8, 0x300010 }, /* PM_EXT_INT */
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{ 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */
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{ 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */
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{ 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */
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{ 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */
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{ 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */
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};
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/*
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* This could be made more efficient with a binary search on
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* a presorted list, if necessary
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*/
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static int find_alternatives_list(unsigned int event)
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{
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int i, j;
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unsigned int alt;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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return -1;
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for (j = 0; j < MAX_ALT; ++j) {
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alt = event_alternatives[i][j];
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if (!alt || event < alt)
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break;
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if (event == alt)
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return i;
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}
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}
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return -1;
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}
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static int p6_get_alternatives(unsigned int event, unsigned int alt[])
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{
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int i, j;
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unsigned int aevent, psel, pmc;
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unsigned int nalt = 1;
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alt[0] = event;
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/* check the alternatives table */
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i = find_alternatives_list(event);
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if (i >= 0) {
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/* copy out alternatives from list */
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for (j = 0; j < MAX_ALT; ++j) {
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aevent = event_alternatives[i][j];
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if (!aevent)
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break;
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if (aevent != event)
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alt[nalt++] = aevent;
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}
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} else {
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/* Check for alternative ways of computing sum events */
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/* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
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psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc && (psel == 0x32 || psel == 0x34))
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alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
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((5 - pmc) << PM_PMC_SH);
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/* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
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if (pmc && (psel == 0x38 || psel == 0x3a))
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alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
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((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
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}
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return nalt;
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}
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static void p6_disable_pmc(unsigned int pmc, u64 mmcr[])
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{
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/* Set PMCxSEL to 0 to disable PMCx */
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mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
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}
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static int power6_generic_events[] = {
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[PERF_COUNT_CPU_CYCLES] = 0x1e,
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[PERF_COUNT_INSTRUCTIONS] = 2,
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[PERF_COUNT_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */
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[PERF_COUNT_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */
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[PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */
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[PERF_COUNT_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
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};
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struct power_pmu power6_pmu = {
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.n_counter = 4,
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.max_alternatives = MAX_ALT,
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.add_fields = 0x55,
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.test_adder = 0,
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.compute_mmcr = p6_compute_mmcr,
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.get_constraint = p6_get_constraint,
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.get_alternatives = p6_get_alternatives,
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.disable_pmc = p6_disable_pmc,
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.n_generic = ARRAY_SIZE(power6_generic_events),
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.generic_events = power6_generic_events,
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};
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