2009-10-02 10:22:09 +08:00
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/*
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* SuperH Mobile SDHI
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*
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2016-02-15 23:01:48 +08:00
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* Copyright (C) 2016 Sang Engineering, Wolfram Sang
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* Copyright (C) 2015-16 Renesas Electronics Corporation
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2009-10-02 10:22:09 +08:00
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Based on "Compaq ASIC3 support":
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*
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* Copyright 2001 Compaq Computer Corporation.
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* Copyright 2004-2005 Phil Blundell
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* Copyright 2007-2008 OpenedHand Ltd.
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*
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* Authors: Phil Blundell <pb@handhelds.org>,
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* Samuel Ortiz <sameo@openedhand.com>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2012-05-02 00:03:43 +08:00
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#include <linux/mod_devicetable.h>
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2011-07-04 03:15:51 +08:00
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#include <linux/module.h>
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2013-02-15 23:13:56 +08:00
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#include <linux/of_device.h>
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2009-10-02 10:22:09 +08:00
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#include <linux/platform_device.h>
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2010-02-22 12:37:09 +08:00
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#include <linux/mmc/host.h>
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2009-10-02 10:22:09 +08:00
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#include <linux/mfd/tmio.h>
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2010-05-20 02:34:16 +08:00
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#include <linux/sh_dma.h>
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2011-06-21 07:00:10 +08:00
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#include <linux/delay.h>
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2016-04-01 23:44:37 +08:00
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/pinctrl-state.h>
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#include <linux/regulator/consumer.h>
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2009-10-02 10:22:09 +08:00
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2011-03-14 16:52:33 +08:00
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#include "tmio_mmc.h"
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2013-11-20 16:31:13 +08:00
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#define EXT_ACC 0xe4
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2016-05-11 20:46:00 +08:00
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#define SDHI_VER_GEN2_SDR50 0x490c
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/* very old datasheets said 0x490c for SDR104, too. They are wrong! */
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#define SDHI_VER_GEN2_SDR104 0xcb0d
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#define SDHI_VER_GEN3_SD 0xcc10
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#define SDHI_VER_GEN3_SDMMC 0xcd10
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2015-01-13 12:59:43 +08:00
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#define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data)
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2016-11-03 22:16:04 +08:00
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struct sh_mobile_sdhi_scc {
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unsigned long clk_rate; /* clock rate for SDR104 */
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u32 tap; /* sampling clock position for SDR104 */
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};
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2013-02-15 23:13:56 +08:00
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struct sh_mobile_sdhi_of_data {
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unsigned long tmio_flags;
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2016-09-12 22:15:05 +08:00
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u32 tmio_ocr_mask;
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2014-02-21 08:54:58 +08:00
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unsigned long capabilities;
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2014-02-21 08:55:27 +08:00
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unsigned long capabilities2;
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2015-01-13 13:00:07 +08:00
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enum dma_slave_buswidth dma_buswidth;
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2014-08-25 10:58:48 +08:00
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dma_addr_t dma_rx_offset;
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2016-02-15 23:01:48 +08:00
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unsigned bus_shift;
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2016-11-03 22:16:04 +08:00
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int scc_offset;
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struct sh_mobile_sdhi_scc *taps;
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int taps_num;
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2013-02-15 23:13:56 +08:00
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};
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2016-04-26 23:55:22 +08:00
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static const struct sh_mobile_sdhi_of_data of_default_cfg = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
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2013-02-15 23:13:56 +08:00
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};
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2016-09-12 22:15:07 +08:00
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static const struct sh_mobile_sdhi_of_data of_rz_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT,
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.tmio_ocr_mask = MMC_VDD_32_33,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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};
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2014-02-21 08:54:58 +08:00
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static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
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2014-08-25 11:03:00 +08:00
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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TMIO_MMC_CLK_ACTUAL,
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2014-02-21 08:54:58 +08:00
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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};
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2016-11-03 22:16:04 +08:00
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/* Definitions for sampling clocks */
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static struct sh_mobile_sdhi_scc rcar_gen2_scc_taps[] = {
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{
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.clk_rate = 156000000,
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.tap = 0x00000703,
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},
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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},
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};
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2014-02-21 08:55:27 +08:00
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static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
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2014-08-25 11:03:00 +08:00
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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2016-05-03 04:25:40 +08:00
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TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
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2014-02-21 08:55:27 +08:00
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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2015-01-13 13:00:07 +08:00
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.dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
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2014-08-25 10:58:48 +08:00
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.dma_rx_offset = 0x2000,
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2016-11-03 22:16:04 +08:00
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.scc_offset = 0x0300,
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.taps = rcar_gen2_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
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};
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/* Definitions for sampling clocks */
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static struct sh_mobile_sdhi_scc rcar_gen3_scc_taps[] = {
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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},
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2014-02-21 08:55:27 +08:00
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};
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2016-02-15 23:01:48 +08:00
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static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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2016-05-03 04:25:40 +08:00
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TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
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2016-05-09 23:01:07 +08:00
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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2016-02-15 23:01:48 +08:00
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.bus_shift = 2,
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2016-11-03 22:16:04 +08:00
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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2016-02-15 23:01:48 +08:00
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};
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2014-02-21 08:54:44 +08:00
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static const struct of_device_id sh_mobile_sdhi_of_match[] = {
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{ .compatible = "renesas,sdhi-shmobile" },
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2016-04-26 23:55:22 +08:00
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{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
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{ .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
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{ .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
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2016-09-12 22:15:07 +08:00
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{ .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
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2014-02-21 08:54:58 +08:00
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{ .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
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2014-02-21 08:55:12 +08:00
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{ .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
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2014-02-21 08:55:27 +08:00
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{ .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
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2014-02-21 08:55:40 +08:00
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{ .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
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2014-08-28 16:07:19 +08:00
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{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
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{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
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{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
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2016-02-15 23:01:48 +08:00
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
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2016-09-06 18:38:38 +08:00
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
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2014-02-21 08:54:44 +08:00
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{},
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};
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MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
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2009-10-02 10:22:09 +08:00
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struct sh_mobile_sdhi {
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struct clk *clk;
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struct tmio_mmc_data mmc_data;
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2010-05-20 02:34:16 +08:00
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struct tmio_mmc_dma dma_priv;
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2016-04-01 23:44:37 +08:00
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default, *pins_uhs;
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2016-11-03 22:16:04 +08:00
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void __iomem *scc_ctl;
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2009-10-02 10:22:09 +08:00
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};
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2015-01-13 13:00:07 +08:00
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static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
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{
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u32 val;
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/*
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* see also
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* sh_mobile_sdhi_of_data :: dma_buswidth
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*/
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switch (sd_ctrl_read16(host, CTL_VERSION)) {
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2016-05-11 20:46:00 +08:00
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case SDHI_VER_GEN2_SDR50:
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2015-01-13 13:00:07 +08:00
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val = (width == 32) ? 0x0001 : 0x0000;
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break;
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2016-05-11 20:46:00 +08:00
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case SDHI_VER_GEN2_SDR104:
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2015-01-13 13:00:07 +08:00
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val = (width == 32) ? 0x0000 : 0x0001;
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break;
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2016-05-11 20:46:00 +08:00
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case SDHI_VER_GEN3_SD:
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case SDHI_VER_GEN3_SDMMC:
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2016-02-15 23:01:48 +08:00
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if (width == 64)
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val = 0x0000;
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else if (width == 32)
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val = 0x0101;
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else
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val = 0x0001;
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break;
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2015-01-13 13:00:07 +08:00
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default:
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/* nothing to do */
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return;
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}
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sd_ctrl_write16(host, EXT_ACC, val);
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}
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2016-04-01 23:44:31 +08:00
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static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host)
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2012-06-21 01:10:32 +08:00
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{
|
2016-04-01 23:44:31 +08:00
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struct mmc_host *mmc = host->mmc;
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2015-01-13 12:59:43 +08:00
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struct sh_mobile_sdhi *priv = host_to_priv(host);
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2013-10-29 06:49:25 +08:00
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int ret = clk_prepare_enable(priv->clk);
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2012-06-21 01:10:32 +08:00
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if (ret < 0)
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return ret;
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2016-04-01 23:44:32 +08:00
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/*
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* The clock driver may not know what maximum frequency
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* actually works, so it should be set with the max-frequency
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* property which will already have been read to f_max. If it
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* was missing, assume the current frequency is the maximum.
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*/
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if (!mmc->f_max)
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mmc->f_max = clk_get_rate(priv->clk);
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/*
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* Minimum frequency is the minimum input clock frequency
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* divided by our maximum divider.
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*/
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mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
|
2015-01-13 13:00:07 +08:00
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/* enable 16bit data access on SDBUF as default */
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sh_mobile_sdhi_sdbuf_width(host, 16);
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2012-06-21 01:10:32 +08:00
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return 0;
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}
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|
2016-04-01 23:44:32 +08:00
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static unsigned int sh_mobile_sdhi_clk_update(struct tmio_mmc_host *host,
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unsigned int new_clock)
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{
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struct sh_mobile_sdhi *priv = host_to_priv(host);
|
2016-05-03 04:25:39 +08:00
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unsigned int freq, diff, best_freq = 0, diff_min = ~0;
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2016-05-03 04:25:42 +08:00
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int i, ret;
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2016-04-01 23:44:32 +08:00
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|
2016-05-03 04:25:41 +08:00
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/* tested only on RCar Gen2+ currently; may work for others */
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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return clk_get_rate(priv->clk);
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|
2016-04-01 23:44:32 +08:00
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/*
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* We want the bus clock to be as close as possible to, but no
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* greater than, new_clock. As we can divide by 1 << i for
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* any i in [0, 9] we want the input clock to be as close as
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* possible, but no greater than, new_clock << i.
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*/
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|
|
for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
|
|
|
|
freq = clk_round_rate(priv->clk, new_clock << i);
|
|
|
|
if (freq > (new_clock << i)) {
|
|
|
|
/* Too fast; look for a slightly slower option */
|
|
|
|
freq = clk_round_rate(priv->clk,
|
|
|
|
(new_clock << i) / 4 * 3);
|
|
|
|
if (freq > (new_clock << i))
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
diff = new_clock - (freq >> i);
|
|
|
|
if (diff <= diff_min) {
|
|
|
|
best_freq = freq;
|
|
|
|
diff_min = diff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-03 04:25:42 +08:00
|
|
|
ret = clk_set_rate(priv->clk, best_freq);
|
2016-04-01 23:44:32 +08:00
|
|
|
|
2016-05-03 04:25:42 +08:00
|
|
|
return ret == 0 ? best_freq : clk_get_rate(priv->clk);
|
2016-04-01 23:44:32 +08:00
|
|
|
}
|
|
|
|
|
2016-04-01 23:44:31 +08:00
|
|
|
static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host)
|
2012-06-21 01:10:32 +08:00
|
|
|
{
|
2015-01-13 12:59:43 +08:00
|
|
|
struct sh_mobile_sdhi *priv = host_to_priv(host);
|
2016-04-01 23:44:31 +08:00
|
|
|
|
2013-10-29 06:49:25 +08:00
|
|
|
clk_disable_unprepare(priv->clk);
|
2012-06-21 01:10:32 +08:00
|
|
|
}
|
|
|
|
|
2016-08-24 17:34:37 +08:00
|
|
|
static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_DAT0);
|
|
|
|
}
|
|
|
|
|
2016-04-01 23:44:37 +08:00
|
|
|
static int sh_mobile_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
|
|
|
|
struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
struct sh_mobile_sdhi *priv = host_to_priv(host);
|
|
|
|
struct pinctrl_state *pin_state;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (ios->signal_voltage) {
|
|
|
|
case MMC_SIGNAL_VOLTAGE_330:
|
|
|
|
pin_state = priv->pins_default;
|
|
|
|
break;
|
|
|
|
case MMC_SIGNAL_VOLTAGE_180:
|
|
|
|
pin_state = priv->pins_uhs;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If anything is missing, assume signal voltage is fixed at
|
|
|
|
* 3.3V and succeed/fail accordingly.
|
|
|
|
*/
|
|
|
|
if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
|
|
|
|
return ios->signal_voltage ==
|
|
|
|
MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
|
|
|
|
|
|
|
|
ret = mmc_regulator_set_vqmmc(host->mmc, ios);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-04-26 23:55:27 +08:00
|
|
|
return pinctrl_select_state(priv->pinctrl, pin_state);
|
2016-04-01 23:44:37 +08:00
|
|
|
}
|
|
|
|
|
2016-11-03 22:16:04 +08:00
|
|
|
/* SCC registers */
|
|
|
|
#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
|
|
|
|
#define SH_MOBILE_SDHI_SCC_TAPSET 0x002
|
|
|
|
#define SH_MOBILE_SDHI_SCC_DT2FF 0x004
|
|
|
|
#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
|
|
|
|
#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
|
|
|
|
#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
|
|
|
|
|
|
|
|
/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
|
|
|
|
#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
|
|
|
|
#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
|
|
|
|
#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
|
|
|
|
|
|
|
|
/* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
|
|
|
|
#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
|
|
|
|
/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
|
|
|
|
#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
|
|
|
|
/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
|
|
|
|
#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
|
|
|
|
|
|
|
|
static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
|
|
|
|
struct sh_mobile_sdhi *priv, int addr)
|
|
|
|
{
|
|
|
|
return readl(priv->scc_ctl + (addr << host->bus_shift));
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void sd_scc_write32(struct tmio_mmc_host *host,
|
|
|
|
struct sh_mobile_sdhi *priv,
|
|
|
|
int addr, u32 val)
|
|
|
|
{
|
|
|
|
writel(val, priv->scc_ctl + (addr << host->bus_shift));
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int sh_mobile_sdhi_init_tuning(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct sh_mobile_sdhi *priv;
|
|
|
|
|
|
|
|
priv = host_to_priv(host);
|
|
|
|
|
|
|
|
/* set sampling clock selection range */
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
|
|
|
|
0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
|
|
|
|
|
|
|
|
/* Initialize SCC */
|
|
|
|
sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
|
|
|
|
SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
|
|
|
|
|
|
|
|
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
|
|
|
|
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
|
|
|
|
SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
|
|
|
|
|
|
|
|
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
|
|
|
|
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
|
|
|
|
~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
|
|
|
|
|
|
|
|
/* Read TAPNUM */
|
|
|
|
return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
|
|
|
|
SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
|
|
|
|
SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_mobile_sdhi_prepare_tuning(struct tmio_mmc_host *host,
|
|
|
|
unsigned long tap)
|
|
|
|
{
|
|
|
|
struct sh_mobile_sdhi *priv = host_to_priv(host);
|
|
|
|
|
|
|
|
/* Set sampling clock position */
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define SH_MOBILE_SDHI_MAX_TAP 3
|
|
|
|
|
|
|
|
static int sh_mobile_sdhi_select_tuning(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct sh_mobile_sdhi *priv = host_to_priv(host);
|
|
|
|
unsigned long tap_cnt; /* counter of tuning success */
|
|
|
|
unsigned long tap_set; /* tap position */
|
|
|
|
unsigned long tap_start;/* start position of tuning success */
|
|
|
|
unsigned long tap_end; /* end position of tuning success */
|
|
|
|
unsigned long ntap; /* temporary counter of tuning success */
|
|
|
|
unsigned long i;
|
|
|
|
|
|
|
|
/* Clear SCC_RVSREQ */
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Find the longest consecutive run of successful probes. If that
|
|
|
|
* is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
|
|
|
|
* center index as the tap.
|
|
|
|
*/
|
|
|
|
tap_cnt = 0;
|
|
|
|
ntap = 0;
|
|
|
|
tap_start = 0;
|
|
|
|
tap_end = 0;
|
|
|
|
for (i = 0; i < host->tap_num * 2; i++) {
|
|
|
|
if (test_bit(i, host->taps))
|
|
|
|
ntap++;
|
|
|
|
else {
|
|
|
|
if (ntap > tap_cnt) {
|
|
|
|
tap_start = i - ntap;
|
|
|
|
tap_end = i - 1;
|
|
|
|
tap_cnt = ntap;
|
|
|
|
}
|
|
|
|
ntap = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ntap > tap_cnt) {
|
|
|
|
tap_start = i - ntap;
|
|
|
|
tap_end = i - 1;
|
|
|
|
tap_cnt = ntap;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
|
|
|
|
tap_set = (tap_start + tap_end) / 2 % host->tap_num;
|
|
|
|
else
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
/* Set SCC */
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
|
|
|
|
|
|
|
|
/* Enable auto re-tuning */
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
|
|
|
|
SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host)
|
|
|
|
{
|
2016-12-13 03:51:25 +08:00
|
|
|
struct sh_mobile_sdhi *priv = host_to_priv(host);
|
2016-11-03 22:16:04 +08:00
|
|
|
|
|
|
|
/* Check SCC error */
|
|
|
|
if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
|
|
|
|
SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
|
|
|
|
SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
|
|
|
|
/* Clear SCC error */
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_mobile_sdhi_hw_reset(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct sh_mobile_sdhi *priv;
|
|
|
|
|
|
|
|
priv = host_to_priv(host);
|
|
|
|
|
|
|
|
/* Reset SCC */
|
|
|
|
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
|
|
|
|
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
|
|
|
|
~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
|
|
|
|
|
|
|
|
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
|
|
|
|
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
|
|
|
|
~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
|
|
|
|
|
|
|
|
sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
|
|
|
|
~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
|
|
|
|
sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
|
|
|
|
}
|
|
|
|
|
2011-06-21 07:00:10 +08:00
|
|
|
static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
int timeout = 1000;
|
|
|
|
|
2016-04-28 00:51:26 +08:00
|
|
|
while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
|
|
|
|
& TMIO_STAT_SCLKDIVEN))
|
2011-06-21 07:00:10 +08:00
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
if (!timeout) {
|
2015-01-13 12:57:22 +08:00
|
|
|
dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
|
2011-06-21 07:00:10 +08:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_mobile_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
|
|
|
|
{
|
|
|
|
switch (addr)
|
|
|
|
{
|
|
|
|
case CTL_SD_CMD:
|
|
|
|
case CTL_STOP_INTERNAL_ACTION:
|
|
|
|
case CTL_XFER_BLK_COUNT:
|
|
|
|
case CTL_SD_CARD_CLK_CTL:
|
|
|
|
case CTL_SD_XFER_LEN:
|
|
|
|
case CTL_SD_MEM_CARD_OPT:
|
|
|
|
case CTL_TRANSACTION_CTL:
|
|
|
|
case CTL_DMA_ENABLE:
|
2014-04-25 17:14:17 +08:00
|
|
|
case EXT_ACC:
|
2011-06-21 07:00:10 +08:00
|
|
|
return sh_mobile_sdhi_wait_idle(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-09 14:45:46 +08:00
|
|
|
static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card,
|
|
|
|
unsigned int direction, int blk_size)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* In Renesas controllers, when performing a
|
|
|
|
* multiple block read of one or two blocks,
|
|
|
|
* depending on the timing with which the
|
|
|
|
* response register is read, the response
|
|
|
|
* value may not be read properly.
|
|
|
|
* Use single block read for this HW bug
|
|
|
|
*/
|
|
|
|
if ((direction == MMC_DATA_READ) &&
|
|
|
|
blk_size == 2)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return blk_size;
|
|
|
|
}
|
|
|
|
|
2015-01-13 12:59:56 +08:00
|
|
|
static void sh_mobile_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
|
|
|
|
{
|
|
|
|
sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0);
|
2015-01-13 13:00:07 +08:00
|
|
|
|
|
|
|
/* enable 32bit access if DMA mode if possibile */
|
|
|
|
sh_mobile_sdhi_sdbuf_width(host, enable ? 32 : 16);
|
2015-01-13 12:59:56 +08:00
|
|
|
}
|
|
|
|
|
2012-11-20 02:23:06 +08:00
|
|
|
static int sh_mobile_sdhi_probe(struct platform_device *pdev)
|
2009-10-02 10:22:09 +08:00
|
|
|
{
|
2016-12-13 03:51:20 +08:00
|
|
|
const struct sh_mobile_sdhi_of_data *of_data = of_device_get_match_data(&pdev->dev);
|
2009-10-02 10:22:09 +08:00
|
|
|
struct sh_mobile_sdhi *priv;
|
2010-05-20 02:34:16 +08:00
|
|
|
struct tmio_mmc_data *mmc_data;
|
2015-02-24 10:06:43 +08:00
|
|
|
struct tmio_mmc_data *mmd = pdev->dev.platform_data;
|
2011-03-14 16:52:33 +08:00
|
|
|
struct tmio_mmc_host *host;
|
2013-11-20 16:30:55 +08:00
|
|
|
struct resource *res;
|
2016-11-03 22:16:04 +08:00
|
|
|
int irq, ret, i;
|
2013-04-26 23:47:19 +08:00
|
|
|
struct tmio_mmc_dma *dma_priv;
|
2009-10-02 10:22:09 +08:00
|
|
|
|
2013-11-20 16:30:55 +08:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-02-15 23:13:58 +08:00
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(struct sh_mobile_sdhi), GFP_KERNEL);
|
2016-01-19 18:42:22 +08:00
|
|
|
if (!priv)
|
2009-10-02 10:22:09 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2010-05-20 02:34:16 +08:00
|
|
|
mmc_data = &priv->mmc_data;
|
2013-04-26 23:47:19 +08:00
|
|
|
dma_priv = &priv->dma_priv;
|
2010-05-20 02:34:16 +08:00
|
|
|
|
2013-02-15 23:13:58 +08:00
|
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
2009-10-02 10:22:09 +08:00
|
|
|
if (IS_ERR(priv->clk)) {
|
|
|
|
ret = PTR_ERR(priv->clk);
|
2012-11-28 17:24:21 +08:00
|
|
|
dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
|
2015-01-13 12:59:24 +08:00
|
|
|
goto eprobe;
|
2009-10-02 10:22:09 +08:00
|
|
|
}
|
|
|
|
|
2016-04-01 23:44:37 +08:00
|
|
|
priv->pinctrl = devm_pinctrl_get(&pdev->dev);
|
|
|
|
if (!IS_ERR(priv->pinctrl)) {
|
|
|
|
priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
|
|
|
|
PINCTRL_STATE_DEFAULT);
|
|
|
|
priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
|
|
|
|
"state_uhs");
|
|
|
|
}
|
|
|
|
|
2015-01-13 12:57:22 +08:00
|
|
|
host = tmio_mmc_host_alloc(pdev);
|
|
|
|
if (!host) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto eprobe;
|
|
|
|
}
|
|
|
|
|
2016-02-15 23:01:48 +08:00
|
|
|
|
2016-12-13 03:51:20 +08:00
|
|
|
if (of_data) {
|
2016-02-15 23:01:48 +08:00
|
|
|
mmc_data->flags |= of_data->tmio_flags;
|
2016-09-12 22:15:05 +08:00
|
|
|
mmc_data->ocr_mask = of_data->tmio_ocr_mask;
|
2016-02-15 23:01:48 +08:00
|
|
|
mmc_data->capabilities |= of_data->capabilities;
|
|
|
|
mmc_data->capabilities2 |= of_data->capabilities2;
|
|
|
|
mmc_data->dma_rx_offset = of_data->dma_rx_offset;
|
|
|
|
dma_priv->dma_buswidth = of_data->dma_buswidth;
|
|
|
|
host->bus_shift = of_data->bus_shift;
|
|
|
|
}
|
|
|
|
|
2015-01-13 12:57:33 +08:00
|
|
|
host->dma = dma_priv;
|
2015-01-13 12:57:42 +08:00
|
|
|
host->write16_hook = sh_mobile_sdhi_write16_hook;
|
2015-01-13 12:57:52 +08:00
|
|
|
host->clk_enable = sh_mobile_sdhi_clk_enable;
|
2016-04-01 23:44:32 +08:00
|
|
|
host->clk_update = sh_mobile_sdhi_clk_update;
|
2015-01-13 12:58:01 +08:00
|
|
|
host->clk_disable = sh_mobile_sdhi_clk_disable;
|
2015-01-13 12:58:10 +08:00
|
|
|
host->multi_io_quirk = sh_mobile_sdhi_multi_io_quirk;
|
2016-08-24 17:34:38 +08:00
|
|
|
|
|
|
|
/* SDR speeds are only available on Gen2+ */
|
|
|
|
if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
|
|
|
|
/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
|
|
|
|
host->card_busy = sh_mobile_sdhi_card_busy;
|
|
|
|
host->start_signal_voltage_switch =
|
|
|
|
sh_mobile_sdhi_start_signal_voltage_switch;
|
|
|
|
}
|
2016-02-15 23:01:48 +08:00
|
|
|
|
|
|
|
/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
|
|
|
|
if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
|
2015-01-13 12:59:33 +08:00
|
|
|
host->bus_shift = 1;
|
2015-01-13 12:57:33 +08:00
|
|
|
|
2015-02-24 10:07:07 +08:00
|
|
|
if (mmd)
|
2015-02-24 10:06:43 +08:00
|
|
|
*mmc_data = *mmd;
|
2015-02-24 10:07:07 +08:00
|
|
|
|
2013-04-26 23:47:19 +08:00
|
|
|
dma_priv->filter = shdma_chan_filter;
|
2015-01-13 12:59:56 +08:00
|
|
|
dma_priv->enable = sh_mobile_sdhi_enable_dma;
|
2013-04-26 23:47:19 +08:00
|
|
|
|
2015-01-13 12:58:46 +08:00
|
|
|
mmc_data->alignment_shift = 1; /* 2-byte alignment */
|
2015-02-24 10:06:43 +08:00
|
|
|
mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
|
2015-01-13 12:58:46 +08:00
|
|
|
|
2010-08-30 18:50:19 +08:00
|
|
|
/*
|
|
|
|
* All SDHI blocks support 2-byte and larger block sizes in 4-bit
|
|
|
|
* bus width mode.
|
|
|
|
*/
|
|
|
|
mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
|
|
|
|
|
2010-12-29 06:22:32 +08:00
|
|
|
/*
|
|
|
|
* All SDHI blocks support SDIO IRQ signalling.
|
|
|
|
*/
|
|
|
|
mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
|
|
|
|
|
2014-08-25 11:00:25 +08:00
|
|
|
/*
|
|
|
|
* All SDHI have CMD12 controll bit
|
|
|
|
*/
|
|
|
|
mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
|
|
|
|
|
2017-01-20 04:07:17 +08:00
|
|
|
/* All SDHI have SDIO status bits which must be 1 */
|
|
|
|
mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
|
2014-08-25 11:00:52 +08:00
|
|
|
|
2015-01-13 12:57:22 +08:00
|
|
|
ret = tmio_mmc_host_probe(host, mmc_data);
|
2011-03-14 16:52:33 +08:00
|
|
|
if (ret < 0)
|
2015-01-13 12:57:22 +08:00
|
|
|
goto efree;
|
2009-10-02 10:22:09 +08:00
|
|
|
|
2016-12-13 03:51:22 +08:00
|
|
|
/* Enable tuning iff we have an SCC and a supported mode */
|
2016-12-13 03:51:26 +08:00
|
|
|
if (of_data && of_data->scc_offset &&
|
|
|
|
(host->mmc->caps & MMC_CAP_UHS_SDR104 ||
|
|
|
|
host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) {
|
2016-12-13 03:51:21 +08:00
|
|
|
const struct sh_mobile_sdhi_scc *taps = of_data->taps;
|
|
|
|
bool hit = false;
|
|
|
|
|
2016-11-03 22:16:04 +08:00
|
|
|
host->mmc->caps |= MMC_CAP_HW_RESET;
|
|
|
|
|
2016-12-13 03:51:21 +08:00
|
|
|
for (i = 0; i < of_data->taps_num; i++) {
|
|
|
|
if (taps[i].clk_rate == 0 ||
|
|
|
|
taps[i].clk_rate == host->mmc->f_max) {
|
|
|
|
host->scc_tappos = taps->tap;
|
|
|
|
hit = true;
|
|
|
|
break;
|
2016-11-03 22:16:04 +08:00
|
|
|
}
|
2016-12-13 03:51:21 +08:00
|
|
|
}
|
2016-11-03 22:16:04 +08:00
|
|
|
|
2016-12-13 03:51:21 +08:00
|
|
|
if (!hit)
|
|
|
|
dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
|
2016-11-03 22:16:04 +08:00
|
|
|
|
2016-12-13 03:51:21 +08:00
|
|
|
priv->scc_ctl = host->ctl + of_data->scc_offset;
|
2016-12-13 03:51:22 +08:00
|
|
|
host->init_tuning = sh_mobile_sdhi_init_tuning;
|
|
|
|
host->prepare_tuning = sh_mobile_sdhi_prepare_tuning;
|
|
|
|
host->select_tuning = sh_mobile_sdhi_select_tuning;
|
|
|
|
host->check_scc_error = sh_mobile_sdhi_check_scc_error;
|
|
|
|
host->hw_reset = sh_mobile_sdhi_hw_reset;
|
2016-11-03 22:16:04 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
i = 0;
|
2016-04-26 23:55:23 +08:00
|
|
|
while (1) {
|
|
|
|
irq = platform_get_irq(pdev, i);
|
|
|
|
if (irq < 0)
|
|
|
|
break;
|
|
|
|
i++;
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
|
2011-08-26 16:42:39 +08:00
|
|
|
dev_name(&pdev->dev), host);
|
|
|
|
if (ret)
|
2013-02-15 23:13:58 +08:00
|
|
|
goto eirq;
|
2011-08-26 16:42:39 +08:00
|
|
|
}
|
|
|
|
|
2016-04-26 23:55:23 +08:00
|
|
|
/* There must be at least one IRQ source */
|
|
|
|
if (!i) {
|
2011-08-26 16:42:39 +08:00
|
|
|
ret = irq;
|
2013-02-15 23:13:58 +08:00
|
|
|
goto eirq;
|
2011-08-26 16:42:39 +08:00
|
|
|
}
|
|
|
|
|
2016-04-01 23:44:32 +08:00
|
|
|
dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
|
2011-05-06 19:02:41 +08:00
|
|
|
mmc_hostname(host->mmc), (unsigned long)
|
2012-02-10 05:57:10 +08:00
|
|
|
(platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
|
2012-11-28 17:24:13 +08:00
|
|
|
host->mmc->f_max / 1000000);
|
2009-10-02 10:22:09 +08:00
|
|
|
|
2011-03-14 16:52:33 +08:00
|
|
|
return ret;
|
2009-10-02 10:22:09 +08:00
|
|
|
|
2013-02-15 23:13:58 +08:00
|
|
|
eirq:
|
2011-05-06 19:02:33 +08:00
|
|
|
tmio_mmc_host_remove(host);
|
2015-01-13 12:57:22 +08:00
|
|
|
efree:
|
|
|
|
tmio_mmc_host_free(host);
|
2011-03-14 16:52:33 +08:00
|
|
|
eprobe:
|
2009-10-02 10:22:09 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_mobile_sdhi_remove(struct platform_device *pdev)
|
|
|
|
{
|
2011-03-14 16:52:33 +08:00
|
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
2011-05-06 19:02:45 +08:00
|
|
|
|
2011-05-27 22:54:05 +08:00
|
|
|
tmio_mmc_host_remove(host);
|
|
|
|
|
2009-10-02 10:22:09 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-05-06 00:13:12 +08:00
|
|
|
static const struct dev_pm_ops tmio_mmc_dev_pm_ops = {
|
2014-08-25 18:18:26 +08:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
|
|
pm_runtime_force_resume)
|
2014-12-04 07:34:11 +08:00
|
|
|
SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
|
2013-10-23 20:51:31 +08:00
|
|
|
tmio_mmc_host_runtime_resume,
|
|
|
|
NULL)
|
2011-05-06 00:13:12 +08:00
|
|
|
};
|
|
|
|
|
2009-10-02 10:22:09 +08:00
|
|
|
static struct platform_driver sh_mobile_sdhi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "sh_mobile_sdhi",
|
2011-05-06 00:13:12 +08:00
|
|
|
.pm = &tmio_mmc_dev_pm_ops,
|
2012-05-02 00:03:43 +08:00
|
|
|
.of_match_table = sh_mobile_sdhi_of_match,
|
2009-10-02 10:22:09 +08:00
|
|
|
},
|
|
|
|
.probe = sh_mobile_sdhi_probe,
|
2012-11-20 02:20:26 +08:00
|
|
|
.remove = sh_mobile_sdhi_remove,
|
2009-10-02 10:22:09 +08:00
|
|
|
};
|
|
|
|
|
2011-11-26 12:55:43 +08:00
|
|
|
module_platform_driver(sh_mobile_sdhi_driver);
|
2009-10-02 10:22:09 +08:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("SuperH Mobile SDHI driver");
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
2011-03-14 16:52:33 +08:00
|
|
|
MODULE_ALIAS("platform:sh_mobile_sdhi");
|