License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2011-09-20 01:45:05 +08:00
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#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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2016-07-14 05:17:00 +08:00
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#include <linux/iommu.h>
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#include <asm/iommu.h>
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#include <asm/msi_bitmap.h>
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2011-09-20 01:45:05 +08:00
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struct pci_dn;
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2017-04-03 17:51:44 +08:00
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/* Maximum possible number of ATSD MMIO registers per NPU */
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#define NV_NMMU_ATSD_REGS 8
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2011-09-20 01:45:05 +08:00
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enum pnv_phb_type {
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2018-01-23 19:31:36 +08:00
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PNV_PHB_IODA1 = 0,
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PNV_PHB_IODA2 = 1,
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PNV_PHB_NPU_NVLINK = 2,
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PNV_PHB_NPU_OCAPI = 3,
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2011-09-20 01:45:05 +08:00
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};
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2011-11-30 02:22:53 +08:00
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/* Precise PHB model for error management */
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enum pnv_phb_model {
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PNV_PHB_MODEL_UNKNOWN,
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PNV_PHB_MODEL_P7IOC,
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2013-04-26 03:20:57 +08:00
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PNV_PHB_MODEL_PHB3,
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2015-12-17 10:43:13 +08:00
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PNV_PHB_MODEL_NPU,
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2017-01-10 12:41:44 +08:00
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PNV_PHB_MODEL_NPU2,
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2011-11-30 02:22:53 +08:00
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};
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2013-09-06 09:00:03 +08:00
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#define PNV_PCI_DIAG_BUF_SIZE 8192
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2012-08-20 11:49:15 +08:00
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#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
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#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
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#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
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2014-07-21 12:42:30 +08:00
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#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
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#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
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2015-03-25 16:23:57 +08:00
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#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
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2011-11-30 02:22:53 +08:00
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2017-06-14 12:19:58 +08:00
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/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
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#define PNV_IODA_STOPPED_STATE 0x8000000000000000
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2011-11-16 01:29:08 +08:00
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/* Data associated with a PE, including IOMMU tracking etc.. */
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2013-04-26 03:21:00 +08:00
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struct pnv_phb;
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2011-11-16 01:29:08 +08:00
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struct pnv_ioda_pe {
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2012-08-20 11:49:15 +08:00
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unsigned long flags;
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2013-04-26 03:21:00 +08:00
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struct pnv_phb *phb;
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2016-05-20 14:41:35 +08:00
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int device_count;
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2012-08-20 11:49:15 +08:00
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2011-11-16 01:29:08 +08:00
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/* A PE can be associated with a single device or an
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* entire bus (& children). In the former case, pdev
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* is populated, in the later case, pbus is.
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*/
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2015-03-25 16:23:57 +08:00
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#ifdef CONFIG_PCI_IOV
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struct pci_dev *parent_dev;
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#endif
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2011-11-16 01:29:08 +08:00
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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/* Effective RID (device RID for a device PE and base bus
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* RID with devfn 0 for a bus PE)
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*/
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unsigned int rid;
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/* PE number */
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unsigned int pe_number;
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/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
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2015-06-05 14:35:08 +08:00
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struct iommu_table_group table_group;
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2011-11-16 01:29:08 +08:00
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2014-02-11 08:32:38 +08:00
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/* 64-bit TCE bypass region */
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bool tce_bypass_enabled;
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uint64_t tce_bypass_base;
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2011-11-16 01:29:08 +08:00
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/* MSIs. MVE index is identical for for 32 and 64 bit MSI
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* and -1 if not supported. (It's actually identical to the
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* PE number)
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*/
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int mve_number;
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2014-07-21 12:42:30 +08:00
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/* PEs in compound case */
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struct pnv_ioda_pe *master;
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struct list_head slaves;
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powerpc/powernv: Enable PCI peer-to-peer
P9 has support for PCI peer-to-peer, enabling a device to write in the
MMIO space of another device directly, without interrupting the CPU.
This patch adds support for it on powernv, by adding a new API to be
called by drivers. The pnv_pci_set_p2p(...) call configures an
'initiator', i.e the device which will issue the MMIO operation, and a
'target', i.e. the device on the receiving side.
P9 really only supports MMIO stores for the time being but that's
expected to change in the future, so the API allows to define both
load and store operations.
/* PCI p2p descriptor */
#define OPAL_PCI_P2P_ENABLE 0x1
#define OPAL_PCI_P2P_LOAD 0x2
#define OPAL_PCI_P2P_STORE 0x4
int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target,
u64 desc)
It uses a new OPAL call, as the configuration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
[mpe: Drop unrelated OPAL calls, s/uint64_t/u64/, minor formatting]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-08-04 17:55:14 +08:00
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/* PCI peer-to-peer*/
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int p2p_initiator_count;
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2011-11-16 01:29:08 +08:00
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/* Link in list of PE#s */
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2012-08-20 11:49:15 +08:00
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struct list_head list;
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2011-11-16 01:29:08 +08:00
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};
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2014-04-24 16:00:09 +08:00
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#define PNV_PHB_FLAG_EEH (1 << 0)
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2016-07-14 05:17:06 +08:00
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#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
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2014-04-24 16:00:09 +08:00
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2011-09-20 01:45:05 +08:00
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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2011-11-30 02:22:53 +08:00
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enum pnv_phb_model model;
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2013-06-20 13:21:06 +08:00
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u64 hub_id;
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2011-09-20 01:45:05 +08:00
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u64 opal_id;
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2014-04-24 16:00:09 +08:00
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int flags;
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2011-09-20 01:45:05 +08:00
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void __iomem *regs;
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2016-07-08 14:37:14 +08:00
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u64 regs_phys;
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2012-08-20 11:49:18 +08:00
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int initialized;
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2011-09-20 01:45:05 +08:00
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spinlock_t lock;
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2013-06-20 18:13:25 +08:00
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#ifdef CONFIG_DEBUG_FS
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2014-04-24 16:00:18 +08:00
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int has_dbgfs;
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2013-06-20 18:13:25 +08:00
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struct dentry *dbgfs;
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#endif
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2011-09-20 01:45:06 +08:00
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#ifdef CONFIG_PCI_MSI
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unsigned int msi_base;
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unsigned int msi32_support;
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2013-03-06 05:12:37 +08:00
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struct msi_bitmap msi_bmp;
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2011-09-20 01:45:06 +08:00
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#endif
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int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
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2013-04-26 03:20:59 +08:00
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unsigned int hwirq, unsigned int virq,
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unsigned int is_64, struct msi_msg *msg);
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2011-09-20 01:45:05 +08:00
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void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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void (*fixup_phb)(struct pci_controller *hose);
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2014-07-21 12:42:30 +08:00
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int (*init_m64)(struct pnv_phb *phb);
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2015-06-19 10:26:17 +08:00
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void (*reserve_m64_pe)(struct pci_bus *bus,
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unsigned long *pe_bitmap, bool all);
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2016-05-03 13:41:36 +08:00
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struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
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2014-07-21 12:42:33 +08:00
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int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
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void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
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int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
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2011-09-20 01:45:05 +08:00
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2016-02-08 12:08:20 +08:00
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struct {
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/* Global bridge info */
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2016-05-03 13:41:24 +08:00
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unsigned int total_pe_num;
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unsigned int reserved_pe_idx;
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2016-05-20 14:41:32 +08:00
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unsigned int root_pe_idx;
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bool root_pe_populated;
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2016-02-08 12:08:20 +08:00
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/* 32-bit MMIO window */
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unsigned int m32_size;
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unsigned int m32_segsize;
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unsigned int m32_pci_base;
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/* 64-bit MMIO window */
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unsigned int m64_bar_idx;
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unsigned long m64_size;
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unsigned long m64_segsize;
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unsigned long m64_base;
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unsigned long m64_bar_alloc;
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/* IO ports */
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unsigned int io_size;
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unsigned int io_segsize;
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unsigned int io_pci_base;
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2016-05-03 13:41:23 +08:00
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/* PE allocation */
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2016-02-08 12:08:20 +08:00
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struct mutex pe_alloc_mutex;
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2016-05-03 13:41:23 +08:00
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unsigned long *pe_alloc;
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struct pnv_ioda_pe *pe_array;
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2016-02-08 12:08:20 +08:00
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/* M32 & IO segment maps */
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2016-05-03 13:41:29 +08:00
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unsigned int *m64_segmap;
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2016-02-08 12:08:20 +08:00
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unsigned int *m32_segmap;
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unsigned int *io_segmap;
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2016-05-05 10:04:16 +08:00
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/* DMA32 segment maps - IODA1 only */
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unsigned int dma32_count;
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unsigned int *dma32_segmap;
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2016-02-08 12:08:20 +08:00
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/* IRQ chip */
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int irq_chip_init;
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struct irq_chip irq_chip;
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/* Sorted list of used PE's based
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* on the sequence of creation
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*/
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struct list_head pe_list;
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struct mutex pe_list_mutex;
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2016-05-20 14:41:29 +08:00
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/* Reverse map of PEs, indexed by {bus, devfn} */
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unsigned int pe_rmap[0x10000];
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2016-02-08 12:08:20 +08:00
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} ioda;
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2011-11-30 02:22:53 +08:00
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2017-06-14 12:19:59 +08:00
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/* PHB and hub diagnostics */
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unsigned int diag_data_size;
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u8 *diag_data;
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2013-12-21 03:06:01 +08:00
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2017-04-03 17:51:44 +08:00
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/* Nvlink2 data */
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struct npu {
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int index;
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__be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
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unsigned int mmio_atsd_count;
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/* Bitmask for MMIO register usage */
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unsigned long mmio_atsd_usage;
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2017-09-06 09:49:00 +08:00
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/* Do we need to explicitly flush the nest mmu? */
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bool nmmu_flush;
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2017-04-03 17:51:44 +08:00
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} npu;
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2016-07-14 05:17:06 +08:00
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#ifdef CONFIG_CXL_BASE
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struct cxl_afu *cxl_afu;
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#endif
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powerpc/powernv: Enable PCI peer-to-peer
P9 has support for PCI peer-to-peer, enabling a device to write in the
MMIO space of another device directly, without interrupting the CPU.
This patch adds support for it on powernv, by adding a new API to be
called by drivers. The pnv_pci_set_p2p(...) call configures an
'initiator', i.e the device which will issue the MMIO operation, and a
'target', i.e. the device on the receiving side.
P9 really only supports MMIO stores for the time being but that's
expected to change in the future, so the API allows to define both
load and store operations.
/* PCI p2p descriptor */
#define OPAL_PCI_P2P_ENABLE 0x1
#define OPAL_PCI_P2P_LOAD 0x2
#define OPAL_PCI_P2P_STORE 0x4
int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target,
u64 desc)
It uses a new OPAL call, as the configuration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
[mpe: Drop unrelated OPAL calls, s/uint64_t/u64/, minor formatting]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-08-04 17:55:14 +08:00
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int p2p_target_count;
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2011-09-20 01:45:05 +08:00
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};
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extern struct pci_ops pnv_pci_ops;
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2015-06-05 14:35:06 +08:00
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extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction,
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2016-08-04 04:46:00 +08:00
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unsigned long attrs);
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2015-06-05 14:35:06 +08:00
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extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
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2015-06-05 14:35:15 +08:00
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extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
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unsigned long *hpa, enum dma_data_direction *direction);
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2015-06-05 14:35:06 +08:00
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extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
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2011-09-20 01:45:05 +08:00
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2013-11-22 16:28:45 +08:00
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void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
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unsigned char *log_buff);
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2015-03-17 13:15:03 +08:00
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int pnv_pci_cfg_read(struct pci_dn *pdn,
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2013-06-27 13:46:48 +08:00
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int where, int size, u32 *val);
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2015-03-17 13:15:03 +08:00
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int pnv_pci_cfg_write(struct pci_dn *pdn,
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2013-06-27 13:46:48 +08:00
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int where, int size, u32 val);
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2015-06-05 14:35:09 +08:00
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extern struct iommu_table *pnv_pci_table_alloc(int nid);
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extern long pnv_pci_link_table_and_group(int node, int num,
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struct iommu_table *tbl,
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struct iommu_table_group *table_group);
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extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
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struct iommu_table_group *table_group);
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2011-09-20 01:45:05 +08:00
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extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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2014-06-06 16:44:03 +08:00
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u64 dma_offset, unsigned page_shift);
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2011-11-16 01:29:08 +08:00
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extern void pnv_pci_init_ioda_hub(struct device_node *np);
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2013-04-26 03:20:57 +08:00
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extern void pnv_pci_init_ioda2_phb(struct device_node *np);
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2015-12-17 10:43:13 +08:00
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extern void pnv_pci_init_npu_phb(struct device_node *np);
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2018-01-23 19:31:36 +08:00
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extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
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2014-04-24 16:00:24 +08:00
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extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
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2015-02-16 11:45:47 +08:00
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extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
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2013-05-10 14:59:18 +08:00
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2015-04-28 13:12:05 +08:00
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extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
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2016-02-09 12:50:22 +08:00
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extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
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2015-04-28 13:12:05 +08:00
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extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
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2016-07-14 05:17:00 +08:00
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extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
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extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
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2016-07-14 05:17:06 +08:00
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extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
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powerpc/powernv: Enable PCI peer-to-peer
P9 has support for PCI peer-to-peer, enabling a device to write in the
MMIO space of another device directly, without interrupting the CPU.
This patch adds support for it on powernv, by adding a new API to be
called by drivers. The pnv_pci_set_p2p(...) call configures an
'initiator', i.e the device which will issue the MMIO operation, and a
'target', i.e. the device on the receiving side.
P9 really only supports MMIO stores for the time being but that's
expected to change in the future, so the API allows to define both
load and store operations.
/* PCI p2p descriptor */
#define OPAL_PCI_P2P_ENABLE 0x1
#define OPAL_PCI_P2P_LOAD 0x2
#define OPAL_PCI_P2P_STORE 0x4
int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target,
u64 desc)
It uses a new OPAL call, as the configuration magic is done on the
PHBs by skiboot.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Russell Currey <ruscur@russell.cc>
[mpe: Drop unrelated OPAL calls, s/uint64_t/u64/, minor formatting]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-08-04 17:55:14 +08:00
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extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
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2017-09-07 14:35:44 +08:00
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extern int pnv_eeh_post_init(void);
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2015-04-28 13:12:05 +08:00
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2016-04-29 16:55:21 +08:00
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extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
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const char *fmt, ...);
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#define pe_err(pe, fmt, ...) \
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pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
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#define pe_warn(pe, fmt, ...) \
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pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
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#define pe_info(pe, fmt, ...) \
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pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
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2015-12-17 10:43:13 +08:00
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/* Nvlink functions */
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2016-04-29 16:55:20 +08:00
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extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
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2017-05-03 11:24:08 +08:00
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extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
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2016-04-29 16:55:24 +08:00
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extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
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extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
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struct iommu_table *tbl);
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extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
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extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
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extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
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2017-04-03 17:51:44 +08:00
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extern int pnv_npu2_init(struct pnv_phb *phb);
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2016-07-14 05:17:06 +08:00
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/* cxl functions */
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extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
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extern void pnv_cxl_disable_device(struct pci_dev *dev);
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2016-07-14 05:17:10 +08:00
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extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
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2016-07-14 05:17:06 +08:00
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/* phb ops (cxl switches these when enabling the kernel api on the phb) */
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extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
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2011-09-20 01:45:05 +08:00
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#endif /* __POWERNV_PCI_H */
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