2019-02-14 16:51:33 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2006-06-05 02:01:08 +08:00
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/*
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* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
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2018-05-28 16:59:14 +08:00
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* (https://opencores.org/project/i2c/overview)
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2006-06-05 02:01:08 +08:00
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*
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2018-08-23 00:16:07 +08:00
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* Peter Korsgaard <peter@korsgaard.com>
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2006-06-05 02:01:08 +08:00
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*
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2012-11-15 23:50:59 +08:00
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* Support for the GRLIB port of the controller by
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* Andreas Larsson <andreas@gaisler.com>
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2006-06-05 02:01:08 +08:00
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*/
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2015-02-06 03:55:01 +08:00
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#include <linux/clk.h>
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2019-02-14 16:51:32 +08:00
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#include <linux/delay.h>
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2013-01-21 18:09:03 +08:00
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#include <linux/err.h>
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2006-06-05 02:01:08 +08:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/wait.h>
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2018-04-20 04:00:09 +08:00
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#include <linux/platform_data/i2c-ocores.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2010-05-22 00:41:01 +08:00
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#include <linux/io.h>
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2012-07-13 21:44:23 +08:00
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#include <linux/log2.h>
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2019-02-14 16:51:30 +08:00
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#include <linux/spinlock.h>
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2019-02-14 16:51:32 +08:00
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#include <linux/jiffies.h>
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2019-02-11 18:37:28 +08:00
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/*
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* 'process_lock' exists because ocores_process() and ocores_process_timeout()
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* can't run in parallel.
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2019-02-14 16:51:30 +08:00
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*/
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2006-06-05 02:01:08 +08:00
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struct ocores_i2c {
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void __iomem *base;
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2019-02-14 11:24:49 +08:00
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int iobase;
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2012-07-13 21:44:23 +08:00
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u32 reg_shift;
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2012-07-13 21:44:25 +08:00
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u32 reg_io_width;
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2006-06-05 02:01:08 +08:00
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wait_queue_head_t wait;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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int pos;
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int nmsgs;
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int state; /* see STATE_ */
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2019-02-14 16:51:30 +08:00
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spinlock_t process_lock;
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2015-02-06 03:55:01 +08:00
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struct clk *clk;
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2015-02-02 23:28:12 +08:00
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int ip_clock_khz;
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int bus_clock_khz;
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2012-11-15 23:50:59 +08:00
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void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
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u8 (*getreg)(struct ocores_i2c *i2c, int reg);
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2006-06-05 02:01:08 +08:00
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};
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/* registers */
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#define OCI2C_PRELOW 0
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#define OCI2C_PREHIGH 1
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#define OCI2C_CONTROL 2
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#define OCI2C_DATA 3
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2006-06-13 03:40:53 +08:00
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#define OCI2C_CMD 4 /* write only */
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#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
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2006-06-05 02:01:08 +08:00
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#define OCI2C_CTRL_IEN 0x40
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#define OCI2C_CTRL_EN 0x80
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#define OCI2C_CMD_START 0x91
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#define OCI2C_CMD_STOP 0x41
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#define OCI2C_CMD_READ 0x21
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#define OCI2C_CMD_WRITE 0x11
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#define OCI2C_CMD_READ_ACK 0x21
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#define OCI2C_CMD_READ_NACK 0x29
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#define OCI2C_CMD_IACK 0x01
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#define OCI2C_STAT_IF 0x01
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#define OCI2C_STAT_TIP 0x02
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#define OCI2C_STAT_ARBLOST 0x20
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#define OCI2C_STAT_BUSY 0x40
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#define OCI2C_STAT_NACK 0x80
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#define STATE_DONE 0
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#define STATE_START 1
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#define STATE_WRITE 2
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#define STATE_READ 3
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#define STATE_ERROR 4
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2012-11-15 23:50:59 +08:00
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#define TYPE_OCORES 0
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#define TYPE_GRLIB 1
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2019-06-01 14:11:14 +08:00
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#define TYPE_SIFIVE_REV0 2
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2012-11-15 23:50:59 +08:00
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static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
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2006-06-05 02:01:08 +08:00
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{
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2012-11-15 23:50:59 +08:00
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iowrite8(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite16(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite32(value, i2c->base + (reg << i2c->reg_shift));
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}
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2015-10-07 07:45:11 +08:00
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static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
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}
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2012-11-15 23:50:59 +08:00
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static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
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{
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return ioread8(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
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{
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return ioread16(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
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{
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return ioread32(i2c->base + (reg << i2c->reg_shift));
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}
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2015-10-07 07:45:11 +08:00
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static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
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{
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return ioread16be(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
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{
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return ioread32be(i2c->base + (reg << i2c->reg_shift));
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}
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2019-02-14 11:24:49 +08:00
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static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
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{
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outb(value, i2c->iobase + reg);
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}
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static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
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{
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return inb(i2c->iobase + reg);
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}
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2006-06-05 02:01:08 +08:00
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static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
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{
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2012-11-15 23:50:59 +08:00
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i2c->setreg(i2c, reg, value);
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2006-06-05 02:01:08 +08:00
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}
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static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
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{
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2012-11-15 23:50:59 +08:00
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return i2c->getreg(i2c, reg);
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2006-06-05 02:01:08 +08:00
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}
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2019-02-14 16:51:31 +08:00
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static void ocores_process(struct ocores_i2c *i2c, u8 stat)
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2006-06-05 02:01:08 +08:00
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{
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struct i2c_msg *msg = i2c->msg;
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2019-02-14 16:51:30 +08:00
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unsigned long flags;
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/*
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* If we spin here is because we are in timeout, so we are going
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* to be in STATE_ERROR. See ocores_process_timeout()
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*/
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spin_lock_irqsave(&i2c->process_lock, flags);
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2006-06-05 02:01:08 +08:00
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if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
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/* stop has been sent */
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
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wake_up(&i2c->wait);
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2019-02-14 16:51:30 +08:00
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goto out;
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2006-06-05 02:01:08 +08:00
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}
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/* error? */
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if (stat & OCI2C_STAT_ARBLOST) {
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i2c->state = STATE_ERROR;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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2019-02-14 16:51:30 +08:00
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goto out;
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2006-06-05 02:01:08 +08:00
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}
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if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
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i2c->state =
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(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
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if (stat & OCI2C_STAT_NACK) {
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i2c->state = STATE_ERROR;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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2019-02-14 16:51:30 +08:00
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goto out;
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2006-06-05 02:01:08 +08:00
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}
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2019-02-14 16:51:34 +08:00
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} else {
|
2006-06-05 02:01:08 +08:00
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msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
|
2019-02-14 16:51:34 +08:00
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}
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2006-06-05 02:01:08 +08:00
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/* end of msg? */
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if (i2c->pos == msg->len) {
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i2c->nmsgs--;
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i2c->msg++;
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i2c->pos = 0;
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msg = i2c->msg;
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if (i2c->nmsgs) { /* end? */
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/* send start? */
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if (!(msg->flags & I2C_M_NOSTART)) {
|
2016-04-04 02:44:56 +08:00
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u8 addr = i2c_8bit_addr_from_msg(msg);
|
2006-06-05 02:01:08 +08:00
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i2c->state = STATE_START;
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oc_setreg(i2c, OCI2C_DATA, addr);
|
2019-02-14 16:51:34 +08:00
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
|
2019-02-14 16:51:30 +08:00
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goto out;
|
2019-02-14 16:51:34 +08:00
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}
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i2c->state = (msg->flags & I2C_M_RD)
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? STATE_READ : STATE_WRITE;
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2006-06-05 02:01:08 +08:00
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} else {
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i2c->state = STATE_DONE;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
|
2019-02-14 16:51:30 +08:00
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goto out;
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2006-06-05 02:01:08 +08:00
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}
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}
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if (i2c->state == STATE_READ) {
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oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
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OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
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} else {
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oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
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}
|
2019-02-14 16:51:30 +08:00
|
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out:
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spin_unlock_irqrestore(&i2c->process_lock, flags);
|
2006-06-05 02:01:08 +08:00
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}
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 21:55:46 +08:00
|
|
|
static irqreturn_t ocores_isr(int irq, void *dev_id)
|
2006-06-05 02:01:08 +08:00
|
|
|
{
|
|
|
|
|
struct ocores_i2c *i2c = dev_id;
|
2019-02-14 16:51:31 +08:00
|
|
|
u8 stat = oc_getreg(i2c, OCI2C_STATUS);
|
|
|
|
|
|
|
|
|
|
if (!(stat & OCI2C_STAT_IF))
|
|
|
|
|
return IRQ_NONE;
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2019-02-14 16:51:31 +08:00
|
|
|
ocores_process(i2c, stat);
|
2006-06-05 02:01:08 +08:00
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-14 16:51:30 +08:00
|
|
|
/**
|
|
|
|
|
* Process timeout event
|
|
|
|
|
* @i2c: ocores I2C device instance
|
|
|
|
|
*/
|
|
|
|
|
static void ocores_process_timeout(struct ocores_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&i2c->process_lock, flags);
|
|
|
|
|
i2c->state = STATE_ERROR;
|
|
|
|
|
oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
|
|
|
|
|
spin_unlock_irqrestore(&i2c->process_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-14 16:51:32 +08:00
|
|
|
/**
|
|
|
|
|
* Wait until something change in a given register
|
|
|
|
|
* @i2c: ocores I2C device instance
|
|
|
|
|
* @reg: register to query
|
|
|
|
|
* @mask: bitmask to apply on register value
|
|
|
|
|
* @val: expected result
|
|
|
|
|
* @timeout: timeout in jiffies
|
|
|
|
|
*
|
|
|
|
|
* Timeout is necessary to avoid to stay here forever when the chip
|
|
|
|
|
* does not answer correctly.
|
|
|
|
|
*
|
|
|
|
|
* Return: 0 on success, -ETIMEDOUT on timeout
|
|
|
|
|
*/
|
|
|
|
|
static int ocores_wait(struct ocores_i2c *i2c,
|
|
|
|
|
int reg, u8 mask, u8 val,
|
|
|
|
|
const unsigned long timeout)
|
|
|
|
|
{
|
|
|
|
|
unsigned long j;
|
|
|
|
|
|
|
|
|
|
j = jiffies + timeout;
|
|
|
|
|
while (1) {
|
|
|
|
|
u8 status = oc_getreg(i2c, reg);
|
|
|
|
|
|
|
|
|
|
if ((status & mask) == val)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (time_after(jiffies, j))
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Wait until is possible to process some data
|
|
|
|
|
* @i2c: ocores I2C device instance
|
|
|
|
|
*
|
|
|
|
|
* Used when the device is in polling mode (interrupts disabled).
|
|
|
|
|
*
|
|
|
|
|
* Return: 0 on success, -ETIMEDOUT on timeout
|
|
|
|
|
*/
|
|
|
|
|
static int ocores_poll_wait(struct ocores_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
u8 mask;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
|
|
|
|
|
/* transfer is over */
|
|
|
|
|
mask = OCI2C_STAT_BUSY;
|
|
|
|
|
} else {
|
|
|
|
|
/* on going transfer */
|
|
|
|
|
mask = OCI2C_STAT_TIP;
|
|
|
|
|
/*
|
|
|
|
|
* We wait for the data to be transferred (8bit),
|
|
|
|
|
* then we start polling on the ACK/NACK bit
|
|
|
|
|
*/
|
|
|
|
|
udelay((8 * 1000) / i2c->bus_clock_khz);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* once we are here we expect to get the expected result immediately
|
|
|
|
|
* so if after 1ms we timeout then something is broken.
|
|
|
|
|
*/
|
|
|
|
|
err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
|
|
|
|
|
if (err)
|
|
|
|
|
dev_warn(i2c->adap.dev.parent,
|
|
|
|
|
"%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
|
|
|
|
|
__func__, mask);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* It handles an IRQ-less transfer
|
|
|
|
|
* @i2c: ocores I2C device instance
|
|
|
|
|
*
|
|
|
|
|
* Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
|
|
|
|
|
* (only that IRQ are not produced). This means that we can re-use entirely
|
|
|
|
|
* ocores_isr(), we just add our polling code around it.
|
|
|
|
|
*
|
|
|
|
|
* It can run in atomic context
|
|
|
|
|
*/
|
|
|
|
|
static void ocores_process_polling(struct ocores_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
while (1) {
|
|
|
|
|
irqreturn_t ret;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
err = ocores_poll_wait(i2c);
|
|
|
|
|
if (err) {
|
|
|
|
|
i2c->state = STATE_ERROR;
|
|
|
|
|
break; /* timeout */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = ocores_isr(-1, i2c);
|
|
|
|
|
if (ret == IRQ_NONE)
|
|
|
|
|
break; /* all messages have been transferred */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ocores_xfer_core(struct ocores_i2c *i2c,
|
|
|
|
|
struct i2c_msg *msgs, int num,
|
|
|
|
|
bool polling)
|
2006-06-05 02:01:08 +08:00
|
|
|
{
|
2019-02-14 16:51:30 +08:00
|
|
|
int ret;
|
2019-02-14 16:51:32 +08:00
|
|
|
u8 ctrl;
|
|
|
|
|
|
|
|
|
|
ctrl = oc_getreg(i2c, OCI2C_CONTROL);
|
|
|
|
|
if (polling)
|
|
|
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
|
|
|
|
|
else
|
|
|
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
|
2006-06-05 02:01:08 +08:00
|
|
|
|
|
|
|
|
i2c->msg = msgs;
|
|
|
|
|
i2c->pos = 0;
|
|
|
|
|
i2c->nmsgs = num;
|
|
|
|
|
i2c->state = STATE_START;
|
|
|
|
|
|
2018-05-16 15:16:47 +08:00
|
|
|
oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
|
2006-06-05 02:01:08 +08:00
|
|
|
oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
|
|
|
|
|
|
2019-02-14 16:51:32 +08:00
|
|
|
if (polling) {
|
|
|
|
|
ocores_process_polling(i2c);
|
|
|
|
|
} else {
|
|
|
|
|
ret = wait_event_timeout(i2c->wait,
|
|
|
|
|
(i2c->state == STATE_ERROR) ||
|
|
|
|
|
(i2c->state == STATE_DONE), HZ);
|
|
|
|
|
if (ret == 0) {
|
|
|
|
|
ocores_process_timeout(i2c);
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
2019-02-14 16:51:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (i2c->state == STATE_DONE) ? num : -EIO;
|
2006-06-05 02:01:08 +08:00
|
|
|
}
|
|
|
|
|
|
2019-02-14 16:51:32 +08:00
|
|
|
static int ocores_xfer_polling(struct i2c_adapter *adap,
|
|
|
|
|
struct i2c_msg *msgs, int num)
|
|
|
|
|
{
|
|
|
|
|
return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ocores_xfer(struct i2c_adapter *adap,
|
|
|
|
|
struct i2c_msg *msgs, int num)
|
|
|
|
|
{
|
2019-04-03 20:40:15 +08:00
|
|
|
return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
|
2019-02-14 16:51:32 +08:00
|
|
|
}
|
|
|
|
|
|
2015-02-02 23:28:12 +08:00
|
|
|
static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
|
2006-06-05 02:01:08 +08:00
|
|
|
{
|
|
|
|
|
int prescale;
|
2015-02-02 23:28:12 +08:00
|
|
|
int diff;
|
2006-06-05 02:01:08 +08:00
|
|
|
u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
|
|
|
|
|
|
|
|
|
|
/* make sure the device is disabled */
|
2019-02-14 16:51:32 +08:00
|
|
|
ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
|
|
|
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl);
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2015-02-02 23:28:12 +08:00
|
|
|
prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
|
|
|
|
|
prescale = clamp(prescale, 0, 0xffff);
|
|
|
|
|
|
|
|
|
|
diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
|
|
|
|
|
if (abs(diff) > i2c->bus_clock_khz / 10) {
|
|
|
|
|
dev_err(dev,
|
|
|
|
|
"Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
|
|
|
|
|
i2c->ip_clock_khz, i2c->bus_clock_khz);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2006-06-05 02:01:08 +08:00
|
|
|
oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
|
|
|
|
|
oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
|
|
|
|
|
|
|
|
|
|
/* Init the device */
|
|
|
|
|
oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
|
2019-02-14 16:51:32 +08:00
|
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
|
2015-02-02 23:28:12 +08:00
|
|
|
|
|
|
|
|
return 0;
|
2006-06-05 02:01:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static u32 ocores_func(struct i2c_adapter *adap)
|
|
|
|
|
{
|
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-04-03 20:40:15 +08:00
|
|
|
static struct i2c_algorithm ocores_algorithm = {
|
2014-07-10 19:46:29 +08:00
|
|
|
.master_xfer = ocores_xfer,
|
2019-04-03 20:40:16 +08:00
|
|
|
.master_xfer_atomic = ocores_xfer_polling,
|
2014-07-10 19:46:29 +08:00
|
|
|
.functionality = ocores_func,
|
2006-06-05 02:01:08 +08:00
|
|
|
};
|
|
|
|
|
|
2017-08-19 18:34:12 +08:00
|
|
|
static const struct i2c_adapter ocores_adapter = {
|
2014-07-10 19:46:29 +08:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.name = "i2c-ocores",
|
|
|
|
|
.class = I2C_CLASS_DEPRECATED,
|
|
|
|
|
.algo = &ocores_algorithm,
|
2006-06-05 02:01:08 +08:00
|
|
|
};
|
|
|
|
|
|
2014-05-15 14:46:11 +08:00
|
|
|
static const struct of_device_id ocores_i2c_match[] = {
|
2012-11-15 23:50:59 +08:00
|
|
|
{
|
|
|
|
|
.compatible = "opencores,i2c-ocores",
|
|
|
|
|
.data = (void *)TYPE_OCORES,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "aeroflexgaisler,i2cmst",
|
|
|
|
|
.data = (void *)TYPE_GRLIB,
|
|
|
|
|
},
|
2019-06-01 14:11:14 +08:00
|
|
|
{
|
|
|
|
|
.compatible = "sifive,fu540-c000-i2c",
|
|
|
|
|
.data = (void *)TYPE_SIFIVE_REV0,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "sifive,i2c0",
|
|
|
|
|
.data = (void *)TYPE_SIFIVE_REV0,
|
|
|
|
|
},
|
2012-11-15 23:50:59 +08:00
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, ocores_i2c_match);
|
|
|
|
|
|
2010-11-25 00:26:20 +08:00
|
|
|
#ifdef CONFIG_OF
|
2019-02-14 16:51:34 +08:00
|
|
|
/*
|
|
|
|
|
* Read and write functions for the GRLIB port of the controller. Registers are
|
2012-11-19 20:17:48 +08:00
|
|
|
* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
|
2019-02-14 16:51:34 +08:00
|
|
|
* register. The subsequent registers have their offsets decreased accordingly.
|
|
|
|
|
*/
|
2012-11-19 20:17:48 +08:00
|
|
|
static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
|
|
|
|
|
{
|
|
|
|
|
u32 rd;
|
|
|
|
|
int rreg = reg;
|
2019-02-14 16:51:34 +08:00
|
|
|
|
2012-11-19 20:17:48 +08:00
|
|
|
if (reg != OCI2C_PRELOW)
|
|
|
|
|
rreg--;
|
|
|
|
|
rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
|
|
|
|
|
if (reg == OCI2C_PREHIGH)
|
|
|
|
|
return (u8)(rd >> 8);
|
|
|
|
|
else
|
|
|
|
|
return (u8)rd;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
|
|
|
|
|
{
|
|
|
|
|
u32 curr, wr;
|
|
|
|
|
int rreg = reg;
|
2019-02-14 16:51:34 +08:00
|
|
|
|
2012-11-19 20:17:48 +08:00
|
|
|
if (reg != OCI2C_PRELOW)
|
|
|
|
|
rreg--;
|
|
|
|
|
if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
|
|
|
|
|
curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
|
|
|
|
|
if (reg == OCI2C_PRELOW)
|
|
|
|
|
wr = (curr & 0xff00) | value;
|
|
|
|
|
else
|
|
|
|
|
wr = (((u32)value) << 8) | (curr & 0xff);
|
|
|
|
|
} else {
|
|
|
|
|
wr = value;
|
|
|
|
|
}
|
|
|
|
|
iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-13 21:44:22 +08:00
|
|
|
static int ocores_i2c_of_probe(struct platform_device *pdev,
|
|
|
|
|
struct ocores_i2c *i2c)
|
2010-11-25 00:26:20 +08:00
|
|
|
{
|
2012-07-13 21:44:23 +08:00
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2012-11-15 23:50:59 +08:00
|
|
|
const struct of_device_id *match;
|
2012-07-13 21:44:23 +08:00
|
|
|
u32 val;
|
2015-02-02 23:28:12 +08:00
|
|
|
u32 clock_frequency;
|
|
|
|
|
bool clock_frequency_present;
|
2012-07-13 21:44:23 +08:00
|
|
|
|
|
|
|
|
if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
|
|
|
|
|
/* no 'reg-shift', check for deprecated 'regstep' */
|
|
|
|
|
if (!of_property_read_u32(np, "regstep", &val)) {
|
|
|
|
|
if (!is_power_of_2(val)) {
|
|
|
|
|
dev_err(&pdev->dev, "invalid regstep %d\n",
|
|
|
|
|
val);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
i2c->reg_shift = ilog2(val);
|
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
|
"regstep property deprecated, use reg-shift\n");
|
|
|
|
|
}
|
2010-11-25 00:26:20 +08:00
|
|
|
}
|
|
|
|
|
|
2015-02-02 23:28:12 +08:00
|
|
|
clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
|
|
|
|
|
&clock_frequency);
|
|
|
|
|
i2c->bus_clock_khz = 100;
|
|
|
|
|
|
2015-02-06 03:55:01 +08:00
|
|
|
i2c->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
|
|
|
|
|
|
if (!IS_ERR(i2c->clk)) {
|
|
|
|
|
int ret = clk_prepare_enable(i2c->clk);
|
|
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"clk_prepare_enable failed: %d\n", ret);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
|
|
|
|
|
if (clock_frequency_present)
|
|
|
|
|
i2c->bus_clock_khz = clock_frequency / 1000;
|
2015-02-20 00:22:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (i2c->ip_clock_khz == 0) {
|
|
|
|
|
if (of_property_read_u32(np, "opencores,ip-clock-frequency",
|
|
|
|
|
&val)) {
|
|
|
|
|
if (!clock_frequency_present) {
|
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"Missing required parameter 'opencores,ip-clock-frequency'\n");
|
2016-08-04 07:38:44 +08:00
|
|
|
clk_disable_unprepare(i2c->clk);
|
2015-02-20 00:22:34 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
i2c->ip_clock_khz = clock_frequency / 1000;
|
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
|
"Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
|
|
|
|
|
} else {
|
|
|
|
|
i2c->ip_clock_khz = val / 1000;
|
|
|
|
|
if (clock_frequency_present)
|
|
|
|
|
i2c->bus_clock_khz = clock_frequency / 1000;
|
2015-02-02 23:28:12 +08:00
|
|
|
}
|
2010-11-25 00:26:20 +08:00
|
|
|
}
|
|
|
|
|
|
2012-07-13 21:44:25 +08:00
|
|
|
of_property_read_u32(pdev->dev.of_node, "reg-io-width",
|
|
|
|
|
&i2c->reg_io_width);
|
2012-11-15 23:50:59 +08:00
|
|
|
|
|
|
|
|
match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
|
2013-02-19 05:33:19 +08:00
|
|
|
if (match && (long)match->data == TYPE_GRLIB) {
|
2012-11-15 23:50:59 +08:00
|
|
|
dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
|
|
|
|
|
i2c->setreg = oc_setreg_grlib;
|
|
|
|
|
i2c->getreg = oc_getreg_grlib;
|
|
|
|
|
}
|
|
|
|
|
|
2010-11-25 00:26:20 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#else
|
2019-02-14 16:51:34 +08:00
|
|
|
#define ocores_i2c_of_probe(pdev, i2c) -ENODEV
|
2010-11-25 00:26:20 +08:00
|
|
|
#endif
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2012-11-28 04:59:38 +08:00
|
|
|
static int ocores_i2c_probe(struct platform_device *pdev)
|
2006-06-05 02:01:08 +08:00
|
|
|
{
|
|
|
|
|
struct ocores_i2c *i2c;
|
|
|
|
|
struct ocores_i2c_platform_data *pdata;
|
2012-11-15 23:50:58 +08:00
|
|
|
struct resource *res;
|
|
|
|
|
int irq;
|
2006-06-05 02:01:08 +08:00
|
|
|
int ret;
|
2009-06-05 21:40:32 +08:00
|
|
|
int i;
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2010-11-25 00:26:21 +08:00
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
|
2006-06-05 02:01:08 +08:00
|
|
|
if (!i2c)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2019-02-14 16:51:30 +08:00
|
|
|
spin_lock_init(&i2c->process_lock);
|
|
|
|
|
|
2013-08-14 17:11:27 +08:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2019-02-14 11:24:49 +08:00
|
|
|
if (res) {
|
|
|
|
|
i2c->base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
|
if (IS_ERR(i2c->base))
|
|
|
|
|
return PTR_ERR(i2c->base);
|
|
|
|
|
} else {
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
|
|
|
|
if (!res)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
i2c->iobase = res->start;
|
|
|
|
|
if (!devm_request_region(&pdev->dev, res->start,
|
|
|
|
|
resource_size(res),
|
|
|
|
|
pdev->name)) {
|
|
|
|
|
dev_err(&pdev->dev, "Can't get I/O resource.\n");
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
}
|
|
|
|
|
i2c->setreg = oc_setreg_io_8;
|
|
|
|
|
i2c->getreg = oc_getreg_io_8;
|
|
|
|
|
}
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2013-07-30 15:59:33 +08:00
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
2010-11-25 00:26:20 +08:00
|
|
|
if (pdata) {
|
2012-07-13 21:44:23 +08:00
|
|
|
i2c->reg_shift = pdata->reg_shift;
|
2012-07-13 21:44:25 +08:00
|
|
|
i2c->reg_io_width = pdata->reg_io_width;
|
2015-02-02 23:28:12 +08:00
|
|
|
i2c->ip_clock_khz = pdata->clock_khz;
|
2019-02-14 11:24:50 +08:00
|
|
|
if (pdata->bus_khz)
|
|
|
|
|
i2c->bus_clock_khz = pdata->bus_khz;
|
|
|
|
|
else
|
|
|
|
|
i2c->bus_clock_khz = 100;
|
2010-11-25 00:26:20 +08:00
|
|
|
} else {
|
|
|
|
|
ret = ocores_i2c_of_probe(pdev, i2c);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-13 21:44:25 +08:00
|
|
|
if (i2c->reg_io_width == 0)
|
|
|
|
|
i2c->reg_io_width = 1; /* Set to default value */
|
|
|
|
|
|
2012-11-15 23:50:59 +08:00
|
|
|
if (!i2c->setreg || !i2c->getreg) {
|
2015-10-07 07:45:11 +08:00
|
|
|
bool be = pdata ? pdata->big_endian :
|
|
|
|
|
of_device_is_big_endian(pdev->dev.of_node);
|
|
|
|
|
|
2012-11-15 23:50:59 +08:00
|
|
|
switch (i2c->reg_io_width) {
|
|
|
|
|
case 1:
|
|
|
|
|
i2c->setreg = oc_setreg_8;
|
|
|
|
|
i2c->getreg = oc_getreg_8;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 2:
|
2015-10-07 07:45:11 +08:00
|
|
|
i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
|
|
|
|
|
i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
|
2012-11-15 23:50:59 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 4:
|
2015-10-07 07:45:11 +08:00
|
|
|
i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
|
|
|
|
|
i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
|
2012-11-15 23:50:59 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
|
|
|
|
|
i2c->reg_io_width);
|
2016-08-04 07:38:44 +08:00
|
|
|
ret = -EINVAL;
|
|
|
|
|
goto err_clk;
|
2012-11-15 23:50:59 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-02-14 16:51:32 +08:00
|
|
|
init_waitqueue_head(&i2c->wait);
|
|
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
|
if (irq == -ENXIO) {
|
2019-04-03 20:40:15 +08:00
|
|
|
ocores_algorithm.master_xfer = ocores_xfer_polling;
|
2019-02-14 16:51:32 +08:00
|
|
|
} else {
|
|
|
|
|
if (irq < 0)
|
|
|
|
|
return irq;
|
|
|
|
|
}
|
|
|
|
|
|
2019-04-03 20:40:15 +08:00
|
|
|
if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
|
2019-02-14 16:51:32 +08:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
|
|
|
|
|
pdev->name, i2c);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
|
|
|
|
goto err_clk;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-02 23:28:12 +08:00
|
|
|
ret = ocores_init(&pdev->dev, i2c);
|
|
|
|
|
if (ret)
|
2016-08-04 07:38:44 +08:00
|
|
|
goto err_clk;
|
2006-06-05 02:01:08 +08:00
|
|
|
|
|
|
|
|
/* hook up driver to tree */
|
|
|
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
|
i2c->adap = ocores_adapter;
|
|
|
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
|
|
|
i2c->adap.dev.parent = &pdev->dev;
|
2010-11-25 00:26:20 +08:00
|
|
|
i2c->adap.dev.of_node = pdev->dev.of_node;
|
2006-06-05 02:01:08 +08:00
|
|
|
|
|
|
|
|
/* add i2c adapter to i2c tree */
|
|
|
|
|
ret = i2c_add_adapter(&i2c->adap);
|
2016-08-09 19:36:17 +08:00
|
|
|
if (ret)
|
2016-08-04 07:38:44 +08:00
|
|
|
goto err_clk;
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2009-06-05 21:40:32 +08:00
|
|
|
/* add in known devices to the bus */
|
2010-11-25 00:26:20 +08:00
|
|
|
if (pdata) {
|
|
|
|
|
for (i = 0; i < pdata->num_devices; i++)
|
|
|
|
|
i2c_new_device(&i2c->adap, pdata->devices + i);
|
|
|
|
|
}
|
2009-06-05 21:40:32 +08:00
|
|
|
|
2006-06-05 02:01:08 +08:00
|
|
|
return 0;
|
2016-08-04 07:38:44 +08:00
|
|
|
|
|
|
|
|
err_clk:
|
|
|
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
|
return ret;
|
2006-06-05 02:01:08 +08:00
|
|
|
}
|
|
|
|
|
|
2012-11-28 04:59:38 +08:00
|
|
|
static int ocores_i2c_remove(struct platform_device *pdev)
|
2006-06-05 02:01:08 +08:00
|
|
|
{
|
|
|
|
|
struct ocores_i2c *i2c = platform_get_drvdata(pdev);
|
2019-02-14 16:51:34 +08:00
|
|
|
u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
|
2006-06-05 02:01:08 +08:00
|
|
|
|
|
|
|
|
/* disable i2c logic */
|
2019-02-14 16:51:34 +08:00
|
|
|
ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
|
|
|
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl);
|
2006-06-05 02:01:08 +08:00
|
|
|
|
|
|
|
|
/* remove adapter & data */
|
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
|
|
2015-02-06 03:55:01 +08:00
|
|
|
if (!IS_ERR(i2c->clk))
|
|
|
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
|
|
2006-06-05 02:01:08 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-07-15 10:29:35 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2012-07-12 03:24:15 +08:00
|
|
|
static int ocores_i2c_suspend(struct device *dev)
|
2008-07-15 04:38:33 +08:00
|
|
|
{
|
2012-07-12 03:24:15 +08:00
|
|
|
struct ocores_i2c *i2c = dev_get_drvdata(dev);
|
2008-07-15 04:38:33 +08:00
|
|
|
u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
|
|
|
|
|
|
|
|
|
|
/* make sure the device is disabled */
|
2019-02-14 16:51:34 +08:00
|
|
|
ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
|
|
|
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl);
|
2008-07-15 04:38:33 +08:00
|
|
|
|
2015-02-06 03:55:01 +08:00
|
|
|
if (!IS_ERR(i2c->clk))
|
|
|
|
|
clk_disable_unprepare(i2c->clk);
|
2008-07-15 04:38:33 +08:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-12 03:24:15 +08:00
|
|
|
static int ocores_i2c_resume(struct device *dev)
|
2008-07-15 04:38:33 +08:00
|
|
|
{
|
2012-07-12 03:24:15 +08:00
|
|
|
struct ocores_i2c *i2c = dev_get_drvdata(dev);
|
2008-07-15 04:38:33 +08:00
|
|
|
|
2015-02-06 03:55:01 +08:00
|
|
|
if (!IS_ERR(i2c->clk)) {
|
2015-02-20 00:22:34 +08:00
|
|
|
unsigned long rate;
|
2015-02-06 03:55:01 +08:00
|
|
|
int ret = clk_prepare_enable(i2c->clk);
|
|
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(dev,
|
|
|
|
|
"clk_prepare_enable failed: %d\n", ret);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2015-02-20 00:22:34 +08:00
|
|
|
rate = clk_get_rate(i2c->clk) / 1000;
|
|
|
|
|
if (rate)
|
|
|
|
|
i2c->ip_clock_khz = rate;
|
2015-02-06 03:55:01 +08:00
|
|
|
}
|
2015-02-02 23:28:12 +08:00
|
|
|
return ocores_init(dev, i2c);
|
2008-07-15 04:38:33 +08:00
|
|
|
}
|
2012-07-12 03:24:15 +08:00
|
|
|
|
|
|
|
|
static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
|
|
|
|
|
#define OCORES_I2C_PM (&ocores_i2c_pm)
|
2008-07-15 04:38:33 +08:00
|
|
|
#else
|
2012-07-12 03:24:15 +08:00
|
|
|
#define OCORES_I2C_PM NULL
|
2008-07-15 04:38:33 +08:00
|
|
|
#endif
|
|
|
|
|
|
2006-06-05 02:01:08 +08:00
|
|
|
static struct platform_driver ocores_i2c_driver = {
|
2008-07-15 04:38:33 +08:00
|
|
|
.probe = ocores_i2c_probe,
|
2012-11-28 04:59:38 +08:00
|
|
|
.remove = ocores_i2c_remove,
|
2008-07-15 04:38:33 +08:00
|
|
|
.driver = {
|
2006-06-05 02:01:08 +08:00
|
|
|
.name = "ocores-i2c",
|
2011-01-22 00:24:48 +08:00
|
|
|
.of_match_table = ocores_i2c_match,
|
2012-07-12 03:24:15 +08:00
|
|
|
.pm = OCORES_I2C_PM,
|
2006-06-05 02:01:08 +08:00
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2012-01-13 03:32:04 +08:00
|
|
|
module_platform_driver(ocores_i2c_driver);
|
2006-06-05 02:01:08 +08:00
|
|
|
|
2018-08-23 00:16:07 +08:00
|
|
|
MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
|
2006-06-05 02:01:08 +08:00
|
|
|
MODULE_DESCRIPTION("OpenCores I2C bus driver");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
2012-01-13 03:32:04 +08:00
|
|
|
MODULE_ALIAS("platform:ocores-i2c");
|