2017-05-24 22:10:34 +08:00
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/*
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* Copyright (C) 2017 Marvell
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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2017-06-15 15:56:17 +08:00
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#include <crypto/hmac.h>
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2017-05-24 22:10:34 +08:00
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#include <crypto/sha.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include "safexcel.h"
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struct safexcel_ahash_ctx {
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struct safexcel_context base;
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struct safexcel_crypto_priv *priv;
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u32 alg;
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u32 ipad[SHA1_DIGEST_SIZE / sizeof(u32)];
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u32 opad[SHA1_DIGEST_SIZE / sizeof(u32)];
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};
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struct safexcel_ahash_req {
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bool last_req;
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bool finish;
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bool hmac;
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2017-12-11 19:10:55 +08:00
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bool needs_inv;
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2017-05-24 22:10:34 +08:00
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2017-12-27 00:21:16 +08:00
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int nents;
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2018-02-26 21:45:10 +08:00
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dma_addr_t result_dma;
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2017-12-27 00:21:16 +08:00
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2018-03-19 16:21:13 +08:00
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u32 digest;
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2017-05-24 22:10:34 +08:00
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u8 state_sz; /* expected sate size, only set once */
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2017-12-11 19:10:58 +08:00
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u32 state[SHA256_DIGEST_SIZE / sizeof(u32)] __aligned(sizeof(u32));
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2017-05-24 22:10:34 +08:00
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u64 len;
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u64 processed;
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u8 cache[SHA256_BLOCK_SIZE] __aligned(sizeof(u32));
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2018-02-26 21:45:11 +08:00
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dma_addr_t cache_dma;
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unsigned int cache_sz;
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2017-05-24 22:10:34 +08:00
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u8 cache_next[SHA256_BLOCK_SIZE] __aligned(sizeof(u32));
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};
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struct safexcel_ahash_export_state {
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u64 len;
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u64 processed;
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2018-03-19 16:21:13 +08:00
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u32 digest;
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2017-05-24 22:10:34 +08:00
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u32 state[SHA256_DIGEST_SIZE / sizeof(u32)];
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u8 cache[SHA256_BLOCK_SIZE];
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};
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static void safexcel_hash_token(struct safexcel_command_desc *cdesc,
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u32 input_length, u32 result_length)
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{
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struct safexcel_token *token =
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(struct safexcel_token *)cdesc->control_data.token;
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token[0].opcode = EIP197_TOKEN_OPCODE_DIRECTION;
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token[0].packet_length = input_length;
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token[0].stat = EIP197_TOKEN_STAT_LAST_HASH;
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token[0].instructions = EIP197_TOKEN_INS_TYPE_HASH;
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token[1].opcode = EIP197_TOKEN_OPCODE_INSERT;
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token[1].packet_length = result_length;
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token[1].stat = EIP197_TOKEN_STAT_LAST_HASH |
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EIP197_TOKEN_STAT_LAST_PACKET;
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token[1].instructions = EIP197_TOKEN_INS_TYPE_OUTPUT |
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EIP197_TOKEN_INS_INSERT_HASH_DIGEST;
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}
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static void safexcel_context_control(struct safexcel_ahash_ctx *ctx,
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struct safexcel_ahash_req *req,
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struct safexcel_command_desc *cdesc,
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unsigned int digestsize,
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unsigned int blocksize)
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{
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int i;
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cdesc->control_data.control0 |= CONTEXT_CONTROL_TYPE_HASH_OUT;
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cdesc->control_data.control0 |= ctx->alg;
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2018-03-19 16:21:13 +08:00
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cdesc->control_data.control0 |= req->digest;
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2017-05-24 22:10:34 +08:00
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2018-03-19 16:21:13 +08:00
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if (req->digest == CONTEXT_CONTROL_DIGEST_PRECOMPUTED) {
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2017-05-24 22:10:34 +08:00
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if (req->processed) {
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if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA1)
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cdesc->control_data.control0 |= CONTEXT_CONTROL_SIZE(6);
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else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA224 ||
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ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA256)
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cdesc->control_data.control0 |= CONTEXT_CONTROL_SIZE(9);
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cdesc->control_data.control1 |= CONTEXT_CONTROL_DIGEST_CNT;
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} else {
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cdesc->control_data.control0 |= CONTEXT_CONTROL_RESTART_HASH;
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}
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if (!req->finish)
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cdesc->control_data.control0 |= CONTEXT_CONTROL_NO_FINISH_HASH;
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/*
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* Copy the input digest if needed, and setup the context
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* fields. Do this now as we need it to setup the first command
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* descriptor.
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*/
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if (req->processed) {
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for (i = 0; i < digestsize / sizeof(u32); i++)
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ctx->base.ctxr->data[i] = cpu_to_le32(req->state[i]);
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if (req->finish)
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ctx->base.ctxr->data[i] = cpu_to_le32(req->processed / blocksize);
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}
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2018-03-19 16:21:13 +08:00
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} else if (req->digest == CONTEXT_CONTROL_DIGEST_HMAC) {
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2017-05-24 22:10:34 +08:00
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cdesc->control_data.control0 |= CONTEXT_CONTROL_SIZE(10);
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memcpy(ctx->base.ctxr->data, ctx->ipad, digestsize);
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memcpy(ctx->base.ctxr->data + digestsize / sizeof(u32),
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ctx->opad, digestsize);
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}
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}
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2017-12-11 19:10:55 +08:00
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static int safexcel_handle_req_result(struct safexcel_crypto_priv *priv, int ring,
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struct crypto_async_request *async,
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bool *should_complete, int *ret)
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2017-05-24 22:10:34 +08:00
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{
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struct safexcel_result_desc *rdesc;
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struct ahash_request *areq = ahash_request_cast(async);
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
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struct safexcel_ahash_req *sreq = ahash_request_ctx(areq);
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2017-12-11 19:10:58 +08:00
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int cache_len;
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2017-05-24 22:10:34 +08:00
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*ret = 0;
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spin_lock_bh(&priv->ring[ring].egress_lock);
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rdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].rdr);
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if (IS_ERR(rdesc)) {
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dev_err(priv->dev,
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"hash: result: could not retrieve the result descriptor\n");
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*ret = PTR_ERR(rdesc);
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} else if (rdesc->result_data.error_code) {
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dev_err(priv->dev,
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"hash: result: result descriptor error (%d)\n",
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rdesc->result_data.error_code);
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*ret = -EINVAL;
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}
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safexcel_complete(priv, ring);
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spin_unlock_bh(&priv->ring[ring].egress_lock);
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if (sreq->finish)
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2017-12-11 19:10:58 +08:00
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memcpy(areq->result, sreq->state,
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crypto_ahash_digestsize(ahash));
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2017-05-24 22:10:34 +08:00
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2017-12-27 00:21:16 +08:00
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if (sreq->nents) {
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dma_unmap_sg(priv->dev, areq->src, sreq->nents, DMA_TO_DEVICE);
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sreq->nents = 0;
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}
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2017-05-24 22:10:34 +08:00
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2018-02-26 21:45:10 +08:00
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if (sreq->result_dma) {
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dma_unmap_single(priv->dev, sreq->result_dma, sreq->state_sz,
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DMA_FROM_DEVICE);
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sreq->result_dma = 0;
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}
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2018-02-26 21:45:11 +08:00
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if (sreq->cache_dma) {
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dma_unmap_single(priv->dev, sreq->cache_dma, sreq->cache_sz,
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DMA_TO_DEVICE);
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sreq->cache_dma = 0;
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}
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2017-05-24 22:10:34 +08:00
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cache_len = sreq->len - sreq->processed;
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if (cache_len)
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memcpy(sreq->cache, sreq->cache_next, cache_len);
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*should_complete = true;
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return 1;
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}
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2017-12-11 19:10:55 +08:00
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static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring,
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struct safexcel_request *request,
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int *commands, int *results)
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2017-05-24 22:10:34 +08:00
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{
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struct ahash_request *areq = ahash_request_cast(async);
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
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struct safexcel_ahash_req *req = ahash_request_ctx(areq);
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struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
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struct safexcel_crypto_priv *priv = ctx->priv;
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struct safexcel_command_desc *cdesc, *first_cdesc = NULL;
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struct safexcel_result_desc *rdesc;
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struct scatterlist *sg;
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2017-12-27 00:21:16 +08:00
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int i, queued, len, cache_len, extra, n_cdesc = 0, ret = 0;
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2017-05-24 22:10:34 +08:00
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queued = len = req->len - req->processed;
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2018-02-13 16:26:53 +08:00
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if (queued <= crypto_ahash_blocksize(ahash))
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2017-05-24 22:10:34 +08:00
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cache_len = queued;
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else
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cache_len = queued - areq->nbytes;
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2017-12-27 00:21:17 +08:00
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if (!req->last_req) {
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/* If this is not the last request and the queued data does not
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* fit into full blocks, cache it for the next send() call.
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*/
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extra = queued & (crypto_ahash_blocksize(ahash) - 1);
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if (!extra)
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/* If this is not the last request and the queued data
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* is a multiple of a block, cache the last one for now.
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*/
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2018-02-13 16:26:52 +08:00
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extra = crypto_ahash_blocksize(ahash);
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2017-12-27 00:21:17 +08:00
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if (extra) {
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sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
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req->cache_next, extra,
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areq->nbytes - extra);
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queued -= extra;
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len -= extra;
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if (!queued) {
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*commands = 0;
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*results = 0;
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return 0;
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}
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}
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2017-05-24 22:10:34 +08:00
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}
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spin_lock_bh(&priv->ring[ring].egress_lock);
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/* Add a command descriptor for the cached data, if any */
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if (cache_len) {
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2018-02-26 21:45:11 +08:00
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req->cache_dma = dma_map_single(priv->dev, req->cache,
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cache_len, DMA_TO_DEVICE);
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2018-03-13 22:54:03 +08:00
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if (dma_mapping_error(priv->dev, req->cache_dma)) {
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spin_unlock_bh(&priv->ring[ring].egress_lock);
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2018-02-26 21:45:11 +08:00
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return -EINVAL;
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2018-03-13 22:54:03 +08:00
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}
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2017-05-24 22:10:34 +08:00
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2018-02-26 21:45:11 +08:00
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req->cache_sz = cache_len;
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2017-05-24 22:10:34 +08:00
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first_cdesc = safexcel_add_cdesc(priv, ring, 1,
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(cache_len == len),
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2018-02-26 21:45:11 +08:00
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req->cache_dma, cache_len, len,
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2017-05-24 22:10:34 +08:00
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ctx->base.ctxr_dma);
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if (IS_ERR(first_cdesc)) {
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ret = PTR_ERR(first_cdesc);
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goto unmap_cache;
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}
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n_cdesc++;
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queued -= cache_len;
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if (!queued)
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goto send_command;
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}
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/* Now handle the current ahash request buffer(s) */
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2017-12-27 00:21:16 +08:00
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req->nents = dma_map_sg(priv->dev, areq->src,
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sg_nents_for_len(areq->src, areq->nbytes),
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DMA_TO_DEVICE);
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if (!req->nents) {
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2017-05-24 22:10:34 +08:00
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ret = -ENOMEM;
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goto cdesc_rollback;
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}
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2017-12-27 00:21:16 +08:00
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for_each_sg(areq->src, sg, req->nents, i) {
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2017-05-24 22:10:34 +08:00
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int sglen = sg_dma_len(sg);
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/* Do not overflow the request */
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if (queued - sglen < 0)
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sglen = queued;
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cdesc = safexcel_add_cdesc(priv, ring, !n_cdesc,
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!(queued - sglen), sg_dma_address(sg),
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sglen, len, ctx->base.ctxr_dma);
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if (IS_ERR(cdesc)) {
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ret = PTR_ERR(cdesc);
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goto cdesc_rollback;
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}
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n_cdesc++;
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if (n_cdesc == 1)
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first_cdesc = cdesc;
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queued -= sglen;
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if (!queued)
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break;
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}
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send_command:
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/* Setup the context options */
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safexcel_context_control(ctx, req, first_cdesc, req->state_sz,
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crypto_ahash_blocksize(ahash));
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/* Add the token */
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safexcel_hash_token(first_cdesc, len, req->state_sz);
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2018-02-26 21:45:10 +08:00
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req->result_dma = dma_map_single(priv->dev, req->state, req->state_sz,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(priv->dev, req->result_dma)) {
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2017-05-24 22:10:34 +08:00
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ret = -EINVAL;
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goto cdesc_rollback;
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}
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/* Add a result descriptor */
|
2018-02-26 21:45:10 +08:00
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rdesc = safexcel_add_rdesc(priv, ring, 1, 1, req->result_dma,
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2017-05-24 22:10:34 +08:00
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req->state_sz);
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if (IS_ERR(rdesc)) {
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ret = PTR_ERR(rdesc);
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2018-02-13 16:26:57 +08:00
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goto unmap_result;
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2017-05-24 22:10:34 +08:00
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}
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spin_unlock_bh(&priv->ring[ring].egress_lock);
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2017-06-15 15:56:23 +08:00
|
|
|
req->processed += len;
|
|
|
|
request->req = &areq->base;
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
*commands = n_cdesc;
|
|
|
|
*results = 1;
|
|
|
|
return 0;
|
|
|
|
|
2018-02-13 16:26:57 +08:00
|
|
|
unmap_result:
|
|
|
|
dma_unmap_sg(priv->dev, areq->src, req->nents, DMA_TO_DEVICE);
|
2017-05-24 22:10:34 +08:00
|
|
|
cdesc_rollback:
|
|
|
|
for (i = 0; i < n_cdesc; i++)
|
|
|
|
safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
|
|
|
|
unmap_cache:
|
2018-02-26 21:45:11 +08:00
|
|
|
if (req->cache_dma) {
|
|
|
|
dma_unmap_single(priv->dev, req->cache_dma, req->cache_sz,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
req->cache_sz = 0;
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool safexcel_ahash_needs_inv_get(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
|
|
|
unsigned int state_w_sz = req->state_sz / sizeof(u32);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < state_w_sz; i++)
|
|
|
|
if (ctx->base.ctxr->data[i] != cpu_to_le32(req->state[i]))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (ctx->base.ctxr->data[state_w_sz] !=
|
|
|
|
cpu_to_le32(req->processed / crypto_ahash_blocksize(ahash)))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_handle_inv_result(struct safexcel_crypto_priv *priv,
|
|
|
|
int ring,
|
|
|
|
struct crypto_async_request *async,
|
|
|
|
bool *should_complete, int *ret)
|
|
|
|
{
|
|
|
|
struct safexcel_result_desc *rdesc;
|
|
|
|
struct ahash_request *areq = ahash_request_cast(async);
|
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(ahash);
|
|
|
|
int enq_ret;
|
|
|
|
|
|
|
|
*ret = 0;
|
|
|
|
|
|
|
|
spin_lock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
rdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].rdr);
|
|
|
|
if (IS_ERR(rdesc)) {
|
|
|
|
dev_err(priv->dev,
|
|
|
|
"hash: invalidate: could not retrieve the result descriptor\n");
|
|
|
|
*ret = PTR_ERR(rdesc);
|
|
|
|
} else if (rdesc->result_data.error_code) {
|
|
|
|
dev_err(priv->dev,
|
|
|
|
"hash: invalidate: result descriptor error (%d)\n",
|
|
|
|
rdesc->result_data.error_code);
|
|
|
|
*ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
safexcel_complete(priv, ring);
|
|
|
|
spin_unlock_bh(&priv->ring[ring].egress_lock);
|
|
|
|
|
|
|
|
if (ctx->base.exit_inv) {
|
|
|
|
dma_pool_free(priv->context_pool, ctx->base.ctxr,
|
|
|
|
ctx->base.ctxr_dma);
|
|
|
|
|
|
|
|
*should_complete = true;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
ring = safexcel_select_ring(priv);
|
|
|
|
ctx->base.ring = ring;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_lock_bh(&priv->ring[ring].queue_lock);
|
|
|
|
enq_ret = crypto_enqueue_request(&priv->ring[ring].queue, async);
|
|
|
|
spin_unlock_bh(&priv->ring[ring].queue_lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
if (enq_ret != -EINPROGRESS)
|
|
|
|
*ret = enq_ret;
|
|
|
|
|
2017-12-14 22:26:51 +08:00
|
|
|
queue_work(priv->ring[ring].workqueue,
|
|
|
|
&priv->ring[ring].work_data.work);
|
2017-06-15 15:56:24 +08:00
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
*should_complete = false;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2017-12-11 19:10:55 +08:00
|
|
|
static int safexcel_handle_result(struct safexcel_crypto_priv *priv, int ring,
|
|
|
|
struct crypto_async_request *async,
|
|
|
|
bool *should_complete, int *ret)
|
|
|
|
{
|
|
|
|
struct ahash_request *areq = ahash_request_cast(async);
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
int err;
|
|
|
|
|
2017-12-14 22:26:58 +08:00
|
|
|
BUG_ON(priv->version == EIP97 && req->needs_inv);
|
|
|
|
|
2017-12-11 19:10:55 +08:00
|
|
|
if (req->needs_inv) {
|
|
|
|
req->needs_inv = false;
|
|
|
|
err = safexcel_handle_inv_result(priv, ring, async,
|
|
|
|
should_complete, ret);
|
|
|
|
} else {
|
|
|
|
err = safexcel_handle_req_result(priv, ring, async,
|
|
|
|
should_complete, ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
static int safexcel_ahash_send_inv(struct crypto_async_request *async,
|
|
|
|
int ring, struct safexcel_request *request,
|
|
|
|
int *commands, int *results)
|
|
|
|
{
|
|
|
|
struct ahash_request *areq = ahash_request_cast(async);
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
int ret;
|
|
|
|
|
2017-12-14 22:26:50 +08:00
|
|
|
ret = safexcel_invalidate_cache(async, ctx->priv,
|
2017-05-24 22:10:34 +08:00
|
|
|
ctx->base.ctxr_dma, ring, request);
|
|
|
|
if (unlikely(ret))
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
*commands = 1;
|
|
|
|
*results = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-12-11 19:10:55 +08:00
|
|
|
static int safexcel_ahash_send(struct crypto_async_request *async,
|
|
|
|
int ring, struct safexcel_request *request,
|
|
|
|
int *commands, int *results)
|
|
|
|
{
|
|
|
|
struct ahash_request *areq = ahash_request_cast(async);
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (req->needs_inv)
|
|
|
|
ret = safexcel_ahash_send_inv(async, ring, request,
|
|
|
|
commands, results);
|
|
|
|
else
|
|
|
|
ret = safexcel_ahash_send_req(async, ring, request,
|
|
|
|
commands, results);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
static int safexcel_ahash_exit_inv(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct safexcel_crypto_priv *priv = ctx->priv;
|
2017-12-11 19:10:57 +08:00
|
|
|
AHASH_REQUEST_ON_STACK(req, __crypto_ahash_cast(tfm));
|
|
|
|
struct safexcel_ahash_req *rctx = ahash_request_ctx(req);
|
2017-09-12 18:12:16 +08:00
|
|
|
struct safexcel_inv_result result = {};
|
2017-06-15 15:56:24 +08:00
|
|
|
int ring = ctx->base.ring;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-12-11 19:10:57 +08:00
|
|
|
memset(req, 0, sizeof(struct ahash_request));
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
/* create invalidation request */
|
|
|
|
init_completion(&result.completion);
|
2017-12-11 19:10:57 +08:00
|
|
|
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
|
2017-05-24 22:10:34 +08:00
|
|
|
safexcel_inv_complete, &result);
|
|
|
|
|
2017-12-11 19:10:57 +08:00
|
|
|
ahash_request_set_tfm(req, __crypto_ahash_cast(tfm));
|
|
|
|
ctx = crypto_tfm_ctx(req->base.tfm);
|
2017-05-24 22:10:34 +08:00
|
|
|
ctx->base.exit_inv = true;
|
2017-12-11 19:10:55 +08:00
|
|
|
rctx->needs_inv = true;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_lock_bh(&priv->ring[ring].queue_lock);
|
2017-12-11 19:10:57 +08:00
|
|
|
crypto_enqueue_request(&priv->ring[ring].queue, &req->base);
|
2017-06-15 15:56:24 +08:00
|
|
|
spin_unlock_bh(&priv->ring[ring].queue_lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-12-14 22:26:51 +08:00
|
|
|
queue_work(priv->ring[ring].workqueue,
|
|
|
|
&priv->ring[ring].work_data.work);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2018-02-13 16:26:55 +08:00
|
|
|
wait_for_completion(&result.completion);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
if (result.error) {
|
|
|
|
dev_warn(priv->dev, "hash: completion error (%d)\n",
|
|
|
|
result.error);
|
|
|
|
return result.error;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-12-14 22:26:46 +08:00
|
|
|
/* safexcel_ahash_cache: cache data until at least one request can be sent to
|
|
|
|
* the engine, aka. when there is at least 1 block size in the pipe.
|
|
|
|
*/
|
2017-05-24 22:10:34 +08:00
|
|
|
static int safexcel_ahash_cache(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
|
|
|
int queued, cache_len;
|
|
|
|
|
2017-12-14 22:26:46 +08:00
|
|
|
/* cache_len: everyting accepted by the driver but not sent yet,
|
|
|
|
* tot sz handled by update() - last req sz - tot sz handled by send()
|
|
|
|
*/
|
2017-05-24 22:10:34 +08:00
|
|
|
cache_len = req->len - areq->nbytes - req->processed;
|
2017-12-14 22:26:46 +08:00
|
|
|
/* queued: everything accepted by the driver which will be handled by
|
|
|
|
* the next send() calls.
|
|
|
|
* tot sz handled by update() - tot sz handled by send()
|
|
|
|
*/
|
2017-05-24 22:10:34 +08:00
|
|
|
queued = req->len - req->processed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In case there isn't enough bytes to proceed (less than a
|
|
|
|
* block size), cache the data until we have enough.
|
|
|
|
*/
|
|
|
|
if (cache_len + areq->nbytes <= crypto_ahash_blocksize(ahash)) {
|
|
|
|
sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
|
|
|
|
req->cache + cache_len,
|
|
|
|
areq->nbytes, 0);
|
|
|
|
return areq->nbytes;
|
|
|
|
}
|
|
|
|
|
2017-12-14 22:26:44 +08:00
|
|
|
/* We couldn't cache all the data */
|
2017-05-24 22:10:34 +08:00
|
|
|
return -E2BIG;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_enqueue(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
struct safexcel_crypto_priv *priv = ctx->priv;
|
2017-06-15 15:56:24 +08:00
|
|
|
int ret, ring;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-12-11 19:10:55 +08:00
|
|
|
req->needs_inv = false;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
if (ctx->base.ctxr) {
|
2017-12-14 22:26:58 +08:00
|
|
|
if (priv->version == EIP197 &&
|
|
|
|
!ctx->base.needs_inv && req->processed &&
|
2018-03-19 16:21:13 +08:00
|
|
|
req->digest == CONTEXT_CONTROL_DIGEST_PRECOMPUTED)
|
2017-12-14 22:26:47 +08:00
|
|
|
/* We're still setting needs_inv here, even though it is
|
|
|
|
* cleared right away, because the needs_inv flag can be
|
|
|
|
* set in other functions and we want to keep the same
|
|
|
|
* logic.
|
|
|
|
*/
|
|
|
|
ctx->base.needs_inv = safexcel_ahash_needs_inv_get(areq);
|
|
|
|
|
2017-12-11 19:10:55 +08:00
|
|
|
if (ctx->base.needs_inv) {
|
|
|
|
ctx->base.needs_inv = false;
|
|
|
|
req->needs_inv = true;
|
|
|
|
}
|
2017-05-24 22:10:34 +08:00
|
|
|
} else {
|
|
|
|
ctx->base.ring = safexcel_select_ring(priv);
|
|
|
|
ctx->base.ctxr = dma_pool_zalloc(priv->context_pool,
|
|
|
|
EIP197_GFP_FLAGS(areq->base),
|
|
|
|
&ctx->base.ctxr_dma);
|
|
|
|
if (!ctx->base.ctxr)
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2017-06-15 15:56:24 +08:00
|
|
|
ring = ctx->base.ring;
|
|
|
|
|
|
|
|
spin_lock_bh(&priv->ring[ring].queue_lock);
|
|
|
|
ret = crypto_enqueue_request(&priv->ring[ring].queue, &areq->base);
|
|
|
|
spin_unlock_bh(&priv->ring[ring].queue_lock);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
2017-12-14 22:26:51 +08:00
|
|
|
queue_work(priv->ring[ring].workqueue,
|
|
|
|
&priv->ring[ring].work_data.work);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_update(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
|
|
|
|
|
|
|
/* If the request is 0 length, do nothing */
|
|
|
|
if (!areq->nbytes)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
req->len += areq->nbytes;
|
|
|
|
|
|
|
|
safexcel_ahash_cache(areq);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We're not doing partial updates when performing an hmac request.
|
|
|
|
* Everything will be handled by the final() call.
|
|
|
|
*/
|
2018-03-19 16:21:13 +08:00
|
|
|
if (req->digest == CONTEXT_CONTROL_DIGEST_HMAC)
|
2017-05-24 22:10:34 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (req->hmac)
|
|
|
|
return safexcel_ahash_enqueue(areq);
|
|
|
|
|
|
|
|
if (!req->last_req &&
|
|
|
|
req->len - req->processed > crypto_ahash_blocksize(ahash))
|
|
|
|
return safexcel_ahash_enqueue(areq);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_final(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
|
|
|
|
req->last_req = true;
|
|
|
|
req->finish = true;
|
|
|
|
|
|
|
|
/* If we have an overall 0 length request */
|
|
|
|
if (!(req->len + areq->nbytes)) {
|
|
|
|
if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA1)
|
|
|
|
memcpy(areq->result, sha1_zero_message_hash,
|
|
|
|
SHA1_DIGEST_SIZE);
|
|
|
|
else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA224)
|
|
|
|
memcpy(areq->result, sha224_zero_message_hash,
|
|
|
|
SHA224_DIGEST_SIZE);
|
|
|
|
else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA256)
|
|
|
|
memcpy(areq->result, sha256_zero_message_hash,
|
|
|
|
SHA256_DIGEST_SIZE);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return safexcel_ahash_enqueue(areq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_finup(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
req->last_req = true;
|
|
|
|
req->finish = true;
|
|
|
|
|
|
|
|
safexcel_ahash_update(areq);
|
|
|
|
return safexcel_ahash_final(areq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_export(struct ahash_request *areq, void *out)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
struct safexcel_ahash_export_state *export = out;
|
|
|
|
|
|
|
|
export->len = req->len;
|
|
|
|
export->processed = req->processed;
|
|
|
|
|
2018-03-19 16:21:13 +08:00
|
|
|
export->digest = req->digest;
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
memcpy(export->state, req->state, req->state_sz);
|
|
|
|
memcpy(export->cache, req->cache, crypto_ahash_blocksize(ahash));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_import(struct ahash_request *areq, const void *in)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
const struct safexcel_ahash_export_state *export = in;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = crypto_ahash_init(areq);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
req->len = export->len;
|
|
|
|
req->processed = export->processed;
|
|
|
|
|
2018-03-19 16:21:13 +08:00
|
|
|
req->digest = export->digest;
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
|
memcpy(req->cache, export->cache, crypto_ahash_blocksize(ahash));
|
|
|
|
memcpy(req->state, export->state, req->state_sz);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_ahash_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct safexcel_alg_template *tmpl =
|
|
|
|
container_of(__crypto_ahash_alg(tfm->__crt_alg),
|
|
|
|
struct safexcel_alg_template, alg.ahash);
|
|
|
|
|
|
|
|
ctx->priv = tmpl->priv;
|
2017-12-11 19:10:55 +08:00
|
|
|
ctx->base.send = safexcel_ahash_send;
|
|
|
|
ctx->base.handle_result = safexcel_handle_result;
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
|
|
sizeof(struct safexcel_ahash_req));
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_sha1_init(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
memset(req, 0, sizeof(*req));
|
|
|
|
|
|
|
|
req->state[0] = SHA1_H0;
|
|
|
|
req->state[1] = SHA1_H1;
|
|
|
|
req->state[2] = SHA1_H2;
|
|
|
|
req->state[3] = SHA1_H3;
|
|
|
|
req->state[4] = SHA1_H4;
|
|
|
|
|
|
|
|
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA1;
|
2018-03-19 16:21:13 +08:00
|
|
|
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
|
2017-05-24 22:10:34 +08:00
|
|
|
req->state_sz = SHA1_DIGEST_SIZE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_sha1_digest(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
int ret = safexcel_sha1_init(areq);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return safexcel_ahash_finup(areq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void safexcel_ahash_cra_exit(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct safexcel_crypto_priv *priv = ctx->priv;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* context not allocated, skip invalidation */
|
|
|
|
if (!ctx->base.ctxr)
|
|
|
|
return;
|
|
|
|
|
2017-12-14 22:26:58 +08:00
|
|
|
if (priv->version == EIP197) {
|
|
|
|
ret = safexcel_ahash_exit_inv(tfm);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(priv->dev, "hash: invalidation error %d\n", ret);
|
|
|
|
} else {
|
|
|
|
dma_pool_free(priv->context_pool, ctx->base.ctxr,
|
|
|
|
ctx->base.ctxr_dma);
|
|
|
|
}
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
struct safexcel_alg_template safexcel_alg_sha1 = {
|
|
|
|
.type = SAFEXCEL_ALG_TYPE_AHASH,
|
|
|
|
.alg.ahash = {
|
|
|
|
.init = safexcel_sha1_init,
|
|
|
|
.update = safexcel_ahash_update,
|
|
|
|
.final = safexcel_ahash_final,
|
|
|
|
.finup = safexcel_ahash_finup,
|
|
|
|
.digest = safexcel_sha1_digest,
|
|
|
|
.export = safexcel_ahash_export,
|
|
|
|
.import = safexcel_ahash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct safexcel_ahash_export_state),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "sha1",
|
|
|
|
.cra_driver_name = "safexcel-sha1",
|
|
|
|
.cra_priority = 300,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
|
|
|
|
.cra_init = safexcel_ahash_cra_init,
|
|
|
|
.cra_exit = safexcel_ahash_cra_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int safexcel_hmac_sha1_init(struct ahash_request *areq)
|
|
|
|
{
|
2018-03-19 16:21:13 +08:00
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
2017-05-24 22:10:34 +08:00
|
|
|
|
|
|
|
safexcel_sha1_init(areq);
|
2018-03-19 16:21:13 +08:00
|
|
|
req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
|
2017-05-24 22:10:34 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_hmac_sha1_digest(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
int ret = safexcel_hmac_sha1_init(areq);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return safexcel_ahash_finup(areq);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct safexcel_ahash_result {
|
|
|
|
struct completion completion;
|
|
|
|
int error;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void safexcel_ahash_complete(struct crypto_async_request *req, int error)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_result *result = req->data;
|
|
|
|
|
|
|
|
if (error == -EINPROGRESS)
|
|
|
|
return;
|
|
|
|
|
|
|
|
result->error = error;
|
|
|
|
complete(&result->completion);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_hmac_init_pad(struct ahash_request *areq,
|
|
|
|
unsigned int blocksize, const u8 *key,
|
|
|
|
unsigned int keylen, u8 *ipad, u8 *opad)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_result result;
|
|
|
|
struct scatterlist sg;
|
|
|
|
int ret, i;
|
|
|
|
u8 *keydup;
|
|
|
|
|
|
|
|
if (keylen <= blocksize) {
|
|
|
|
memcpy(ipad, key, keylen);
|
|
|
|
} else {
|
|
|
|
keydup = kmemdup(key, keylen, GFP_KERNEL);
|
|
|
|
if (!keydup)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ahash_request_set_callback(areq, CRYPTO_TFM_REQ_MAY_BACKLOG,
|
|
|
|
safexcel_ahash_complete, &result);
|
|
|
|
sg_init_one(&sg, keydup, keylen);
|
|
|
|
ahash_request_set_crypt(areq, &sg, ipad, keylen);
|
|
|
|
init_completion(&result.completion);
|
|
|
|
|
|
|
|
ret = crypto_ahash_digest(areq);
|
2018-02-26 21:45:12 +08:00
|
|
|
if (ret == -EINPROGRESS || ret == -EBUSY) {
|
2017-05-24 22:10:34 +08:00
|
|
|
wait_for_completion_interruptible(&result.completion);
|
|
|
|
ret = result.error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Avoid leaking */
|
|
|
|
memzero_explicit(keydup, keylen);
|
|
|
|
kfree(keydup);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(areq));
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(ipad + keylen, 0, blocksize - keylen);
|
|
|
|
memcpy(opad, ipad, blocksize);
|
|
|
|
|
|
|
|
for (i = 0; i < blocksize; i++) {
|
2017-06-15 15:56:17 +08:00
|
|
|
ipad[i] ^= HMAC_IPAD_VALUE;
|
|
|
|
opad[i] ^= HMAC_OPAD_VALUE;
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_hmac_init_iv(struct ahash_request *areq,
|
|
|
|
unsigned int blocksize, u8 *pad, void *state)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_result result;
|
|
|
|
struct safexcel_ahash_req *req;
|
|
|
|
struct scatterlist sg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ahash_request_set_callback(areq, CRYPTO_TFM_REQ_MAY_BACKLOG,
|
|
|
|
safexcel_ahash_complete, &result);
|
|
|
|
sg_init_one(&sg, pad, blocksize);
|
|
|
|
ahash_request_set_crypt(areq, &sg, pad, blocksize);
|
|
|
|
init_completion(&result.completion);
|
|
|
|
|
|
|
|
ret = crypto_ahash_init(areq);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
req = ahash_request_ctx(areq);
|
|
|
|
req->hmac = true;
|
|
|
|
req->last_req = true;
|
|
|
|
|
|
|
|
ret = crypto_ahash_update(areq);
|
2017-12-14 22:26:48 +08:00
|
|
|
if (ret && ret != -EINPROGRESS && ret != -EBUSY)
|
2017-05-24 22:10:34 +08:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
wait_for_completion_interruptible(&result.completion);
|
|
|
|
if (result.error)
|
|
|
|
return result.error;
|
|
|
|
|
|
|
|
return crypto_ahash_export(areq, state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_hmac_setkey(const char *alg, const u8 *key,
|
|
|
|
unsigned int keylen, void *istate, void *ostate)
|
|
|
|
{
|
|
|
|
struct ahash_request *areq;
|
|
|
|
struct crypto_ahash *tfm;
|
|
|
|
unsigned int blocksize;
|
|
|
|
u8 *ipad, *opad;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
tfm = crypto_alloc_ahash(alg, CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
CRYPTO_ALG_TYPE_AHASH_MASK);
|
|
|
|
if (IS_ERR(tfm))
|
|
|
|
return PTR_ERR(tfm);
|
|
|
|
|
|
|
|
areq = ahash_request_alloc(tfm, GFP_KERNEL);
|
|
|
|
if (!areq) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto free_ahash;
|
|
|
|
}
|
|
|
|
|
|
|
|
crypto_ahash_clear_flags(tfm, ~0);
|
|
|
|
blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
|
|
|
|
|
|
|
|
ipad = kzalloc(2 * blocksize, GFP_KERNEL);
|
|
|
|
if (!ipad) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto free_request;
|
|
|
|
}
|
|
|
|
|
|
|
|
opad = ipad + blocksize;
|
|
|
|
|
|
|
|
ret = safexcel_hmac_init_pad(areq, blocksize, key, keylen, ipad, opad);
|
|
|
|
if (ret)
|
|
|
|
goto free_ipad;
|
|
|
|
|
|
|
|
ret = safexcel_hmac_init_iv(areq, blocksize, ipad, istate);
|
|
|
|
if (ret)
|
|
|
|
goto free_ipad;
|
|
|
|
|
|
|
|
ret = safexcel_hmac_init_iv(areq, blocksize, opad, ostate);
|
|
|
|
|
|
|
|
free_ipad:
|
|
|
|
kfree(ipad);
|
|
|
|
free_request:
|
|
|
|
ahash_request_free(areq);
|
|
|
|
free_ahash:
|
|
|
|
crypto_free_ahash(tfm);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_hmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
|
2017-12-14 22:26:58 +08:00
|
|
|
struct safexcel_crypto_priv *priv = ctx->priv;
|
2017-05-24 22:10:34 +08:00
|
|
|
struct safexcel_ahash_export_state istate, ostate;
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
ret = safexcel_hmac_setkey("safexcel-sha1", key, keylen, &istate, &ostate);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-12-14 22:26:58 +08:00
|
|
|
if (priv->version == EIP197 && ctx->base.ctxr) {
|
2017-12-14 22:26:47 +08:00
|
|
|
for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
|
|
|
|
if (ctx->ipad[i] != le32_to_cpu(istate.state[i]) ||
|
|
|
|
ctx->opad[i] != le32_to_cpu(ostate.state[i])) {
|
|
|
|
ctx->base.needs_inv = true;
|
|
|
|
break;
|
|
|
|
}
|
2017-05-24 22:10:34 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-19 17:02:30 +08:00
|
|
|
memcpy(ctx->ipad, &istate.state, SHA1_DIGEST_SIZE);
|
|
|
|
memcpy(ctx->opad, &ostate.state, SHA1_DIGEST_SIZE);
|
|
|
|
|
2017-05-24 22:10:34 +08:00
|
|
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return 0;
|
|
|
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}
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|
|
|
|
|
|
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struct safexcel_alg_template safexcel_alg_hmac_sha1 = {
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.type = SAFEXCEL_ALG_TYPE_AHASH,
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|
.alg.ahash = {
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.init = safexcel_hmac_sha1_init,
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.update = safexcel_ahash_update,
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.final = safexcel_ahash_final,
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.finup = safexcel_ahash_finup,
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.digest = safexcel_hmac_sha1_digest,
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.setkey = safexcel_hmac_sha1_setkey,
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.export = safexcel_ahash_export,
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.import = safexcel_ahash_import,
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|
|
.halg = {
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.digestsize = SHA1_DIGEST_SIZE,
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|
|
.statesize = sizeof(struct safexcel_ahash_export_state),
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|
|
.base = {
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|
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.cra_name = "hmac(sha1)",
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.cra_driver_name = "safexcel-hmac-sha1",
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|
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.cra_priority = 300,
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|
|
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.cra_flags = CRYPTO_ALG_ASYNC |
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|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
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|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
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|
|
|
.cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
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|
|
|
.cra_init = safexcel_ahash_cra_init,
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|
|
.cra_exit = safexcel_ahash_cra_exit,
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|
|
|
.cra_module = THIS_MODULE,
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|
|
|
},
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int safexcel_sha256_init(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
memset(req, 0, sizeof(*req));
|
|
|
|
|
|
|
|
req->state[0] = SHA256_H0;
|
|
|
|
req->state[1] = SHA256_H1;
|
|
|
|
req->state[2] = SHA256_H2;
|
|
|
|
req->state[3] = SHA256_H3;
|
|
|
|
req->state[4] = SHA256_H4;
|
|
|
|
req->state[5] = SHA256_H5;
|
|
|
|
req->state[6] = SHA256_H6;
|
|
|
|
req->state[7] = SHA256_H7;
|
|
|
|
|
|
|
|
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA256;
|
2018-03-19 16:21:13 +08:00
|
|
|
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
|
2017-05-24 22:10:34 +08:00
|
|
|
req->state_sz = SHA256_DIGEST_SIZE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_sha256_digest(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
int ret = safexcel_sha256_init(areq);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return safexcel_ahash_finup(areq);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct safexcel_alg_template safexcel_alg_sha256 = {
|
|
|
|
.type = SAFEXCEL_ALG_TYPE_AHASH,
|
|
|
|
.alg.ahash = {
|
|
|
|
.init = safexcel_sha256_init,
|
|
|
|
.update = safexcel_ahash_update,
|
|
|
|
.final = safexcel_ahash_final,
|
|
|
|
.finup = safexcel_ahash_finup,
|
|
|
|
.digest = safexcel_sha256_digest,
|
|
|
|
.export = safexcel_ahash_export,
|
|
|
|
.import = safexcel_ahash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct safexcel_ahash_export_state),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "sha256",
|
|
|
|
.cra_driver_name = "safexcel-sha256",
|
|
|
|
.cra_priority = 300,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
|
|
|
|
.cra_init = safexcel_ahash_cra_init,
|
|
|
|
.cra_exit = safexcel_ahash_cra_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int safexcel_sha224_init(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
|
|
|
|
struct safexcel_ahash_req *req = ahash_request_ctx(areq);
|
|
|
|
|
|
|
|
memset(req, 0, sizeof(*req));
|
|
|
|
|
|
|
|
req->state[0] = SHA224_H0;
|
|
|
|
req->state[1] = SHA224_H1;
|
|
|
|
req->state[2] = SHA224_H2;
|
|
|
|
req->state[3] = SHA224_H3;
|
|
|
|
req->state[4] = SHA224_H4;
|
|
|
|
req->state[5] = SHA224_H5;
|
|
|
|
req->state[6] = SHA224_H6;
|
|
|
|
req->state[7] = SHA224_H7;
|
|
|
|
|
|
|
|
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA224;
|
2018-03-19 16:21:13 +08:00
|
|
|
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
|
2017-05-24 22:10:34 +08:00
|
|
|
req->state_sz = SHA256_DIGEST_SIZE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int safexcel_sha224_digest(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
int ret = safexcel_sha224_init(areq);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return safexcel_ahash_finup(areq);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct safexcel_alg_template safexcel_alg_sha224 = {
|
|
|
|
.type = SAFEXCEL_ALG_TYPE_AHASH,
|
|
|
|
.alg.ahash = {
|
|
|
|
.init = safexcel_sha224_init,
|
|
|
|
.update = safexcel_ahash_update,
|
|
|
|
.final = safexcel_ahash_final,
|
|
|
|
.finup = safexcel_ahash_finup,
|
|
|
|
.digest = safexcel_sha224_digest,
|
|
|
|
.export = safexcel_ahash_export,
|
|
|
|
.import = safexcel_ahash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct safexcel_ahash_export_state),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "sha224",
|
|
|
|
.cra_driver_name = "safexcel-sha224",
|
|
|
|
.cra_priority = 300,
|
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
|
|
|
|
.cra_init = safexcel_ahash_cra_init,
|
|
|
|
.cra_exit = safexcel_ahash_cra_exit,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
},
|
|
|
|
};
|