2012-06-14 01:01:28 +08:00
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/*
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* Device Tree Include file for Marvell Armada 370 family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada 370 SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada 370 family SoC";
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compatible = "marvell,armada370", "marvell,armada-370-xp";
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2012-09-20 04:53:01 +08:00
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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2012-06-14 01:01:28 +08:00
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x1d0>,
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<0xd0021870 0x58>;
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};
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soc {
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x100>;
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};
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2012-09-13 23:41:49 +08:00
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pinctrl {
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compatible = "marvell,mv88f6710-pinctrl";
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reg = <0xd0018000 0x38>;
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2012-09-20 04:53:01 +08:00
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};
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gpio0: gpio@d0018100 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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gpio1: gpio@d0018140 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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gpio2: gpio@d0018180 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018180 0x40>;
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ngpios = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <91>;
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2012-09-13 23:41:49 +08:00
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};
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2012-11-17 22:22:24 +08:00
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coreclk: mvebu-sar@d0018230 {
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compatible = "marvell,armada-370-core-clock";
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reg = <0xd0018230 0x08>;
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#clock-cells = <1>;
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};
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gateclk: clock-gating-control@d0018220 {
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compatible = "marvell,armada-370-gating-clock";
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reg = <0xd0018220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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2012-11-20 23:03:12 +08:00
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xor@d0060800 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060800 0x100
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0xd0060A00 0x100>;
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status = "okay";
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2012-11-17 22:22:24 +08:00
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2012-11-20 23:03:12 +08:00
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xor00 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@d0060900 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060900 0x100
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0xd0060b00 0x100>;
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status = "okay";
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xor10 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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2012-06-14 01:01:28 +08:00
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};
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};
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