2005-04-17 06:20:36 +08:00
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/*******************************************************************************
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2006-09-28 03:53:14 +08:00
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Intel PRO/10GbE Linux driver
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2008-07-09 06:53:09 +08:00
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Copyright(c) 1999 - 2008 Intel Corporation.
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2006-09-28 03:53:14 +08:00
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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2005-04-17 06:20:36 +08:00
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more details.
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2006-09-28 03:53:14 +08:00
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2005-04-17 06:20:36 +08:00
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You should have received a copy of the GNU General Public License along with
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2006-09-28 03:53:14 +08:00
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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2005-04-17 06:20:36 +08:00
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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2006-09-28 03:53:14 +08:00
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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2005-04-17 06:20:36 +08:00
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* glue for the OS independent part of ixgb
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* includes register access macros
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*/
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#ifndef _IXGB_OSDEP_H_
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#define _IXGB_OSDEP_H_
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#undef ASSERT
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2009-04-11 22:50:23 +08:00
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#define ASSERT(x) BUG_ON(!(x))
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2010-04-27 08:50:58 +08:00
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#define ENTER() pr_debug("%s\n", __func__);
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2005-04-17 06:20:36 +08:00
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#define IXGB_WRITE_REG(a, reg, value) ( \
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writel((value), ((a)->hw_addr + IXGB_##reg)))
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#define IXGB_READ_REG(a, reg) ( \
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readl((a)->hw_addr + IXGB_##reg))
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#define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
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#define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
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readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
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#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
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#define IXGB_MEMCPY memcpy
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#endif /* _IXGB_OSDEP_H_ */
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