2005-09-26 14:04:21 +08:00
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#
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# Makefile for the linux ppc-specific parts of the memory manager.
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#
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2009-06-10 04:48:51 +08:00
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subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
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2012-11-27 01:41:08 +08:00
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ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
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2005-10-11 17:40:20 +08:00
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2014-11-06 00:27:41 +08:00
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obj-y := fault.o mem.o pgtable.o mmap.o \
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2016-08-11 14:03:14 +08:00
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init_$(BITS).o pgtable_$(BITS).o
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2008-12-19 03:13:42 +08:00
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obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
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tlb_nohash_low.o
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2016-08-11 14:03:14 +08:00
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obj-$(CONFIG_PPC_BOOK3E) += tlb_low_$(BITS)e.o
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2009-06-03 05:17:45 +08:00
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hash64-$(CONFIG_PPC_NATIVE) := hash_native_64.o
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2016-04-29 21:25:44 +08:00
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obj-$(CONFIG_PPC_BOOK3E_64) += pgtable-book3e.o
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2016-04-29 21:26:29 +08:00
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obj-$(CONFIG_PPC_STD_MMU_64) += pgtable-hash64.o hash_utils_64.o slb_low.o slb.o $(hash64-y) mmu_context_book3s64.o pgtable-book3s64.o
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2016-04-29 21:26:05 +08:00
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obj-$(CONFIG_PPC_RADIX_MMU) += pgtable-radix.o tlb-radix.o
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2016-04-29 21:26:03 +08:00
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obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o hash_low_32.o mmu_context_hash32.o
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2016-08-11 14:03:14 +08:00
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obj-$(CONFIG_PPC_STD_MMU) += tlb_hash$(BITS).o
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2015-12-01 11:36:43 +08:00
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ifeq ($(CONFIG_PPC_STD_MMU_64),y)
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2015-12-01 11:36:49 +08:00
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obj-$(CONFIG_PPC_4K_PAGES) += hash64_4k.o
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2015-12-01 11:36:43 +08:00
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obj-$(CONFIG_PPC_64K_PAGES) += hash64_64k.o
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endif
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2011-09-29 18:55:12 +08:00
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obj-$(CONFIG_PPC_ICSWX) += icswx.o
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obj-$(CONFIG_PPC_ICSWX_PID) += icswx_pid.o
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2007-08-20 20:27:07 +08:00
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obj-$(CONFIG_40x) += 40x_mmu.o
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2005-09-26 14:04:21 +08:00
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obj-$(CONFIG_44x) += 44x_mmu.o
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powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-10 00:07:50 +08:00
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obj-$(CONFIG_PPC_8xx) += 8xx_mmu.o
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2009-10-17 07:48:40 +08:00
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obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
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2005-10-10 19:58:35 +08:00
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obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
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2015-02-23 23:14:31 +08:00
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obj-$(CONFIG_PPC_SPLPAR) += vphn.o
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2007-05-08 14:27:27 +08:00
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obj-$(CONFIG_PPC_MM_SLICES) += slice.o
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2009-10-27 03:24:31 +08:00
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obj-y += hugetlbpage.o
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2013-06-20 17:00:16 +08:00
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ifeq ($(CONFIG_HUGETLB_PAGE),y)
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2009-10-27 03:24:31 +08:00
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obj-$(CONFIG_PPC_STD_MMU_64) += hugetlbpage-hash64.o
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2016-04-29 21:26:25 +08:00
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obj-$(CONFIG_PPC_RADIX_MMU) += hugetlbpage-radix.o
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2011-06-28 17:54:48 +08:00
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obj-$(CONFIG_PPC_BOOK3E_MMU) += hugetlbpage-book3e.o
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2009-10-27 03:24:31 +08:00
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endif
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2013-06-20 17:00:21 +08:00
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obj-$(CONFIG_TRANSPARENT_HUGEPAGE) += hugepage-hash64.o
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[POWERPC] Provide a way to protect 4k subpages when using 64k pages
Using 64k pages on 64-bit PowerPC systems makes life difficult for
emulators that are trying to emulate an ISA, such as x86, which use a
smaller page size, since the emulator can no longer use the MMU and
the normal system calls for controlling page protections. Of course,
the emulator can emulate the MMU by checking and possibly remapping
the address for each memory access in software, but that is pretty
slow.
This provides a facility for such programs to control the access
permissions on individual 4k sub-pages of 64k pages. The idea is
that the emulator supplies an array of protection masks to apply to a
specified range of virtual addresses. These masks are applied at the
level where hardware PTEs are inserted into the hardware page table
based on the Linux PTEs, so the Linux PTEs are not affected. Note
that this new mechanism does not allow any access that would otherwise
be prohibited; it can only prohibit accesses that would otherwise be
allowed. This new facility is only available on 64-bit PowerPC and
only when the kernel is configured for 64k pages.
The masks are supplied using a new subpage_prot system call, which
takes a starting virtual address and length, and a pointer to an array
of protection masks in memory. The array has a 32-bit word per 64k
page to be protected; each 32-bit word consists of 16 2-bit fields,
for which 0 allows any access (that is otherwise allowed), 1 prevents
write accesses, and 2 or 3 prevent any access.
Implicit in this is that the regions of the address space that are
protected are switched to use 4k hardware pages rather than 64k
hardware pages (on machines with hardware 64k page support). In fact
the whole process is switched to use 4k hardware pages when the
subpage_prot system call is used, but this could be improved in future
to switch only the affected segments.
The subpage protection bits are stored in a 3 level tree akin to the
page table tree. The top level of this tree is stored in a structure
that is appended to the top level of the page table tree, i.e., the
pgd array. Since it will often only be 32-bit addresses (below 4GB)
that are protected, the pointers to the first four bottom level pages
are also stored in this structure (each bottom level page contains the
protection bits for 1GB of address space), so the protection bits for
addresses below 4GB can be accessed with one fewer loads than those
for higher addresses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-24 05:35:13 +08:00
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obj-$(CONFIG_PPC_SUBPAGE_PROT) += subpage-prot.o
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2009-05-27 11:36:10 +08:00
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obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
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2009-06-19 03:25:00 +08:00
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obj-$(CONFIG_HIGHMEM) += highmem.o
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2014-10-08 16:54:50 +08:00
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obj-$(CONFIG_PPC_COPRO_BASE) += copro_fault.o
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2015-06-05 14:35:24 +08:00
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obj-$(CONFIG_SPAPR_TCE_IOMMU) += mmu_context_iommu.o
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2016-05-27 13:49:00 +08:00
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obj-$(CONFIG_PPC_PTDUMP) += dump_linuxpagetables.o \
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dump_hashpagetable.o
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