2011-11-21 05:32:10 +08:00
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/*
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* This file is part of wl1271
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*
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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2011-11-22 00:55:51 +08:00
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#include <linux/err.h>
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2012-04-11 16:03:14 +08:00
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#include <linux/wl12xx.h>
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2011-11-21 05:32:10 +08:00
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#include "../wlcore/wlcore.h"
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2011-11-22 00:55:51 +08:00
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#include "../wlcore/debug.h"
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2012-04-11 15:54:52 +08:00
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#include "../wlcore/io.h"
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2012-04-11 16:03:14 +08:00
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#include "../wlcore/acx.h"
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2011-12-12 17:41:44 +08:00
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#include "../wlcore/tx.h"
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2011-12-12 18:11:43 +08:00
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#include "../wlcore/rx.h"
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2012-04-11 16:03:14 +08:00
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#include "../wlcore/boot.h"
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2011-11-22 00:55:51 +08:00
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2011-12-05 22:51:10 +08:00
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#include "wl12xx.h"
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2011-11-29 19:38:37 +08:00
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#include "reg.h"
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2011-12-02 06:47:45 +08:00
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#include "cmd.h"
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#include "acx.h"
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2012-05-10 17:14:08 +08:00
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#include "debugfs.h"
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2011-11-22 02:37:14 +08:00
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2012-05-10 17:13:43 +08:00
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static char *fref_param;
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static char *tcxo_param;
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2011-12-05 22:12:54 +08:00
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static struct wlcore_conf wl12xx_conf = {
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.sg = {
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.params = {
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[CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
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[CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
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[CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
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[CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
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[CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
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[CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
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[CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
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[CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
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[CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
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[CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
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[CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
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[CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
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[CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
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[CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
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[CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
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[CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
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[CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
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[CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
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[CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
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[CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
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[CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
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[CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
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[CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
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[CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
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[CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
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[CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
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/* active scan params */
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[CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
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[CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
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[CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
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/* passive scan params */
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[CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
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[CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
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[CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
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/* passive scan in dual antenna params */
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[CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
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[CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
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[CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
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/* general params */
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[CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
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[CONF_SG_ANTENNA_CONFIGURATION] = 0,
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[CONF_SG_BEACON_MISS_PERCENT] = 60,
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[CONF_SG_DHCP_TIME] = 5000,
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[CONF_SG_RXT] = 1200,
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[CONF_SG_TXT] = 1000,
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[CONF_SG_ADAPTIVE_RXT_TXT] = 1,
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[CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
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[CONF_SG_HV3_MAX_SERVED] = 6,
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[CONF_SG_PS_POLL_TIMEOUT] = 10,
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[CONF_SG_UPSD_TIMEOUT] = 10,
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[CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
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[CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
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[CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
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/* AP params */
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[CONF_AP_BEACON_MISS_TX] = 3,
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[CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
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[CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
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[CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
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[CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
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[CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
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/* CTS Diluting params */
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[CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
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[CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
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},
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.state = CONF_SG_PROTECTIVE,
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},
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.rx = {
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.rx_msdu_life_time = 512000,
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.packet_detection_threshold = 0,
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.ps_poll_timeout = 15,
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.upsd_timeout = 15,
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.rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
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.rx_cca_threshold = 0,
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.irq_blk_threshold = 0xFFFF,
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.irq_pkt_threshold = 0,
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.irq_timeout = 600,
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.queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
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},
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.tx = {
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.tx_energy_detection = 0,
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.sta_rc_conf = {
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.enabled_rates = 0,
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.short_retry_limit = 10,
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.long_retry_limit = 10,
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.aflags = 0,
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},
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.ac_conf_count = 4,
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.ac_conf = {
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[CONF_TX_AC_BE] = {
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.ac = CONF_TX_AC_BE,
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.cw_min = 15,
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.cw_max = 63,
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.aifsn = 3,
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.tx_op_limit = 0,
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},
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[CONF_TX_AC_BK] = {
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.ac = CONF_TX_AC_BK,
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.cw_min = 15,
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.cw_max = 63,
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.aifsn = 7,
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.tx_op_limit = 0,
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},
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[CONF_TX_AC_VI] = {
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.ac = CONF_TX_AC_VI,
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.cw_min = 15,
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.cw_max = 63,
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.aifsn = CONF_TX_AIFS_PIFS,
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.tx_op_limit = 3008,
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},
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[CONF_TX_AC_VO] = {
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.ac = CONF_TX_AC_VO,
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.cw_min = 15,
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.cw_max = 63,
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.aifsn = CONF_TX_AIFS_PIFS,
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.tx_op_limit = 1504,
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},
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},
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.max_tx_retries = 100,
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.ap_aging_period = 300,
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.tid_conf_count = 4,
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.tid_conf = {
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[CONF_TX_AC_BE] = {
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.queue_id = CONF_TX_AC_BE,
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.channel_type = CONF_CHANNEL_TYPE_EDCF,
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.tsid = CONF_TX_AC_BE,
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.ps_scheme = CONF_PS_SCHEME_LEGACY,
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.ack_policy = CONF_ACK_POLICY_LEGACY,
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.apsd_conf = {0, 0},
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},
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[CONF_TX_AC_BK] = {
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.queue_id = CONF_TX_AC_BK,
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.channel_type = CONF_CHANNEL_TYPE_EDCF,
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.tsid = CONF_TX_AC_BK,
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.ps_scheme = CONF_PS_SCHEME_LEGACY,
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.ack_policy = CONF_ACK_POLICY_LEGACY,
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.apsd_conf = {0, 0},
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},
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[CONF_TX_AC_VI] = {
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.queue_id = CONF_TX_AC_VI,
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.channel_type = CONF_CHANNEL_TYPE_EDCF,
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.tsid = CONF_TX_AC_VI,
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.ps_scheme = CONF_PS_SCHEME_LEGACY,
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.ack_policy = CONF_ACK_POLICY_LEGACY,
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.apsd_conf = {0, 0},
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},
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[CONF_TX_AC_VO] = {
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.queue_id = CONF_TX_AC_VO,
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.channel_type = CONF_CHANNEL_TYPE_EDCF,
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.tsid = CONF_TX_AC_VO,
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.ps_scheme = CONF_PS_SCHEME_LEGACY,
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.ack_policy = CONF_ACK_POLICY_LEGACY,
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.apsd_conf = {0, 0},
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},
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},
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.frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
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.tx_compl_timeout = 700,
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.tx_compl_threshold = 4,
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.basic_rate = CONF_HW_BIT_RATE_1MBPS,
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.basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
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.tmpl_short_retry_limit = 10,
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.tmpl_long_retry_limit = 10,
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.tx_watchdog_timeout = 5000,
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},
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.conn = {
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.wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
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.listen_interval = 1,
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.suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
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.suspend_listen_interval = 3,
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.bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
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2012-05-15 21:35:20 +08:00
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.bcn_filt_ie_count = 3,
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2011-12-05 22:12:54 +08:00
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.bcn_filt_ie = {
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[0] = {
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.ie = WLAN_EID_CHANNEL_SWITCH,
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.rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
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},
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[1] = {
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.ie = WLAN_EID_HT_OPERATION,
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.rule = CONF_BCN_RULE_PASS_ON_CHANGE,
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},
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2012-05-15 21:35:20 +08:00
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[2] = {
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.ie = WLAN_EID_ERP_INFO,
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.rule = CONF_BCN_RULE_PASS_ON_CHANGE,
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},
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2011-12-05 22:12:54 +08:00
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},
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2012-05-15 22:08:57 +08:00
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.synch_fail_thold = 12,
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.bss_lose_timeout = 400,
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2011-12-05 22:12:54 +08:00
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.beacon_rx_timeout = 10000,
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.broadcast_timeout = 20000,
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.rx_broadcast_in_ps = 1,
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.ps_poll_threshold = 10,
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.bet_enable = CONF_BET_MODE_ENABLE,
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.bet_max_consecutive = 50,
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.psm_entry_retries = 8,
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.psm_exit_retries = 16,
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.psm_entry_nullfunc_retries = 3,
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2012-07-03 16:34:43 +08:00
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.dynamic_ps_timeout = 1500,
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2011-12-05 22:12:54 +08:00
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.forced_ps = false,
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.keep_alive_interval = 55000,
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.max_listen_interval = 20,
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2012-06-10 22:09:22 +08:00
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.sta_sleep_auth = WL1271_PSM_ILLEGAL,
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2011-12-05 22:12:54 +08:00
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},
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.itrim = {
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.enable = false,
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.timeout = 50000,
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},
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.pm_config = {
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.host_clk_settling_time = 5000,
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2012-06-08 04:39:24 +08:00
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.host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
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2011-12-05 22:12:54 +08:00
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},
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.roam_trigger = {
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.trigger_pacing = 1,
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.avg_weight_rssi_beacon = 20,
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.avg_weight_rssi_data = 10,
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.avg_weight_snr_beacon = 20,
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.avg_weight_snr_data = 10,
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},
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.scan = {
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.min_dwell_time_active = 7500,
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.max_dwell_time_active = 30000,
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.min_dwell_time_passive = 100000,
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.max_dwell_time_passive = 100000,
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.num_probe_reqs = 2,
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.split_scan_timeout = 50000,
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},
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.sched_scan = {
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/*
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* Values are in TU/1000 but since sched scan FW command
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* params are in TUs rounding up may occur.
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*/
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.base_dwell_time = 7500,
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.max_dwell_time_delta = 22500,
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/* based on 250bits per probe @1Mbps */
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.dwell_time_delta_per_probe = 2000,
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/* based on 250bits per probe @6Mbps (plus a bit more) */
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.dwell_time_delta_per_probe_5 = 350,
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.dwell_time_passive = 100000,
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.dwell_time_dfs = 150000,
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.num_probe_reqs = 2,
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.rssi_threshold = -90,
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.snr_threshold = 0,
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},
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.ht = {
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.rx_ba_win_size = 8,
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.tx_ba_win_size = 64,
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.inactivity_timeout = 10000,
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.tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
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},
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2011-12-06 01:52:22 +08:00
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/*
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* Memory config for wl127x chips is given in the
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* wl12xx_default_priv_conf struct. The below configuration is
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* for wl128x chips.
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*/
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.mem = {
|
2011-12-05 22:12:54 +08:00
|
|
|
.num_stations = 1,
|
|
|
|
.ssid_profiles = 1,
|
|
|
|
.rx_block_num = 40,
|
|
|
|
.tx_min_block_num = 40,
|
|
|
|
.dynamic_memory = 1,
|
|
|
|
.min_req_tx_blocks = 45,
|
|
|
|
.min_req_rx_blocks = 22,
|
|
|
|
.tx_min = 27,
|
|
|
|
},
|
|
|
|
.fm_coex = {
|
|
|
|
.enable = true,
|
|
|
|
.swallow_period = 5,
|
|
|
|
.n_divider_fref_set_1 = 0xff, /* default */
|
|
|
|
.n_divider_fref_set_2 = 12,
|
2012-05-10 22:08:33 +08:00
|
|
|
.m_divider_fref_set_1 = 0xffff,
|
|
|
|
.m_divider_fref_set_2 = 148, /* default */
|
2011-12-05 22:12:54 +08:00
|
|
|
.coex_pll_stabilization_time = 0xffffffff, /* default */
|
|
|
|
.ldo_stabilization_time = 0xffff, /* default */
|
|
|
|
.fm_disturbed_band_margin = 0xff, /* default */
|
|
|
|
.swallow_clk_diff = 0xff, /* default */
|
|
|
|
},
|
|
|
|
.rx_streaming = {
|
|
|
|
.duration = 150,
|
|
|
|
.queues = 0x1,
|
|
|
|
.interval = 20,
|
|
|
|
.always = 0,
|
|
|
|
},
|
|
|
|
.fwlog = {
|
|
|
|
.mode = WL12XX_FWLOG_ON_DEMAND,
|
|
|
|
.mem_blocks = 2,
|
|
|
|
.severity = 0,
|
|
|
|
.timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
|
|
|
|
.output = WL12XX_FWLOG_OUTPUT_HOST,
|
|
|
|
.threshold = 0,
|
|
|
|
},
|
|
|
|
.rate = {
|
|
|
|
.rate_retry_score = 32000,
|
|
|
|
.per_add = 8192,
|
|
|
|
.per_th1 = 2048,
|
|
|
|
.per_th2 = 4096,
|
|
|
|
.max_per = 8100,
|
|
|
|
.inverse_curiosity_factor = 5,
|
|
|
|
.tx_fail_low_th = 4,
|
|
|
|
.tx_fail_high_th = 10,
|
|
|
|
.per_alpha_shift = 4,
|
|
|
|
.per_add_shift = 13,
|
|
|
|
.per_beta1_shift = 10,
|
|
|
|
.per_beta2_shift = 8,
|
|
|
|
.rate_check_up = 2,
|
|
|
|
.rate_check_down = 12,
|
|
|
|
.rate_retry_policy = {
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
0x00, 0x00, 0x00,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.hangover = {
|
|
|
|
.recover_time = 0,
|
|
|
|
.hangover_period = 20,
|
|
|
|
.dynamic_mode = 1,
|
|
|
|
.early_termination_mode = 1,
|
|
|
|
.max_period = 20,
|
|
|
|
.min_period = 1,
|
|
|
|
.increase_delta = 1,
|
|
|
|
.decrease_delta = 2,
|
|
|
|
.quiet_time = 4,
|
|
|
|
.increase_time = 1,
|
|
|
|
.window_size = 16,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-12-06 01:52:22 +08:00
|
|
|
static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
|
|
|
|
.rf = {
|
|
|
|
.tx_per_channel_power_compensation_2 = {
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
},
|
|
|
|
.tx_per_channel_power_compensation_5 = {
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.mem_wl127x = {
|
|
|
|
.num_stations = 1,
|
|
|
|
.ssid_profiles = 1,
|
|
|
|
.rx_block_num = 70,
|
|
|
|
.tx_min_block_num = 40,
|
|
|
|
.dynamic_memory = 1,
|
|
|
|
.min_req_tx_blocks = 100,
|
|
|
|
.min_req_rx_blocks = 22,
|
|
|
|
.tx_min = 27,
|
|
|
|
},
|
|
|
|
|
|
|
|
};
|
2011-12-05 22:12:54 +08:00
|
|
|
|
2011-12-08 05:38:47 +08:00
|
|
|
#define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT 1
|
|
|
|
#define WL12XX_TX_HW_BLOCK_GEM_SPARE 2
|
2011-12-12 17:41:44 +08:00
|
|
|
#define WL12XX_TX_HW_BLOCK_SIZE 252
|
2011-12-08 05:38:47 +08:00
|
|
|
|
2011-12-08 06:43:48 +08:00
|
|
|
static const u8 wl12xx_rate_to_idx_2ghz[] = {
|
|
|
|
/* MCS rates are used only with 11n */
|
|
|
|
7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
|
|
|
|
7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
|
|
|
|
6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
|
|
|
|
5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
|
|
|
|
4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
|
|
|
|
3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
|
|
|
|
2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
|
|
|
|
1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
|
|
|
|
0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
|
|
|
|
|
|
|
|
11, /* WL12XX_CONF_HW_RXTX_RATE_54 */
|
|
|
|
10, /* WL12XX_CONF_HW_RXTX_RATE_48 */
|
|
|
|
9, /* WL12XX_CONF_HW_RXTX_RATE_36 */
|
|
|
|
8, /* WL12XX_CONF_HW_RXTX_RATE_24 */
|
|
|
|
|
|
|
|
/* TI-specific rate */
|
|
|
|
CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
|
|
|
|
|
|
|
|
7, /* WL12XX_CONF_HW_RXTX_RATE_18 */
|
|
|
|
6, /* WL12XX_CONF_HW_RXTX_RATE_12 */
|
|
|
|
3, /* WL12XX_CONF_HW_RXTX_RATE_11 */
|
|
|
|
5, /* WL12XX_CONF_HW_RXTX_RATE_9 */
|
|
|
|
4, /* WL12XX_CONF_HW_RXTX_RATE_6 */
|
|
|
|
2, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
|
|
|
|
1, /* WL12XX_CONF_HW_RXTX_RATE_2 */
|
|
|
|
0 /* WL12XX_CONF_HW_RXTX_RATE_1 */
|
|
|
|
};
|
|
|
|
|
|
|
|
static const u8 wl12xx_rate_to_idx_5ghz[] = {
|
|
|
|
/* MCS rates are used only with 11n */
|
|
|
|
7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
|
|
|
|
7, /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
|
|
|
|
6, /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
|
|
|
|
5, /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
|
|
|
|
4, /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
|
|
|
|
3, /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
|
|
|
|
2, /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
|
|
|
|
1, /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
|
|
|
|
0, /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
|
|
|
|
|
|
|
|
7, /* WL12XX_CONF_HW_RXTX_RATE_54 */
|
|
|
|
6, /* WL12XX_CONF_HW_RXTX_RATE_48 */
|
|
|
|
5, /* WL12XX_CONF_HW_RXTX_RATE_36 */
|
|
|
|
4, /* WL12XX_CONF_HW_RXTX_RATE_24 */
|
|
|
|
|
|
|
|
/* TI-specific rate */
|
|
|
|
CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22 */
|
|
|
|
|
|
|
|
3, /* WL12XX_CONF_HW_RXTX_RATE_18 */
|
|
|
|
2, /* WL12XX_CONF_HW_RXTX_RATE_12 */
|
|
|
|
CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11 */
|
|
|
|
1, /* WL12XX_CONF_HW_RXTX_RATE_9 */
|
|
|
|
0, /* WL12XX_CONF_HW_RXTX_RATE_6 */
|
|
|
|
CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5 */
|
|
|
|
CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2 */
|
|
|
|
CONF_HW_RXTX_RATE_UNSUPPORTED /* WL12XX_CONF_HW_RXTX_RATE_1 */
|
|
|
|
};
|
|
|
|
|
|
|
|
static const u8 *wl12xx_band_rate_to_idx[] = {
|
|
|
|
[IEEE80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
|
|
|
|
[IEEE80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
|
|
|
|
};
|
|
|
|
|
|
|
|
enum wl12xx_hw_rates {
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS7,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS6,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS5,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS4,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS3,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS2,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS1,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MCS0,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_54,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_48,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_36,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_24,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_22,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_18,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_12,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_11,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_9,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_6,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_5_5,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_2,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_1,
|
|
|
|
WL12XX_CONF_HW_RXTX_RATE_MAX,
|
|
|
|
};
|
2011-12-08 05:38:47 +08:00
|
|
|
|
2011-11-22 02:37:14 +08:00
|
|
|
static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
|
|
|
|
[PART_DOWN] = {
|
|
|
|
.mem = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x000177c0
|
|
|
|
},
|
|
|
|
.reg = {
|
|
|
|
.start = REGISTERS_BASE,
|
|
|
|
.size = 0x00008800
|
|
|
|
},
|
|
|
|
.mem2 = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x00000000
|
|
|
|
},
|
|
|
|
.mem3 = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x00000000
|
|
|
|
},
|
|
|
|
},
|
|
|
|
|
2011-11-29 19:38:37 +08:00
|
|
|
[PART_BOOT] = { /* in wl12xx we can use a mix of work and down
|
|
|
|
* partition here */
|
|
|
|
.mem = {
|
|
|
|
.start = 0x00040000,
|
|
|
|
.size = 0x00014fc0
|
|
|
|
},
|
|
|
|
.reg = {
|
|
|
|
.start = REGISTERS_BASE,
|
|
|
|
.size = 0x00008800
|
|
|
|
},
|
|
|
|
.mem2 = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x00000000
|
|
|
|
},
|
|
|
|
.mem3 = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x00000000
|
|
|
|
},
|
|
|
|
},
|
|
|
|
|
2011-11-22 02:37:14 +08:00
|
|
|
[PART_WORK] = {
|
|
|
|
.mem = {
|
|
|
|
.start = 0x00040000,
|
|
|
|
.size = 0x00014fc0
|
|
|
|
},
|
|
|
|
.reg = {
|
|
|
|
.start = REGISTERS_BASE,
|
|
|
|
.size = 0x0000a000
|
|
|
|
},
|
|
|
|
.mem2 = {
|
|
|
|
.start = 0x003004f8,
|
|
|
|
.size = 0x00000004
|
|
|
|
},
|
|
|
|
.mem3 = {
|
|
|
|
.start = 0x00040404,
|
|
|
|
.size = 0x00000000
|
|
|
|
},
|
|
|
|
},
|
|
|
|
|
|
|
|
[PART_DRPW] = {
|
|
|
|
.mem = {
|
|
|
|
.start = 0x00040000,
|
|
|
|
.size = 0x00014fc0
|
|
|
|
},
|
|
|
|
.reg = {
|
|
|
|
.start = DRPW_BASE,
|
|
|
|
.size = 0x00006000
|
|
|
|
},
|
|
|
|
.mem2 = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x00000000
|
|
|
|
},
|
|
|
|
.mem3 = {
|
|
|
|
.start = 0x00000000,
|
|
|
|
.size = 0x00000000
|
|
|
|
}
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-11-29 19:38:37 +08:00
|
|
|
static const int wl12xx_rtable[REG_TABLE_LEN] = {
|
|
|
|
[REG_ECPU_CONTROL] = WL12XX_REG_ECPU_CONTROL,
|
|
|
|
[REG_INTERRUPT_NO_CLEAR] = WL12XX_REG_INTERRUPT_NO_CLEAR,
|
|
|
|
[REG_INTERRUPT_ACK] = WL12XX_REG_INTERRUPT_ACK,
|
|
|
|
[REG_COMMAND_MAILBOX_PTR] = WL12XX_REG_COMMAND_MAILBOX_PTR,
|
|
|
|
[REG_EVENT_MAILBOX_PTR] = WL12XX_REG_EVENT_MAILBOX_PTR,
|
|
|
|
[REG_INTERRUPT_TRIG] = WL12XX_REG_INTERRUPT_TRIG,
|
|
|
|
[REG_INTERRUPT_MASK] = WL12XX_REG_INTERRUPT_MASK,
|
|
|
|
[REG_PC_ON_RECOVERY] = WL12XX_SCR_PAD4,
|
|
|
|
[REG_CHIP_ID_B] = WL12XX_CHIP_ID_B,
|
|
|
|
[REG_CMD_MBOX_ADDRESS] = WL12XX_CMD_MBOX_ADDRESS,
|
|
|
|
|
|
|
|
/* data access memory addresses, used with partition translation */
|
|
|
|
[REG_SLV_MEM_DATA] = WL1271_SLV_MEM_DATA,
|
|
|
|
[REG_SLV_REG_DATA] = WL1271_SLV_REG_DATA,
|
|
|
|
|
|
|
|
/* raw data access memory addresses */
|
|
|
|
[REG_RAW_FW_STATUS_ADDR] = FW_STATUS_ADDR,
|
|
|
|
};
|
|
|
|
|
2011-11-29 22:27:31 +08:00
|
|
|
/* TODO: maybe move to a new header file? */
|
2012-06-27 20:21:10 +08:00
|
|
|
#define WL127X_FW_NAME_MULTI "ti-connectivity/wl127x-fw-5-mr.bin"
|
|
|
|
#define WL127X_FW_NAME_SINGLE "ti-connectivity/wl127x-fw-5-sr.bin"
|
|
|
|
#define WL127X_PLT_FW_NAME "ti-connectivity/wl127x-fw-5-plt.bin"
|
2011-11-29 22:27:31 +08:00
|
|
|
|
2012-06-27 20:21:10 +08:00
|
|
|
#define WL128X_FW_NAME_MULTI "ti-connectivity/wl128x-fw-5-mr.bin"
|
|
|
|
#define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-5-sr.bin"
|
|
|
|
#define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-5-plt.bin"
|
2011-11-29 22:27:31 +08:00
|
|
|
|
2012-06-18 18:21:55 +08:00
|
|
|
static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
|
2011-12-12 18:15:08 +08:00
|
|
|
{
|
2012-06-18 18:21:55 +08:00
|
|
|
int ret;
|
|
|
|
|
2011-12-12 18:15:08 +08:00
|
|
|
if (wl->chip.id != CHIP_ID_1283_PG20) {
|
|
|
|
struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
|
2012-05-10 17:13:45 +08:00
|
|
|
struct wl127x_rx_mem_pool_addr rx_mem_addr;
|
2011-12-12 18:15:08 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Choose the block we want to read
|
|
|
|
* For aggregated packets, only the first memory block
|
|
|
|
* should be retrieved. The FW takes care of the rest.
|
|
|
|
*/
|
|
|
|
u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
|
|
|
|
|
|
|
|
rx_mem_addr.addr = (mem_block << 8) +
|
|
|
|
le32_to_cpu(wl_mem_map->packet_memory_pool_start);
|
|
|
|
|
|
|
|
rx_mem_addr.addr_extra = rx_mem_addr.addr + 4;
|
|
|
|
|
2012-06-18 18:21:55 +08:00
|
|
|
ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr,
|
|
|
|
sizeof(rx_mem_addr), false);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2011-12-12 18:15:08 +08:00
|
|
|
}
|
2012-06-18 18:21:55 +08:00
|
|
|
|
|
|
|
return 0;
|
2011-12-12 18:15:08 +08:00
|
|
|
}
|
|
|
|
|
2011-11-29 22:27:31 +08:00
|
|
|
static int wl12xx_identify_chip(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
switch (wl->chip.id) {
|
|
|
|
case CHIP_ID_1271_PG10:
|
|
|
|
wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
|
|
|
|
wl->chip.id);
|
|
|
|
|
2012-05-18 12:46:36 +08:00
|
|
|
wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
|
2012-06-27 18:01:44 +08:00
|
|
|
WLCORE_QUIRK_DUAL_PROBE_TMPL |
|
2012-05-18 12:46:36 +08:00
|
|
|
WLCORE_QUIRK_TKIP_HEADER_SPACE;
|
2011-11-29 22:27:31 +08:00
|
|
|
wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
|
|
|
|
wl->mr_fw_name = WL127X_FW_NAME_MULTI;
|
2011-12-06 01:52:22 +08:00
|
|
|
memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
|
|
|
|
sizeof(wl->conf.mem));
|
2011-12-12 18:15:08 +08:00
|
|
|
|
|
|
|
/* read data preparation is only needed by wl127x */
|
|
|
|
wl->ops->prepare_read = wl127x_prepare_read;
|
|
|
|
|
2012-06-25 22:46:40 +08:00
|
|
|
wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
|
|
|
|
WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
|
|
|
|
WL127X_MINOR_VER);
|
2011-11-29 22:27:31 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case CHIP_ID_1271_PG20:
|
|
|
|
wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
|
|
|
|
wl->chip.id);
|
|
|
|
|
2012-05-18 12:46:36 +08:00
|
|
|
wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
|
2012-06-27 18:01:44 +08:00
|
|
|
WLCORE_QUIRK_DUAL_PROBE_TMPL |
|
2012-05-18 12:46:36 +08:00
|
|
|
WLCORE_QUIRK_TKIP_HEADER_SPACE;
|
2011-11-29 22:27:31 +08:00
|
|
|
wl->plt_fw_name = WL127X_PLT_FW_NAME;
|
|
|
|
wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
|
|
|
|
wl->mr_fw_name = WL127X_FW_NAME_MULTI;
|
2011-12-06 01:52:22 +08:00
|
|
|
memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
|
|
|
|
sizeof(wl->conf.mem));
|
2011-12-12 18:15:08 +08:00
|
|
|
|
|
|
|
/* read data preparation is only needed by wl127x */
|
|
|
|
wl->ops->prepare_read = wl127x_prepare_read;
|
|
|
|
|
2012-06-25 22:46:40 +08:00
|
|
|
wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER, WL127X_IFTYPE_VER,
|
|
|
|
WL127X_MAJOR_VER, WL127X_SUBTYPE_VER,
|
|
|
|
WL127X_MINOR_VER);
|
2011-11-29 22:27:31 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case CHIP_ID_1283_PG20:
|
|
|
|
wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
|
|
|
|
wl->chip.id);
|
|
|
|
wl->plt_fw_name = WL128X_PLT_FW_NAME;
|
|
|
|
wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
|
|
|
|
wl->mr_fw_name = WL128X_FW_NAME_MULTI;
|
2012-06-05 05:02:25 +08:00
|
|
|
|
|
|
|
/* wl128x requires TX blocksize alignment */
|
2012-05-18 12:46:36 +08:00
|
|
|
wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
|
2012-06-27 18:01:44 +08:00
|
|
|
WLCORE_QUIRK_DUAL_PROBE_TMPL |
|
2012-05-18 12:46:36 +08:00
|
|
|
WLCORE_QUIRK_TKIP_HEADER_SPACE;
|
2012-06-05 05:02:25 +08:00
|
|
|
|
2012-06-25 22:46:40 +08:00
|
|
|
wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER, WL128X_IFTYPE_VER,
|
|
|
|
WL128X_MAJOR_VER, WL128X_SUBTYPE_VER,
|
|
|
|
WL128X_MINOR_VER);
|
2011-11-29 22:27:31 +08:00
|
|
|
break;
|
|
|
|
case CHIP_ID_1283_PG10:
|
|
|
|
default:
|
|
|
|
wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-06-20 05:03:46 +08:00
|
|
|
static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
|
|
|
|
u16 val)
|
2012-04-11 16:03:14 +08:00
|
|
|
{
|
2012-06-20 05:48:23 +08:00
|
|
|
int ret;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
/* write address >> 1 + 0x30000 to OCP_POR_CTR */
|
|
|
|
addr = (addr >> 1) + 0x30000;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* write value to OCP_POR_WDATA */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* write 1 to OCP_CMD */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
2012-06-20 05:03:46 +08:00
|
|
|
static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
|
|
|
|
u16 *out)
|
2012-04-11 16:03:14 +08:00
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
int timeout = OCP_CMD_LOOP;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* write address >> 1 + 0x30000 to OCP_POR_CTR */
|
|
|
|
addr = (addr >> 1) + 0x30000;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* write 2 to OCP_CMD */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* poll for data ready */
|
|
|
|
do {
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
} while (!(val & OCP_READY_MASK) && --timeout);
|
|
|
|
|
|
|
|
if (!timeout) {
|
|
|
|
wl1271_warning("Top register access timed out.");
|
2012-06-18 20:50:21 +08:00
|
|
|
return -ETIMEDOUT;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* check data status and return if OK */
|
2012-06-18 20:50:21 +08:00
|
|
|
if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
|
2012-04-11 16:03:14 +08:00
|
|
|
wl1271_warning("Top register access returned error.");
|
2012-06-18 20:50:21 +08:00
|
|
|
return -EIO;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
2012-06-18 20:50:21 +08:00
|
|
|
|
|
|
|
if (out)
|
|
|
|
*out = val & 0xffff;
|
|
|
|
|
|
|
|
return 0;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
u16 spare_reg;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Mask bits [2] & [8:4] in the sys_clk_cfg register */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
if (spare_reg == 0xFFFF)
|
|
|
|
return -EFAULT;
|
|
|
|
spare_reg |= (BIT(3) | BIT(5) | BIT(6));
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
|
|
|
|
WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Delay execution for 15msec, to let the HW settle */
|
|
|
|
mdelay(15);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
u16 tcxo_detection;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
|
|
|
|
if (ret < 0)
|
|
|
|
return false;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
if (tcxo_detection & TCXO_DET_FAILED)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool wl128x_is_fref_valid(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
u16 fref_detection;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
|
|
|
|
if (ret < 0)
|
|
|
|
return false;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
if (fref_detection & FREF_CLK_DETECT_FAIL)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
|
|
|
|
{
|
2012-06-20 05:48:23 +08:00
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
|
|
|
|
MCS_PLL_CONFIG_REG_VAL);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
|
|
|
|
{
|
|
|
|
u16 spare_reg;
|
|
|
|
u16 pll_config;
|
|
|
|
u8 input_freq;
|
2012-05-10 17:13:43 +08:00
|
|
|
struct wl12xx_priv *priv = wl->priv;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Mask bits [3:1] in the sys_clk_cfg register */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
if (spare_reg == 0xFFFF)
|
|
|
|
return -EFAULT;
|
|
|
|
spare_reg |= BIT(2);
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Handle special cases of the TCXO clock */
|
2012-05-10 17:13:43 +08:00
|
|
|
if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
|
|
|
|
priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
|
2012-04-11 16:03:14 +08:00
|
|
|
return wl128x_manually_configure_mcs_pll(wl);
|
|
|
|
|
|
|
|
/* Set the input frequency according to the selected clock source */
|
|
|
|
input_freq = (clk & 1) + 1;
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
if (pll_config == 0xFFFF)
|
|
|
|
return -EFAULT;
|
|
|
|
pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
|
|
|
|
pll_config |= MCS_PLL_ENABLE_HP;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* WL128x has two clocks input - TCXO and FREF.
|
|
|
|
* TCXO is the main clock of the device, while FREF is used to sync
|
|
|
|
* between the GPS and the cellular modem.
|
|
|
|
* In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
|
|
|
|
* as the WLAN/BT main clock.
|
|
|
|
*/
|
|
|
|
static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
|
|
|
|
{
|
2012-05-10 17:13:43 +08:00
|
|
|
struct wl12xx_priv *priv = wl->priv;
|
2012-04-11 16:03:14 +08:00
|
|
|
u16 sys_clk_cfg;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* For XTAL-only modes, FREF will be used after switching from TCXO */
|
2012-05-10 17:13:43 +08:00
|
|
|
if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
|
|
|
|
priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
|
2012-04-11 16:03:14 +08:00
|
|
|
if (!wl128x_switch_tcxo_to_fref(wl))
|
|
|
|
return -EINVAL;
|
|
|
|
goto fref_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Query the HW, to determine which clock source we should use */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
if (sys_clk_cfg == 0xFFFF)
|
|
|
|
return -EINVAL;
|
|
|
|
if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
|
|
|
|
goto fref_clk;
|
|
|
|
|
|
|
|
/* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
|
2012-05-10 17:13:43 +08:00
|
|
|
if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
|
|
|
|
priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
|
2012-04-11 16:03:14 +08:00
|
|
|
if (!wl128x_switch_tcxo_to_fref(wl))
|
|
|
|
return -EINVAL;
|
|
|
|
goto fref_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TCXO clock is selected */
|
|
|
|
if (!wl128x_is_tcxo_valid(wl))
|
|
|
|
return -EINVAL;
|
2012-05-10 17:13:43 +08:00
|
|
|
*selected_clock = priv->tcxo_clock;
|
2012-04-11 16:03:14 +08:00
|
|
|
goto config_mcs_pll;
|
|
|
|
|
|
|
|
fref_clk:
|
|
|
|
/* FREF clock is selected */
|
|
|
|
if (!wl128x_is_fref_valid(wl))
|
|
|
|
return -EINVAL;
|
2012-05-10 17:13:43 +08:00
|
|
|
*selected_clock = priv->ref_clock;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
config_mcs_pll:
|
|
|
|
return wl128x_configure_mcs_pll(wl, *selected_clock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int wl127x_boot_clk(struct wl1271 *wl)
|
|
|
|
{
|
2012-05-10 17:13:43 +08:00
|
|
|
struct wl12xx_priv *priv = wl->priv;
|
2012-04-11 16:03:14 +08:00
|
|
|
u32 pause;
|
|
|
|
u32 clk;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
|
|
|
|
wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
|
|
|
|
|
2012-05-10 17:13:43 +08:00
|
|
|
if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
|
|
|
|
priv->ref_clock == CONF_REF_CLK_38_4_E ||
|
|
|
|
priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
|
2012-04-11 16:03:14 +08:00
|
|
|
/* ref clk: 19.2/38.4/38.4-XTAL */
|
|
|
|
clk = 0x3;
|
2012-05-10 17:13:43 +08:00
|
|
|
else if (priv->ref_clock == CONF_REF_CLK_26_E ||
|
2012-06-02 00:19:01 +08:00
|
|
|
priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
|
2012-05-10 17:13:43 +08:00
|
|
|
priv->ref_clock == CONF_REF_CLK_52_E)
|
2012-04-11 16:03:14 +08:00
|
|
|
/* ref clk: 26/52 */
|
|
|
|
clk = 0x5;
|
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
|
2012-05-10 17:13:43 +08:00
|
|
|
if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
|
2012-04-11 16:03:14 +08:00
|
|
|
u16 val;
|
|
|
|
/* Set clock type (open drain) */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
val &= FREF_CLK_TYPE_BITS;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Set clock pull mode (no pull) */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
val |= NO_PULL;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
} else {
|
|
|
|
u16 val;
|
|
|
|
/* Set clock polarity */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
val &= FREF_CLK_POLARITY_BITS;
|
|
|
|
val |= CLK_REQ_OUTN_SEL;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
|
|
|
|
|
|
|
|
pause &= ~(WU_COUNTER_PAUSE_VAL);
|
|
|
|
pause |= WU_COUNTER_PAUSE_VAL;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
out:
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int wl1271_boot_soft_reset(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
unsigned long timeout;
|
|
|
|
u32 boot_data;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret = 0;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* perform soft reset */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* SOFT_RESET is self clearing */
|
|
|
|
timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
|
|
|
|
while (1) {
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
|
|
|
|
if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
|
|
/* 1.2 check pWhalBus->uSelfClearTime if the
|
|
|
|
* timeout was reached */
|
|
|
|
wl1271_error("soft reset timeout");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
udelay(SOFT_RESET_STALL_TIME);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* disable Rx/Tx */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* disable auto calibration on start*/
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
out:
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int wl12xx_pre_boot(struct wl1271 *wl)
|
|
|
|
{
|
2012-05-10 17:13:43 +08:00
|
|
|
struct wl12xx_priv *priv = wl->priv;
|
2012-04-11 16:03:14 +08:00
|
|
|
int ret = 0;
|
|
|
|
u32 clk;
|
|
|
|
int selected_clock = -1;
|
|
|
|
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20) {
|
|
|
|
ret = wl128x_boot_clk(wl, &selected_clock);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
} else {
|
|
|
|
ret = wl127x_boot_clk(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Continue the ELP wake up sequence */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-04-11 16:03:14 +08:00
|
|
|
udelay(500);
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Read-modify-write DRPW_SCRATCH_START register (see next state)
|
|
|
|
to be used by DRPw FW. The RTRIM value will be added by the FW
|
|
|
|
before taking DRPw out of reset */
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
|
|
|
|
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20)
|
|
|
|
clk |= ((selected_clock & 0x3) << 1) << 4;
|
|
|
|
else
|
2012-05-10 17:13:43 +08:00
|
|
|
clk |= (priv->ref_clock << 1) << 4;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* Disable interrupts */
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
ret = wl1271_boot_soft_reset(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
static int wl12xx_pre_upload(struct wl1271 *wl)
|
2012-04-11 16:03:14 +08:00
|
|
|
{
|
2012-06-18 20:50:21 +08:00
|
|
|
u32 tmp;
|
|
|
|
u16 polarity;
|
|
|
|
int ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* write firmware's last address (ie. it's length) to
|
|
|
|
* ACX_EEPROMLESS_IND_REG */
|
|
|
|
wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
|
|
|
|
|
|
|
|
/* 6. read the EEPROM parameters */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
|
|
|
|
* to upload_fw) */
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20) {
|
|
|
|
ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
}
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-05-08 19:02:12 +08:00
|
|
|
/* polarity must be set before the firmware is loaded */
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
/* We use HIGH polarity, so unset the LOW bit */
|
|
|
|
polarity &= ~POLARITY_LOW;
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
out:
|
|
|
|
return ret;
|
2012-05-08 19:02:12 +08:00
|
|
|
}
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
static int wl12xx_enable_interrupts(struct wl1271 *wl)
|
2012-05-08 19:02:12 +08:00
|
|
|
{
|
2012-06-20 05:48:23 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
|
|
|
|
WL12XX_ACX_ALL_EVENTS_VECTOR);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
wlcore_enable_interrupts(wl);
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
|
|
|
|
WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
|
2012-04-11 16:03:14 +08:00
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
out:
|
|
|
|
return ret;
|
2012-04-11 16:03:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int wl12xx_boot(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = wl12xx_pre_boot(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wlcore_boot_upload_nvs(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_pre_upload(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
ret = wlcore_boot_upload_firmware(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wlcore_boot_run_firmware(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wl12xx_enable_interrupts(wl);
|
2012-04-11 16:03:14 +08:00
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-06-18 18:21:55 +08:00
|
|
|
static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
|
2011-12-13 18:27:22 +08:00
|
|
|
void *buf, size_t len)
|
2012-04-11 15:15:46 +08:00
|
|
|
{
|
2012-06-18 18:21:55 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
|
2012-06-18 18:21:55 +08:00
|
|
|
|
|
|
|
return ret;
|
2012-04-11 15:15:46 +08:00
|
|
|
}
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
static int wl12xx_ack_event(struct wl1271 *wl)
|
2012-04-11 15:15:46 +08:00
|
|
|
{
|
2012-06-20 05:48:23 +08:00
|
|
|
return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
|
|
|
|
WL12XX_INTR_TRIG_EVENT_ACK);
|
2012-04-11 15:15:46 +08:00
|
|
|
}
|
|
|
|
|
2011-12-12 17:41:44 +08:00
|
|
|
static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
|
|
|
|
{
|
|
|
|
u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
|
|
|
|
u32 align_len = wlcore_calc_packet_alignment(wl, len);
|
|
|
|
|
|
|
|
return (align_len + blk_size - 1) / blk_size + spare_blks;
|
|
|
|
}
|
|
|
|
|
2011-12-12 17:44:27 +08:00
|
|
|
static void
|
|
|
|
wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
|
|
|
|
u32 blks, u32 spare_blks)
|
|
|
|
{
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20) {
|
|
|
|
desc->wl128x_mem.total_mem_blocks = blks;
|
|
|
|
} else {
|
|
|
|
desc->wl127x_mem.extra_blocks = spare_blks;
|
|
|
|
desc->wl127x_mem.total_mem_blocks = blks;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-12-12 17:47:09 +08:00
|
|
|
static void
|
|
|
|
wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
|
|
|
|
struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
|
|
|
|
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20) {
|
|
|
|
desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
|
|
|
|
desc->length = cpu_to_le16(aligned_len >> 2);
|
|
|
|
|
|
|
|
wl1271_debug(DEBUG_TX,
|
|
|
|
"tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
|
|
|
|
desc->hlid,
|
|
|
|
le16_to_cpu(desc->length),
|
|
|
|
le16_to_cpu(desc->life_time),
|
|
|
|
desc->wl128x_mem.total_mem_blocks,
|
|
|
|
desc->wl128x_mem.extra_bytes);
|
|
|
|
} else {
|
|
|
|
/* calculate number of padding bytes */
|
|
|
|
int pad = aligned_len - skb->len;
|
|
|
|
desc->tx_attr |=
|
|
|
|
cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
|
|
|
|
|
|
|
|
/* Store the aligned length in terms of words */
|
|
|
|
desc->length = cpu_to_le16(aligned_len >> 2);
|
|
|
|
|
|
|
|
wl1271_debug(DEBUG_TX,
|
|
|
|
"tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
|
|
|
|
pad, desc->hlid,
|
|
|
|
le16_to_cpu(desc->length),
|
|
|
|
le16_to_cpu(desc->life_time),
|
|
|
|
desc->wl127x_mem.total_mem_blocks);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-12-12 18:11:43 +08:00
|
|
|
static enum wl_rx_buf_align
|
|
|
|
wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
|
|
|
|
{
|
|
|
|
if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
|
|
|
|
return WLCORE_RX_BUF_UNALIGNED;
|
|
|
|
|
|
|
|
return WLCORE_RX_BUF_ALIGNED;
|
|
|
|
}
|
|
|
|
|
2011-12-12 18:18:17 +08:00
|
|
|
static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
|
|
|
|
u32 data_len)
|
|
|
|
{
|
|
|
|
struct wl1271_rx_descriptor *desc = rx_data;
|
|
|
|
|
|
|
|
/* invalid packet */
|
|
|
|
if (data_len < sizeof(*desc) ||
|
|
|
|
data_len < sizeof(*desc) + desc->pad_len)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return data_len - sizeof(*desc) - desc->pad_len;
|
|
|
|
}
|
|
|
|
|
2012-06-18 17:31:16 +08:00
|
|
|
static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
|
2011-12-12 17:32:37 +08:00
|
|
|
{
|
2012-05-10 17:13:54 +08:00
|
|
|
if (wl->fw_status_1->tx_results_counter ==
|
|
|
|
(wl->tx_results_count & 0xff))
|
2012-06-18 17:31:16 +08:00
|
|
|
return 0;
|
2011-12-12 17:32:37 +08:00
|
|
|
|
2012-06-18 17:31:16 +08:00
|
|
|
return wlcore_tx_complete(wl);
|
2011-12-12 17:32:37 +08:00
|
|
|
}
|
|
|
|
|
2011-12-02 06:47:45 +08:00
|
|
|
static int wl12xx_hw_init(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20) {
|
|
|
|
u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
|
|
|
|
|
|
|
|
ret = wl128x_cmd_general_parms(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-07-11 23:48:06 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are in calibrator based auto detect then we got the FEM nr
|
|
|
|
* in wl->fem_manuf. No need to continue further
|
|
|
|
*/
|
|
|
|
if (wl->plt_mode == PLT_FEM_DETECT)
|
|
|
|
goto out;
|
|
|
|
|
2011-12-02 06:47:45 +08:00
|
|
|
ret = wl128x_cmd_radio_parms(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
|
|
|
|
/* Enable SDIO padding */
|
|
|
|
host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
|
|
|
|
|
|
|
|
/* Must be before wl1271_acx_init_mem_config() */
|
|
|
|
ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
} else {
|
|
|
|
ret = wl1271_cmd_general_parms(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-07-11 23:48:06 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are in calibrator based auto detect then we got the FEM nr
|
|
|
|
* in wl->fem_manuf. No need to continue further
|
|
|
|
*/
|
|
|
|
if (wl->plt_mode == PLT_FEM_DETECT)
|
|
|
|
goto out;
|
|
|
|
|
2011-12-02 06:47:45 +08:00
|
|
|
ret = wl1271_cmd_radio_parms(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
ret = wl1271_cmd_ext_radio_parms(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-12-13 19:18:17 +08:00
|
|
|
static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
|
|
|
|
struct wl12xx_vif *wlvif)
|
|
|
|
{
|
|
|
|
return wlvif->rate_set;
|
|
|
|
}
|
|
|
|
|
2011-12-07 04:24:57 +08:00
|
|
|
static int wl12xx_identify_fw(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
unsigned int *fw_ver = wl->chip.fw_ver;
|
|
|
|
|
|
|
|
/* Only new station firmwares support routing fw logs to the host */
|
|
|
|
if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
|
|
|
|
(fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
|
|
|
|
wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
|
|
|
|
|
|
|
|
/* This feature is not yet supported for AP mode */
|
|
|
|
if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
|
|
|
|
wl->quirks |= WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-12-05 22:12:54 +08:00
|
|
|
static void wl12xx_conf_init(struct wl1271 *wl)
|
|
|
|
{
|
2011-12-06 01:52:22 +08:00
|
|
|
struct wl12xx_priv *priv = wl->priv;
|
|
|
|
|
2011-12-05 22:12:54 +08:00
|
|
|
/* apply driver default configuration */
|
|
|
|
memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
|
2011-12-06 01:52:22 +08:00
|
|
|
|
|
|
|
/* apply default private configuration */
|
|
|
|
memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
|
2011-12-05 22:12:54 +08:00
|
|
|
}
|
|
|
|
|
2012-04-11 16:07:28 +08:00
|
|
|
static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
bool supported = false;
|
|
|
|
u8 major, minor;
|
|
|
|
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20) {
|
|
|
|
major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
|
|
|
|
minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
|
|
|
|
|
|
|
|
/* in wl128x we have the MAC address if the PG is >= (2, 1) */
|
|
|
|
if (major > 2 || (major == 2 && minor >= 1))
|
|
|
|
supported = true;
|
|
|
|
} else {
|
|
|
|
major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
|
|
|
|
minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
|
|
|
|
|
|
|
|
/* in wl127x we have the MAC address if the PG is >= (3, 1) */
|
|
|
|
if (major == 3 && minor >= 1)
|
|
|
|
supported = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
wl1271_debug(DEBUG_PROBE,
|
|
|
|
"PG Ver major = %d minor = %d, MAC %s present",
|
|
|
|
major, minor, supported ? "is" : "is not");
|
|
|
|
|
|
|
|
return supported;
|
|
|
|
}
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
static int wl12xx_get_fuse_mac(struct wl1271 *wl)
|
2012-04-11 16:07:28 +08:00
|
|
|
{
|
|
|
|
u32 mac1, mac2;
|
2012-06-18 20:50:21 +08:00
|
|
|
int ret;
|
2012-04-11 16:07:28 +08:00
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:07:28 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2012-04-11 16:07:28 +08:00
|
|
|
|
|
|
|
/* these are the two parts of the BD_ADDR */
|
|
|
|
wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
|
|
|
|
((mac1 & 0xff000000) >> 24);
|
|
|
|
wl->fuse_nic_addr = mac1 & 0xffffff;
|
|
|
|
|
2012-06-20 05:48:23 +08:00
|
|
|
ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
|
2012-06-18 20:50:21 +08:00
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
2012-04-11 16:07:28 +08:00
|
|
|
}
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
|
2012-04-11 15:54:52 +08:00
|
|
|
{
|
2012-06-18 20:50:21 +08:00
|
|
|
u16 die_info;
|
|
|
|
int ret;
|
2012-04-11 15:54:52 +08:00
|
|
|
|
|
|
|
if (wl->chip.id == CHIP_ID_1283_PG20)
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
|
|
|
|
&die_info);
|
2012-04-11 15:54:52 +08:00
|
|
|
else
|
2012-06-18 20:50:21 +08:00
|
|
|
ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
|
|
|
|
&die_info);
|
2012-04-11 15:54:52 +08:00
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
if (ret >= 0 && ver)
|
|
|
|
*ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
|
|
|
|
|
|
|
|
return ret;
|
2012-04-11 15:54:52 +08:00
|
|
|
}
|
|
|
|
|
2012-06-18 20:50:21 +08:00
|
|
|
static int wl12xx_get_mac(struct wl1271 *wl)
|
2012-04-11 16:07:28 +08:00
|
|
|
{
|
|
|
|
if (wl12xx_mac_in_fuse(wl))
|
2012-06-18 20:50:21 +08:00
|
|
|
return wl12xx_get_fuse_mac(wl);
|
|
|
|
|
|
|
|
return 0;
|
2012-04-11 16:07:28 +08:00
|
|
|
}
|
|
|
|
|
2012-05-10 17:13:27 +08:00
|
|
|
static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
|
|
|
|
struct wl1271_tx_hw_descr *desc,
|
|
|
|
struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
desc->wl12xx_reserved = 0;
|
|
|
|
}
|
|
|
|
|
2012-05-10 17:13:49 +08:00
|
|
|
static int wl12xx_plt_init(struct wl1271 *wl)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = wl->ops->boot(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = wl->ops->hw_init(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out_irq_disable;
|
|
|
|
|
2012-07-11 23:48:06 +08:00
|
|
|
/*
|
|
|
|
* If we are in calibrator based auto detect then we got the FEM nr
|
|
|
|
* in wl->fem_manuf. No need to continue further
|
|
|
|
*/
|
|
|
|
if (wl->plt_mode == PLT_FEM_DETECT)
|
|
|
|
goto out;
|
|
|
|
|
2012-05-10 17:13:49 +08:00
|
|
|
ret = wl1271_acx_init_mem_config(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out_irq_disable;
|
|
|
|
|
|
|
|
ret = wl12xx_acx_mem_cfg(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out_free_memmap;
|
|
|
|
|
|
|
|
/* Enable data path */
|
|
|
|
ret = wl1271_cmd_data_path(wl, 1);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out_free_memmap;
|
|
|
|
|
|
|
|
/* Configure for CAM power saving (ie. always active) */
|
|
|
|
ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out_free_memmap;
|
|
|
|
|
|
|
|
/* configure PM */
|
|
|
|
ret = wl1271_acx_pm_config(wl);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out_free_memmap;
|
|
|
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
out_free_memmap:
|
|
|
|
kfree(wl->target_mem_map);
|
|
|
|
wl->target_mem_map = NULL;
|
|
|
|
|
|
|
|
out_irq_disable:
|
|
|
|
mutex_unlock(&wl->mutex);
|
|
|
|
/* Unlocking the mutex in the middle of handling is
|
|
|
|
inherently unsafe. In this case we deem it safe to do,
|
|
|
|
because we need to let any possibly pending IRQ out of
|
|
|
|
the system (and while we are WL1271_STATE_OFF the IRQ
|
|
|
|
work function will not do anything.) Also, any other
|
|
|
|
possible concurrent operations will fail due to the
|
|
|
|
current state, hence the wl1271 struct should be safe. */
|
|
|
|
wlcore_disable_interrupts(wl);
|
|
|
|
mutex_lock(&wl->mutex);
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-18 12:46:37 +08:00
|
|
|
static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
|
|
|
|
{
|
|
|
|
if (is_gem)
|
|
|
|
return WL12XX_TX_HW_BLOCK_GEM_SPARE;
|
|
|
|
|
|
|
|
return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
|
|
|
|
}
|
|
|
|
|
2012-05-18 12:46:40 +08:00
|
|
|
static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
|
|
|
|
struct ieee80211_vif *vif,
|
|
|
|
struct ieee80211_sta *sta,
|
|
|
|
struct ieee80211_key_conf *key_conf)
|
|
|
|
{
|
|
|
|
return wlcore_set_key(wl, cmd, vif, sta, key_conf);
|
|
|
|
}
|
|
|
|
|
2011-11-29 22:27:31 +08:00
|
|
|
static struct wlcore_ops wl12xx_ops = {
|
2011-12-12 17:44:27 +08:00
|
|
|
.identify_chip = wl12xx_identify_chip,
|
2011-12-07 04:24:57 +08:00
|
|
|
.identify_fw = wl12xx_identify_fw,
|
2011-12-12 17:44:27 +08:00
|
|
|
.boot = wl12xx_boot,
|
2012-05-10 17:13:49 +08:00
|
|
|
.plt_init = wl12xx_plt_init,
|
2011-12-12 17:44:27 +08:00
|
|
|
.trigger_cmd = wl12xx_trigger_cmd,
|
|
|
|
.ack_event = wl12xx_ack_event,
|
|
|
|
.calc_tx_blocks = wl12xx_calc_tx_blocks,
|
|
|
|
.set_tx_desc_blocks = wl12xx_set_tx_desc_blocks,
|
2011-12-12 17:47:09 +08:00
|
|
|
.set_tx_desc_data_len = wl12xx_set_tx_desc_data_len,
|
2011-12-12 18:11:43 +08:00
|
|
|
.get_rx_buf_align = wl12xx_get_rx_buf_align,
|
2011-12-12 18:18:17 +08:00
|
|
|
.get_rx_packet_len = wl12xx_get_rx_packet_len,
|
2011-12-12 17:32:37 +08:00
|
|
|
.tx_immediate_compl = NULL,
|
|
|
|
.tx_delayed_compl = wl12xx_tx_delayed_compl,
|
2011-12-02 06:47:45 +08:00
|
|
|
.hw_init = wl12xx_hw_init,
|
2011-12-13 18:15:09 +08:00
|
|
|
.init_vif = NULL,
|
2011-12-13 19:18:17 +08:00
|
|
|
.sta_get_ap_rate_mask = wl12xx_sta_get_ap_rate_mask,
|
2011-12-12 17:44:27 +08:00
|
|
|
.get_pg_ver = wl12xx_get_pg_ver,
|
|
|
|
.get_mac = wl12xx_get_mac,
|
2012-05-10 17:13:27 +08:00
|
|
|
.set_tx_desc_csum = wl12xx_set_tx_desc_csum,
|
2012-05-10 17:13:28 +08:00
|
|
|
.set_rx_csum = NULL,
|
2012-05-10 17:13:34 +08:00
|
|
|
.ap_get_mimo_wide_rate_mask = NULL,
|
2012-05-10 17:14:19 +08:00
|
|
|
.debugfs_init = wl12xx_debugfs_add_files,
|
2012-05-18 12:46:37 +08:00
|
|
|
.get_spare_blocks = wl12xx_get_spare_blocks,
|
2012-05-18 12:46:40 +08:00
|
|
|
.set_key = wl12xx_set_key,
|
2012-05-13 19:53:40 +08:00
|
|
|
.pre_pkt_send = NULL,
|
2011-11-29 22:27:31 +08:00
|
|
|
};
|
|
|
|
|
2011-12-13 19:20:44 +08:00
|
|
|
static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
|
|
|
|
.cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
|
|
|
|
(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
|
|
|
|
.ht_supported = true,
|
|
|
|
.ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
|
|
|
|
.ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
|
|
|
|
.mcs = {
|
|
|
|
.rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
|
|
|
|
.rx_highest = cpu_to_le16(72),
|
|
|
|
.tx_params = IEEE80211_HT_MCS_TX_DEFINED,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-11-22 00:55:51 +08:00
|
|
|
static int __devinit wl12xx_probe(struct platform_device *pdev)
|
|
|
|
{
|
2012-05-10 17:13:43 +08:00
|
|
|
struct wl12xx_platform_data *pdata = pdev->dev.platform_data;
|
2011-11-22 00:55:51 +08:00
|
|
|
struct wl1271 *wl;
|
|
|
|
struct ieee80211_hw *hw;
|
2011-12-08 03:09:03 +08:00
|
|
|
struct wl12xx_priv *priv;
|
2011-11-22 00:55:51 +08:00
|
|
|
|
2012-07-29 23:21:12 +08:00
|
|
|
hw = wlcore_alloc_hw(sizeof(*priv), WL12XX_AGGR_BUFFER_SIZE);
|
2011-11-22 00:55:51 +08:00
|
|
|
if (IS_ERR(hw)) {
|
|
|
|
wl1271_error("can't allocate hw");
|
|
|
|
return PTR_ERR(hw);
|
|
|
|
}
|
|
|
|
|
|
|
|
wl = hw->priv;
|
2012-05-10 17:13:43 +08:00
|
|
|
priv = wl->priv;
|
2011-11-22 01:25:24 +08:00
|
|
|
wl->ops = &wl12xx_ops;
|
2011-11-22 02:37:14 +08:00
|
|
|
wl->ptable = wl12xx_ptable;
|
2011-11-29 19:38:37 +08:00
|
|
|
wl->rtable = wl12xx_rtable;
|
2012-07-31 19:48:46 +08:00
|
|
|
wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
|
|
|
|
wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
|
2011-12-08 06:43:48 +08:00
|
|
|
wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
|
|
|
|
wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
|
|
|
|
wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
|
2011-12-12 18:08:25 +08:00
|
|
|
wl->fw_status_priv_len = 0;
|
2012-05-10 17:14:08 +08:00
|
|
|
wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
|
2012-06-14 00:09:25 +08:00
|
|
|
wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ, &wl12xx_ht_cap);
|
|
|
|
wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ, &wl12xx_ht_cap);
|
2011-12-05 22:12:54 +08:00
|
|
|
wl12xx_conf_init(wl);
|
2011-11-22 00:55:51 +08:00
|
|
|
|
2012-05-10 17:13:43 +08:00
|
|
|
if (!fref_param) {
|
|
|
|
priv->ref_clock = pdata->board_ref_clock;
|
|
|
|
} else {
|
|
|
|
if (!strcmp(fref_param, "19.2"))
|
|
|
|
priv->ref_clock = WL12XX_REFCLOCK_19;
|
|
|
|
else if (!strcmp(fref_param, "26"))
|
|
|
|
priv->ref_clock = WL12XX_REFCLOCK_26;
|
|
|
|
else if (!strcmp(fref_param, "26x"))
|
|
|
|
priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
|
|
|
|
else if (!strcmp(fref_param, "38.4"))
|
|
|
|
priv->ref_clock = WL12XX_REFCLOCK_38;
|
|
|
|
else if (!strcmp(fref_param, "38.4x"))
|
|
|
|
priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
|
|
|
|
else if (!strcmp(fref_param, "52"))
|
|
|
|
priv->ref_clock = WL12XX_REFCLOCK_52;
|
|
|
|
else
|
|
|
|
wl1271_error("Invalid fref parameter %s", fref_param);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!tcxo_param) {
|
|
|
|
priv->tcxo_clock = pdata->board_tcxo_clock;
|
|
|
|
} else {
|
|
|
|
if (!strcmp(tcxo_param, "19.2"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
|
|
|
|
else if (!strcmp(tcxo_param, "26"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
|
|
|
|
else if (!strcmp(tcxo_param, "38.4"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
|
|
|
|
else if (!strcmp(tcxo_param, "52"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
|
|
|
|
else if (!strcmp(tcxo_param, "16.368"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
|
|
|
|
else if (!strcmp(tcxo_param, "32.736"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
|
|
|
|
else if (!strcmp(tcxo_param, "16.8"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
|
|
|
|
else if (!strcmp(tcxo_param, "33.6"))
|
|
|
|
priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
|
|
|
|
else
|
|
|
|
wl1271_error("Invalid tcxo parameter %s", tcxo_param);
|
|
|
|
}
|
|
|
|
|
2011-11-22 00:55:51 +08:00
|
|
|
return wlcore_probe(wl, pdev);
|
|
|
|
}
|
2011-11-21 05:32:10 +08:00
|
|
|
|
|
|
|
static const struct platform_device_id wl12xx_id_table[] __devinitconst = {
|
|
|
|
{ "wl12xx", 0 },
|
|
|
|
{ } /* Terminating Entry */
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
|
|
|
|
|
|
|
|
static struct platform_driver wl12xx_driver = {
|
2011-11-22 00:55:51 +08:00
|
|
|
.probe = wl12xx_probe,
|
2011-11-21 05:32:10 +08:00
|
|
|
.remove = __devexit_p(wlcore_remove),
|
|
|
|
.id_table = wl12xx_id_table,
|
|
|
|
.driver = {
|
|
|
|
.name = "wl12xx_driver",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-09-27 17:02:38 +08:00
|
|
|
module_platform_driver(wl12xx_driver);
|
2011-11-21 05:32:10 +08:00
|
|
|
|
2012-05-10 17:13:43 +08:00
|
|
|
module_param_named(fref, fref_param, charp, 0);
|
|
|
|
MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
|
|
|
|
|
|
|
|
module_param_named(tcxo, tcxo_param, charp, 0);
|
|
|
|
MODULE_PARM_DESC(tcxo,
|
|
|
|
"TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
|
|
|
|
|
2011-11-21 05:32:10 +08:00
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
|
2011-11-29 22:27:31 +08:00
|
|
|
MODULE_FIRMWARE(WL127X_FW_NAME_SINGLE);
|
|
|
|
MODULE_FIRMWARE(WL127X_FW_NAME_MULTI);
|
|
|
|
MODULE_FIRMWARE(WL127X_PLT_FW_NAME);
|
|
|
|
MODULE_FIRMWARE(WL128X_FW_NAME_SINGLE);
|
|
|
|
MODULE_FIRMWARE(WL128X_FW_NAME_MULTI);
|
|
|
|
MODULE_FIRMWARE(WL128X_PLT_FW_NAME);
|