2019-07-12 00:52:01 +08:00
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======================================
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Coresight - HW Assisted Tracing on ARM
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======================================
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2014-11-04 02:07:42 +08:00
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2019-07-12 00:52:01 +08:00
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:Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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:Date: September 11th, 2014
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2014-11-04 02:07:42 +08:00
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Introduction
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------------
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Coresight is an umbrella of technologies allowing for the debugging of ARM
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based SoC. It includes solutions for JTAG and HW assisted tracing. This
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document is concerned with the latter.
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HW assisted tracing is becoming increasingly useful when dealing with systems
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that have many SoCs and other components like GPU and DMA engines. ARM has
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developed a HW assisted tracing solution by means of different components, each
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2015-03-31 04:13:37 +08:00
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being added to a design at synthesis time to cater to specific tracing needs.
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2015-07-31 23:37:29 +08:00
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Components are generally categorised as source, link and sinks and are
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2014-11-04 02:07:42 +08:00
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(usually) discovered using the AMBA bus.
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"Sources" generate a compressed stream representing the processor instruction
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path based on tracing scenarios as configured by users. From there the stream
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flows through the coresight system (via ATB bus) using links that are connecting
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the emanating source to a sink(s). Sinks serve as endpoints to the coresight
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implementation, either storing the compressed stream in a memory buffer or
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creating an interface to the outside world where data can be transferred to a
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host without fear of filling up the onboard coresight memory buffer.
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2019-07-12 00:52:01 +08:00
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At typical coresight system would look like this::
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2014-11-04 02:07:42 +08:00
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*****************************************************************
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**************************** AMBA AXI ****************************===||
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***************************************************************** ||
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^ ^ | ||
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0000000 ::::: 0000000 ::::: ::::: @@@@@@@ ||||||||||||
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0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
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|->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
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| #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
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| # ETM # ::::: | # PTM # ::::: ::::: @ |
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| ##### ^ ^ | ##### ^ ! ^ ! . | |||||||||
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| |->### | ! | |->### | ! | ! . | || DAP ||
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| | # | ! | | # | ! | ! . | |||||||||
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| | . | ! | | . | ! | ! . | | |
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| | . | ! | | . | ! | ! . | | *
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| | . | ! | | . | ! | ! . | | SWD/
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| | . | ! | | . | ! | ! . | | JTAG
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*****************************************************************<-|
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2015-01-27 00:22:21 +08:00
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*************************** AMBA Debug APB ************************
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*****************************************************************
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| . ! . ! ! . |
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| . * . * * . |
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*****************************************************************
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******************** Cross Trigger Matrix (CTM) *******************
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*****************************************************************
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| . ^ . . |
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| * ! * * |
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*****************************************************************
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****************** AMBA Advanced Trace Bus (ATB) ******************
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*****************************************************************
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| ! =============== |
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| * ===== F =====<---------|
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| ::::::::: ==== U ====
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|-->:: CTI ::<!! === N ===
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| ::::::::: ! == N ==
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| ^ * == E ==
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| ! &&&&&&&&& IIIIIII == L ==
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|------>&& ETB &&<......II I =======
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| ! &&&&&&&&& II I .
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| ! I I .
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| ! I REP I<..........
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| ! I I
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| !!>&&&&&&&&& II I *Source: ARM ltd.
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|------>& TPIU &<......II I DAP = Debug Access Port
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&&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell
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; PTM = Program Trace Macrocell
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; CTI = Cross Trigger Interface
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* ETB = Embedded Trace Buffer
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To trace port TPIU= Trace Port Interface Unit
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SWD = Serial Wire Debug
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2015-01-27 00:22:21 +08:00
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While on target configuration of the components is done via the APB bus,
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2014-11-04 02:07:42 +08:00
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all trace data are carried out-of-band on the ATB bus. The CTM provides
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a way to aggregate and distribute signals between CoreSight components.
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The coresight framework provides a central point to represent, configure and
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manage coresight devices on a platform. This first implementation centers on
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the basic tracing functionality, enabling components such ETM/PTM, funnel,
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replicator, TMC, TPIU and ETB. Future work will enable more
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intricate IP blocks such as STM and CTI.
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Acronyms and Classification
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---------------------------
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Acronyms:
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2019-07-12 00:52:01 +08:00
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PTM:
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Program Trace Macrocell
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ETM:
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Embedded Trace Macrocell
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STM:
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System trace Macrocell
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ETB:
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Embedded Trace Buffer
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ITM:
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Instrumentation Trace Macrocell
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TPIU:
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Trace Port Interface Unit
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TMC-ETR:
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Trace Memory Controller, configured as Embedded Trace Router
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TMC-ETF:
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Trace Memory Controller, configured as Embedded Trace FIFO
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CTI:
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Cross Trigger Interface
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2014-11-04 02:07:42 +08:00
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Classification:
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Source:
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ETMv3.x ETMv4, PTMv1.0, PTMv1.1, STM, STM500, ITM
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Link:
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Funnel, replicator (intelligent or not), TMC-ETR
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Sinks:
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ETBv1.0, ETB1.1, TPIU, TMC-ETF
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Misc:
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CTI
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Device Tree Bindings
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2019-07-12 00:52:01 +08:00
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--------------------
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2014-11-04 02:07:42 +08:00
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See Documentation/devicetree/bindings/arm/coresight.txt for details.
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As of this writing drivers for ITM, STMs and CTIs are not provided but are
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expected to be added as the solution matures.
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Framework and implementation
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----------------------------
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The coresight framework provides a central point to represent, configure and
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manage coresight devices on a platform. Any coresight compliant device can
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register with the framework for as long as they use the right APIs:
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2019-07-12 00:52:01 +08:00
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.. c:function:: struct coresight_device *coresight_register(struct coresight_desc *desc);
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.. c:function:: void coresight_unregister(struct coresight_device *csdev);
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The registering function is taking a ``struct coresight_desc *desc`` and
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register the device with the core framework. The unregister function takes
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a reference to a ``struct coresight_device *csdev`` obtained at registration time.
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If everything goes well during the registration process the new devices will
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show up under /sys/bus/coresight/devices, as showns here for a TC2 platform::
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2019-07-12 00:52:01 +08:00
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root:~# ls /sys/bus/coresight/devices/
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replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
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20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
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root:~#
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2019-07-12 00:52:01 +08:00
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The functions take a ``struct coresight_device``, which looks like this::
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struct coresight_desc {
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enum coresight_dev_type type;
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struct coresight_dev_subtype subtype;
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const struct coresight_ops *ops;
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struct coresight_platform_data *pdata;
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struct device *dev;
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const struct attribute_group **groups;
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};
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The "coresight_dev_type" identifies what the device is, i.e, source link or
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sink while the "coresight_dev_subtype" will characterise that type further.
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2019-07-12 00:52:01 +08:00
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The ``struct coresight_ops`` is mandatory and will tell the framework how to
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perform base operations related to the components, each component having
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a different set of requirement. For that ``struct coresight_ops_sink``,
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``struct coresight_ops_link`` and ``struct coresight_ops_source`` have been
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provided.
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2019-07-12 00:52:01 +08:00
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The next field ``struct coresight_platform_data *pdata`` is acquired by calling
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``of_get_coresight_platform_data()``, as part of the driver's _probe routine and
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``struct device *dev`` gets the device reference embedded in the ``amba_device``::
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2019-07-12 00:52:01 +08:00
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static int etm_probe(struct amba_device *adev, const struct amba_id *id)
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{
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...
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...
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drvdata->dev = &adev->dev;
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...
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}
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Specific class of device (source, link, or sink) have generic operations
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that can be performed on them (see ``struct coresight_ops``). The ``**groups``
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is a list of sysfs entries pertaining to operations
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specific to that component only. "Implementation defined" customisations are
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expected to be accessed and controlled using those entries.
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2019-06-11 02:02:42 +08:00
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Device Naming scheme
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--------------------
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2019-06-11 02:02:42 +08:00
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The devices that appear on the "coresight" bus were named the same as their
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parent devices, i.e, the real devices that appears on AMBA bus or the platform bus.
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Thus the names were based on the Linux Open Firmware layer naming convention,
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which follows the base physical address of the device followed by the device
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type. e.g::
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2019-07-12 00:52:01 +08:00
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root:~# ls /sys/bus/coresight/devices/
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20010000.etf 20040000.funnel 20100000.stm 22040000.etm
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22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu
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20070000.etr 20120000.replicator 220c0000.funnel
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23040000.etm 23140000.etm 23340000.etm
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However, with the introduction of ACPI support, the names of the real
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devices are a bit cryptic and non-obvious. Thus, a new naming scheme was
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introduced to use more generic names based on the type of the device. The
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following rules apply::
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1) Devices that are bound to CPUs, are named based on the CPU logical
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number.
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e.g, ETM bound to CPU0 is named "etm0"
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2) All other devices follow a pattern, "<device_type_prefix>N", where :
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<device_type_prefix> - A prefix specific to the type of the device
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N - a sequential number assigned based on the order
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of probing.
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e.g, tmc_etf0, tmc_etr0, funnel0, funnel1
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2019-07-12 00:52:01 +08:00
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Thus, with the new scheme the devices could appear as ::
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2019-07-12 00:52:01 +08:00
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root:~# ls /sys/bus/coresight/devices/
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etm0 etm1 etm2 etm3 etm4 etm5 funnel0
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funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0
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Some of the examples below might refer to old naming scheme and some
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to the newer scheme, to give a confirmation that what you see on your
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system is not unexpected. One must use the "names" as they appear on
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the system under specified locations.
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2020-05-19 02:02:25 +08:00
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Topology Representation
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-----------------------
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Each CoreSight component has a ``connections`` directory which will contain
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links to other CoreSight components. This allows the user to explore the trace
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topology and for larger systems, determine the most appropriate sink for a
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given source. The connection information can also be used to establish
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which CTI devices are connected to a given component. This directory contains a
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``nr_links`` attribute detailing the number of links in the directory.
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For an ETM source, in this case ``etm0`` on a Juno platform, a typical
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arrangement will be::
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linaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections
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<file details> cti_cpu0 -> ../../../23020000.cti/cti_cpu0
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<file details> nr_links
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<file details> out:0 -> ../../../230c0000.funnel/funnel2
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Following the out port to ``funnel2``::
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linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections
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<file details> in:0 -> ../../../23040000.etm/etm0
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<file details> in:1 -> ../../../23140000.etm/etm3
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<file details> in:2 -> ../../../23240000.etm/etm4
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<file details> in:3 -> ../../../23340000.etm/etm5
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<file details> nr_links
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<file details> out:0 -> ../../../20040000.funnel/funnel0
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And again to ``funnel0``::
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linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections
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<file details> in:0 -> ../../../220c0000.funnel/funnel1
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<file details> in:1 -> ../../../230c0000.funnel/funnel2
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<file details> nr_links
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<file details> out:0 -> ../../../20010000.etf/tmc_etf0
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Finding the first sink ``tmc_etf0``. This can be used to collect data
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as a sink, or as a link to propagate further along the chain::
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linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections
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<file details> cti_sys0 -> ../../../20020000.cti/cti_sys0
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<file details> in:0 -> ../../../20040000.funnel/funnel0
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|
|
|
|
<file details> nr_links
|
|
|
|
|
<file details> out:0 -> ../../../20150000.funnel/funnel4
|
|
|
|
|
|
|
|
|
|
via ``funnel4``::
|
|
|
|
|
|
|
|
|
|
linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections
|
|
|
|
|
<file details> in:0 -> ../../../20010000.etf/tmc_etf0
|
|
|
|
|
<file details> in:1 -> ../../../20140000.etf/tmc_etf1
|
|
|
|
|
<file details> nr_links
|
|
|
|
|
<file details> out:0 -> ../../../20120000.replicator/replicator0
|
|
|
|
|
|
|
|
|
|
and a ``replicator0``::
|
|
|
|
|
|
|
|
|
|
linaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections
|
|
|
|
|
<file details> in:0 -> ../../../20150000.funnel/funnel4
|
|
|
|
|
<file details> nr_links
|
|
|
|
|
<file details> out:0 -> ../../../20030000.tpiu/tpiu0
|
|
|
|
|
<file details> out:1 -> ../../../20070000.etr/tmc_etr0
|
|
|
|
|
|
|
|
|
|
Arriving at the final sink in the chain, ``tmc_etr0``::
|
|
|
|
|
|
|
|
|
|
linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections
|
|
|
|
|
<file details> cti_sys0 -> ../../../20020000.cti/cti_sys0
|
|
|
|
|
<file details> in:0 -> ../../../20120000.replicator/replicator0
|
|
|
|
|
<file details> nr_links
|
|
|
|
|
|
|
|
|
|
As described below, when using sysfs it is sufficient to enable a sink and
|
|
|
|
|
a source for successful trace. The framework will correctly enable all
|
|
|
|
|
intermediate links as required.
|
|
|
|
|
|
|
|
|
|
Note: ``cti_sys0`` appears in two of the connections lists above.
|
|
|
|
|
CTIs can connect to multiple devices and are arranged in a star topology
|
|
|
|
|
via the CTM. See (:doc:`coresight-ect`) [#fourth]_ for further details.
|
|
|
|
|
Looking at this device we see 4 connections::
|
|
|
|
|
|
|
|
|
|
linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections
|
|
|
|
|
<file details> nr_links
|
|
|
|
|
<file details> stm0 -> ../../../20100000.stm/stm0
|
|
|
|
|
<file details> tmc_etf0 -> ../../../20010000.etf/tmc_etf0
|
|
|
|
|
<file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0
|
|
|
|
|
<file details> tpiu0 -> ../../../20030000.tpiu/tpiu0
|
|
|
|
|
|
|
|
|
|
|
2016-05-04 01:33:40 +08:00
|
|
|
How to use the tracer modules
|
|
|
|
|
-----------------------------
|
2014-11-04 02:07:42 +08:00
|
|
|
|
2019-07-12 00:52:01 +08:00
|
|
|
There are two ways to use the Coresight framework:
|
|
|
|
|
|
|
|
|
|
1. using the perf cmd line tools.
|
|
|
|
|
2. interacting directly with the Coresight devices using the sysFS interface.
|
|
|
|
|
|
|
|
|
|
Preference is given to the former as using the sysFS interface
|
2018-04-18 00:08:06 +08:00
|
|
|
requires a deep understanding of the Coresight HW. The following sections
|
|
|
|
|
provide details on using both methods.
|
|
|
|
|
|
|
|
|
|
1) Using the sysFS interface:
|
|
|
|
|
|
|
|
|
|
Before trace collection can start, a coresight sink needs to be identified.
|
2014-11-04 02:07:42 +08:00
|
|
|
There is no limit on the amount of sinks (nor sources) that can be enabled at
|
|
|
|
|
any given moment. As a generic operation, all device pertaining to the sink
|
2019-07-12 00:52:01 +08:00
|
|
|
class will have an "active" entry in sysfs::
|
|
|
|
|
|
|
|
|
|
root:/sys/bus/coresight/devices# ls
|
|
|
|
|
replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
|
|
|
|
|
20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
|
|
|
|
|
root:/sys/bus/coresight/devices# ls 20010000.etb
|
|
|
|
|
enable_sink status trigger_cntr
|
|
|
|
|
root:/sys/bus/coresight/devices# echo 1 > 20010000.etb/enable_sink
|
|
|
|
|
root:/sys/bus/coresight/devices# cat 20010000.etb/enable_sink
|
|
|
|
|
1
|
|
|
|
|
root:/sys/bus/coresight/devices#
|
2014-11-04 02:07:42 +08:00
|
|
|
|
|
|
|
|
At boot time the current etm3x driver will configure the first address
|
|
|
|
|
comparator with "_stext" and "_etext", essentially tracing any instruction
|
|
|
|
|
that falls within that range. As such "enabling" a source will immediately
|
2019-07-12 00:52:01 +08:00
|
|
|
trigger a trace capture::
|
|
|
|
|
|
|
|
|
|
root:/sys/bus/coresight/devices# echo 1 > 2201c000.ptm/enable_source
|
|
|
|
|
root:/sys/bus/coresight/devices# cat 2201c000.ptm/enable_source
|
|
|
|
|
1
|
|
|
|
|
root:/sys/bus/coresight/devices# cat 20010000.etb/status
|
|
|
|
|
Depth: 0x2000
|
|
|
|
|
Status: 0x1
|
|
|
|
|
RAM read ptr: 0x0
|
|
|
|
|
RAM wrt ptr: 0x19d3 <----- The write pointer is moving
|
|
|
|
|
Trigger cnt: 0x0
|
|
|
|
|
Control: 0x1
|
|
|
|
|
Flush status: 0x0
|
|
|
|
|
Flush ctrl: 0x2001
|
|
|
|
|
root:/sys/bus/coresight/devices#
|
|
|
|
|
|
|
|
|
|
Trace collection is stopped the same way::
|
|
|
|
|
|
|
|
|
|
root:/sys/bus/coresight/devices# echo 0 > 2201c000.ptm/enable_source
|
|
|
|
|
root:/sys/bus/coresight/devices#
|
|
|
|
|
|
|
|
|
|
The content of the ETB buffer can be harvested directly from /dev::
|
|
|
|
|
|
|
|
|
|
root:/sys/bus/coresight/devices# dd if=/dev/20010000.etb \
|
|
|
|
|
of=~/cstrace.bin
|
|
|
|
|
64+0 records in
|
|
|
|
|
64+0 records out
|
|
|
|
|
32768 bytes (33 kB) copied, 0.00125258 s, 26.2 MB/s
|
|
|
|
|
root:/sys/bus/coresight/devices#
|
2014-11-04 02:07:42 +08:00
|
|
|
|
|
|
|
|
The file cstrace.bin can be decompressed using "ptm2human", DS-5 or Trace32.
|
|
|
|
|
|
|
|
|
|
Following is a DS-5 output of an experimental loop that increments a variable up
|
|
|
|
|
to a certain value. The example is simple and yet provides a glimpse of the
|
|
|
|
|
wealth of possibilities that coresight provides.
|
2019-07-12 00:52:01 +08:00
|
|
|
::
|
|
|
|
|
|
|
|
|
|
Info Tracing enabled
|
|
|
|
|
Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
|
|
|
|
|
Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
|
|
|
|
|
Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
|
|
|
|
|
Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B550 E3530004 false CMP r3,#4
|
|
|
|
|
Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
|
|
|
|
|
Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
|
|
|
|
|
Timestamp Timestamp: 17106715833
|
|
|
|
|
Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B550 E3530004 false CMP r3,#4
|
|
|
|
|
Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
|
|
|
|
|
Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
|
|
|
|
|
Instruction 9 0x8026B54C E59D3004 false LDR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B550 E3530004 false CMP r3,#4
|
|
|
|
|
Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
|
|
|
|
|
Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
|
|
|
|
|
Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B550 E3530004 false CMP r3,#4
|
|
|
|
|
Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
|
|
|
|
|
Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
|
|
|
|
|
Instruction 7 0x8026B54C E59D3004 false LDR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B550 E3530004 false CMP r3,#4
|
|
|
|
|
Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
|
|
|
|
|
Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
|
|
|
|
|
Instruction 10 0x8026B54C E59D3004 false LDR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B550 E3530004 false CMP r3,#4
|
|
|
|
|
Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
|
|
|
|
|
Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
|
|
|
|
|
Instruction 6 0x8026B560 EE1D3F30 false MRC p15,#0x0,r3,c13,c0,#1
|
|
|
|
|
Instruction 0 0x8026B564 E1A0100D false MOV r1,sp
|
|
|
|
|
Instruction 0 0x8026B568 E3C12D7F false BIC r2,r1,#0x1fc0
|
|
|
|
|
Instruction 0 0x8026B56C E3C2203F false BIC r2,r2,#0x3f
|
|
|
|
|
Instruction 0 0x8026B570 E59D1004 false LDR r1,[sp,#4]
|
|
|
|
|
Instruction 0 0x8026B574 E59F0010 false LDR r0,[pc,#16] ; [0x8026B58C] = 0x80550368
|
|
|
|
|
Instruction 0 0x8026B578 E592200C false LDR r2,[r2,#0xc]
|
|
|
|
|
Instruction 0 0x8026B57C E59221D0 false LDR r2,[r2,#0x1d0]
|
|
|
|
|
Instruction 0 0x8026B580 EB07A4CF true BL {pc}+0x1e9344 ; 0x804548c4
|
|
|
|
|
Info Tracing enabled
|
|
|
|
|
Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc
|
|
|
|
|
Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
|
|
|
|
|
Timestamp Timestamp: 17107041535
|
2016-05-04 01:33:40 +08:00
|
|
|
|
2018-04-18 00:08:06 +08:00
|
|
|
2) Using perf framework:
|
|
|
|
|
|
|
|
|
|
Coresight tracers are represented using the Perf framework's Performance
|
|
|
|
|
Monitoring Unit (PMU) abstraction. As such the perf framework takes charge of
|
|
|
|
|
controlling when tracing gets enabled based on when the process of interest is
|
|
|
|
|
scheduled. When configured in a system, Coresight PMUs will be listed when
|
|
|
|
|
queried by the perf command line tool:
|
|
|
|
|
|
|
|
|
|
linaro@linaro-nano:~$ ./perf list pmu
|
|
|
|
|
|
|
|
|
|
List of pre-defined events (to be used in -e):
|
|
|
|
|
|
|
|
|
|
cs_etm// [Kernel PMU event]
|
|
|
|
|
|
|
|
|
|
linaro@linaro-nano:~$
|
|
|
|
|
|
|
|
|
|
Regardless of the number of tracers available in a system (usually equal to the
|
|
|
|
|
amount of processor cores), the "cs_etm" PMU will be listed only once.
|
|
|
|
|
|
|
|
|
|
A Coresight PMU works the same way as any other PMU, i.e the name of the PMU is
|
|
|
|
|
listed along with configuration options within forward slashes '/'. Since a
|
|
|
|
|
Coresight system will typically have more than one sink, the name of the sink to
|
2019-06-11 02:02:42 +08:00
|
|
|
work with needs to be specified as an event option.
|
2019-07-12 00:52:01 +08:00
|
|
|
On newer kernels the available sinks are listed in sysFS under
|
|
|
|
|
($SYSFS)/bus/event_source/devices/cs_etm/sinks/::
|
2019-06-11 02:02:42 +08:00
|
|
|
|
|
|
|
|
root@localhost:/sys/bus/event_source/devices/cs_etm/sinks# ls
|
|
|
|
|
tmc_etf0 tmc_etr0 tpiu0
|
|
|
|
|
|
|
|
|
|
On older kernels, this may need to be found from the list of coresight devices,
|
2019-07-12 00:52:01 +08:00
|
|
|
available under ($SYSFS)/bus/coresight/devices/::
|
2019-06-11 02:02:42 +08:00
|
|
|
|
|
|
|
|
root:~# ls /sys/bus/coresight/devices/
|
|
|
|
|
etm0 etm1 etm2 etm3 etm4 etm5 funnel0
|
|
|
|
|
funnel1 funnel2 replicator0 stm0 tmc_etf0 tmc_etr0 tpiu0
|
|
|
|
|
root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program
|
2018-04-18 00:08:06 +08:00
|
|
|
|
2019-06-11 02:02:42 +08:00
|
|
|
As mentioned above in section "Device Naming scheme", the names of the devices could
|
|
|
|
|
look different from what is used in the example above. One must use the device names
|
|
|
|
|
as it appears under the sysFS.
|
2018-04-18 00:08:06 +08:00
|
|
|
|
|
|
|
|
The syntax within the forward slashes '/' is important. The '@' character
|
|
|
|
|
tells the parser that a sink is about to be specified and that this is the sink
|
|
|
|
|
to use for the trace session.
|
|
|
|
|
|
|
|
|
|
More information on the above and other example on how to use Coresight with
|
|
|
|
|
the perf tools can be found in the "HOWTO.md" file of the openCSD gitHub
|
2019-07-12 00:52:01 +08:00
|
|
|
repository [#third]_.
|
2018-04-18 00:08:06 +08:00
|
|
|
|
2018-04-18 00:08:07 +08:00
|
|
|
2.1) AutoFDO analysis using the perf tools:
|
2018-02-14 19:24:41 +08:00
|
|
|
|
|
|
|
|
perf can be used to record and analyze trace of programs.
|
|
|
|
|
|
|
|
|
|
Execution can be recorded using 'perf record' with the cs_etm event,
|
2019-07-12 00:52:01 +08:00
|
|
|
specifying the name of the sink to record to, e.g::
|
2018-02-14 19:24:41 +08:00
|
|
|
|
2019-06-11 02:02:42 +08:00
|
|
|
perf record -e cs_etm/@tmc_etr0/u --per-thread
|
2018-02-14 19:24:41 +08:00
|
|
|
|
|
|
|
|
The 'perf report' and 'perf script' commands can be used to analyze execution,
|
|
|
|
|
synthesizing instruction and branch events from the instruction trace.
|
|
|
|
|
'perf inject' can be used to replace the trace data with the synthesized events.
|
|
|
|
|
The --itrace option controls the type and frequency of synthesized events
|
|
|
|
|
(see perf documentation).
|
|
|
|
|
|
|
|
|
|
Note that only 64-bit programs are currently supported - further work is
|
|
|
|
|
required to support instruction decode of 32-bit Arm programs.
|
|
|
|
|
|
2021-02-12 01:20:38 +08:00
|
|
|
2.2) Tracing PID
|
|
|
|
|
|
|
|
|
|
The kernel can be built to write the PID value into the PE ContextID registers.
|
|
|
|
|
For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may
|
|
|
|
|
implement Arm Virtualization Host Extensions (VHE), which the kernel can
|
|
|
|
|
run at EL2 as a virtualisation host; in this case, the PID value is stored in
|
|
|
|
|
CONTEXTIDR_EL2.
|
|
|
|
|
|
|
|
|
|
perf provides PMU formats that program the ETM to insert these values into the
|
|
|
|
|
trace data; the PMU formats are defined as below:
|
|
|
|
|
|
|
|
|
|
"contextid1": Available on both EL1 kernel and EL2 kernel. When the
|
|
|
|
|
kernel is running at EL1, "contextid1" enables the PID
|
|
|
|
|
tracing; when the kernel is running at EL2, this enables
|
|
|
|
|
tracing the PID of guest applications.
|
|
|
|
|
|
|
|
|
|
"contextid2": Only usable when the kernel is running at EL2. When
|
|
|
|
|
selected, enables PID tracing on EL2 kernel.
|
|
|
|
|
|
|
|
|
|
"contextid": Will be an alias for the option that enables PID
|
|
|
|
|
tracing. I.e,
|
|
|
|
|
contextid == contextid1, on EL1 kernel.
|
|
|
|
|
contextid == contextid2, on EL2 kernel.
|
|
|
|
|
|
|
|
|
|
perf will always enable PID tracing at the relevant EL, this is accomplished by
|
|
|
|
|
automatically enable the "contextid" config - but for EL2 it is possible to make
|
|
|
|
|
specific adjustments using configs "contextid1" and "contextid2", E.g. if a user
|
|
|
|
|
wants to trace PIDs for both host and guest, the two configs "contextid1" and
|
|
|
|
|
"contextid2" can be set at the same time:
|
|
|
|
|
|
|
|
|
|
perf record -e cs_etm/contextid1,contextid2/u -- vm
|
|
|
|
|
|
2018-02-14 19:24:41 +08:00
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Generating coverage files for Feedback Directed Optimization: AutoFDO
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---------------------------------------------------------------------
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'perf inject' accepts the --itrace option in which case tracing data is
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removed and replaced with the synthesized events. e.g.
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2019-07-12 00:52:01 +08:00
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::
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2018-02-14 19:24:41 +08:00
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perf inject --itrace --strip -i perf.data -o perf.data.new
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Below is an example of using ARM ETM for autoFDO. It requires autofdo
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(https://github.com/google/autofdo) and gcc version 5. The bubble
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sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial).
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2019-07-12 00:52:01 +08:00
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::
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2018-02-14 19:24:41 +08:00
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$ gcc-5 -O3 sort.c -o sort
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$ taskset -c 2 ./sort
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Bubble sorting array of 30000 elements
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5910 ms
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2019-06-11 02:02:42 +08:00
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$ perf record -e cs_etm/@tmc_etr0/u --per-thread taskset -c 2 ./sort
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2018-02-14 19:24:41 +08:00
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Bubble sorting array of 30000 elements
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12543 ms
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[ perf record: Woken up 35 times to write data ]
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[ perf record: Captured and wrote 69.640 MB perf.data ]
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$ perf inject -i perf.data -o inj.data --itrace=il64 --strip
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$ create_gcov --binary=./sort --profile=inj.data --gcov=sort.gcov -gcov_version=1
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$ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo
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$ taskset -c 2 ./sort_autofdo
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Bubble sorting array of 30000 elements
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5806 ms
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2018-04-18 00:08:07 +08:00
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How to use the STM module
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-------------------------
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Using the System Trace Macrocell module is the same as the tracers - the only
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difference is that clients are driving the trace capture rather
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than the program flow through the code.
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As with any other CoreSight component, specifics about the STM tracer can be
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2019-07-12 00:52:01 +08:00
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found in sysfs with more information on each entry being found in [#first]_::
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2018-04-18 00:08:07 +08:00
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2019-07-12 00:52:01 +08:00
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root@genericarmv8:~# ls /sys/bus/coresight/devices/stm0
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enable_source hwevent_select port_enable subsystem uevent
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hwevent_enable mgmt port_select traceid
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root@genericarmv8:~#
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2018-04-18 00:08:07 +08:00
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Like any other source a sink needs to be identified and the STM enabled before
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2019-07-12 00:52:01 +08:00
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being used::
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2018-04-18 00:08:07 +08:00
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2019-07-12 00:52:01 +08:00
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root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
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root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/stm0/enable_source
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2018-04-18 00:08:07 +08:00
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From there user space applications can request and use channels using the devfs
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2019-07-12 00:52:01 +08:00
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interface provided for that purpose by the generic STM API::
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root@genericarmv8:~# ls -l /dev/stm0
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crw------- 1 root root 10, 61 Jan 3 18:11 /dev/stm0
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root@genericarmv8:~#
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2019-11-01 01:58:33 +08:00
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Details on how to use the generic STM API can be found here:- :doc:`../stm` [#second]_.
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2018-04-18 00:08:07 +08:00
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2020-03-21 00:53:01 +08:00
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The CTI & CTM Modules
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---------------------
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The CTI (Cross Trigger Interface) provides a set of trigger signals between
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individual CTIs and components, and can propagate these between all CTIs via
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channels on the CTM (Cross Trigger Matrix).
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A separate documentation file is provided to explain the use of these devices.
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(:doc:`coresight-ect`) [#fourth]_.
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2019-07-12 00:52:01 +08:00
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.. [#first] Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
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2018-04-18 00:08:07 +08:00
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2019-07-12 00:52:01 +08:00
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.. [#second] Documentation/trace/stm.rst
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2018-04-18 00:08:07 +08:00
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2019-07-12 00:52:01 +08:00
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.. [#third] https://github.com/Linaro/perf-opencsd
|
2020-03-21 00:53:01 +08:00
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.. [#fourth] Documentation/trace/coresight/coresight-ect.rst
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