2018-08-22 06:02:14 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2015-10-16 17:41:19 +08:00
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/*
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* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2015 Glider bvba
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*
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* Based on clk-rcar-gen3.c
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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2016-06-01 20:54:10 +08:00
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#include <linux/soc/renesas/rcar-rst.h>
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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#include <linux/sys_soc.h>
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2015-10-16 17:41:19 +08:00
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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2016-05-04 20:32:56 +08:00
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#include "rcar-gen3-cpg.h"
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2015-10-16 17:41:19 +08:00
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
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2015-10-16 17:41:19 +08:00
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL3,
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CLK_PLL4,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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CLK_S0,
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CLK_S1,
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CLK_S2,
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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2016-03-30 22:58:19 +08:00
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CLK_RINT,
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2015-10-16 17:41:19 +08:00
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/* Module Clocks */
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MOD_CLK_BASE
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};
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
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2015-10-16 17:41:19 +08:00
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/* External Clock Inputs */
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2016-11-10 20:16:57 +08:00
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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2015-10-16 17:41:19 +08:00
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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2016-08-10 15:29:43 +08:00
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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2015-10-16 17:41:19 +08:00
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2018-07-11 19:28:44 +08:00
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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2018-07-23 21:21:52 +08:00
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2015-10-16 17:41:19 +08:00
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/* Core Clock Outputs */
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2018-01-30 02:01:51 +08:00
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DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
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2018-01-30 02:01:52 +08:00
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DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
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2015-10-16 17:41:19 +08:00
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DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
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DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
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DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
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2015-10-16 17:41:19 +08:00
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DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
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DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
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DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
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2015-10-16 17:41:19 +08:00
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DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
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DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
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DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
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DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
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DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
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DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
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DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
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DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
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2016-01-30 14:33:59 +08:00
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2016-11-10 20:16:57 +08:00
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DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
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DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
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DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
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DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
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2016-01-30 14:33:59 +08:00
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2015-10-16 17:41:19 +08:00
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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2018-05-17 17:04:15 +08:00
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DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
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2015-10-16 17:41:19 +08:00
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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2018-11-21 17:43:16 +08:00
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DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
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2015-10-16 17:41:19 +08:00
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2016-02-26 01:05:25 +08:00
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DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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2016-04-25 19:39:19 +08:00
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DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
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2016-11-10 20:16:57 +08:00
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DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
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2016-03-30 22:58:19 +08:00
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2018-07-11 19:28:44 +08:00
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DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
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2016-03-30 22:58:20 +08:00
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2016-11-10 20:16:57 +08:00
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DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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2015-10-16 17:41:19 +08:00
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};
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
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DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
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DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
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2015-10-16 17:41:19 +08:00
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DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
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DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
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DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
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DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
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DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
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DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
|
|
|
|
|
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
|
|
|
|
|
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
|
2018-05-24 22:19:09 +08:00
|
|
|
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
|
2016-09-09 19:43:10 +08:00
|
|
|
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
|
|
|
|
|
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
|
|
|
|
|
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
|
|
|
|
|
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
|
2016-01-30 14:33:59 +08:00
|
|
|
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
|
|
|
|
|
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
|
|
|
|
|
DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
|
|
|
|
|
DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
|
|
|
|
|
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
|
2017-04-20 01:46:24 +08:00
|
|
|
DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
|
2016-01-22 18:02:29 +08:00
|
|
|
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
|
2017-04-20 01:46:24 +08:00
|
|
|
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
|
2016-02-01 19:29:05 +08:00
|
|
|
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
|
|
|
|
|
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
|
2017-03-01 00:17:31 +08:00
|
|
|
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
|
2016-02-18 15:14:03 +08:00
|
|
|
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
|
2017-10-10 19:04:28 +08:00
|
|
|
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
|
|
|
|
|
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
|
2016-06-17 20:25:14 +08:00
|
|
|
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
|
|
|
|
|
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
|
|
|
|
|
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
|
|
|
|
|
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
|
|
|
|
|
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
|
2016-06-19 10:34:18 +08:00
|
|
|
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
|
2017-05-08 17:43:49 +08:00
|
|
|
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
|
|
|
|
|
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
|
|
|
|
|
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
|
2017-04-20 01:46:23 +08:00
|
|
|
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
|
2017-04-20 01:46:25 +08:00
|
|
|
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
|
2016-04-25 19:39:19 +08:00
|
|
|
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
|
|
|
|
|
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
|
|
|
|
|
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
|
|
|
|
|
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
|
|
|
|
|
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
|
|
|
|
|
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
|
2016-06-10 15:36:44 +08:00
|
|
|
DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
|
|
|
|
|
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
|
2015-12-24 18:14:18 +08:00
|
|
|
DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
|
|
|
|
|
DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
|
2017-05-08 17:43:49 +08:00
|
|
|
DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4),
|
2016-02-26 01:05:26 +08:00
|
|
|
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
|
2016-02-26 01:05:24 +08:00
|
|
|
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
|
2017-05-08 17:43:49 +08:00
|
|
|
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
|
|
|
|
|
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
|
2016-05-23 10:05:42 +08:00
|
|
|
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
|
2017-05-08 17:43:49 +08:00
|
|
|
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
|
|
|
|
|
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
|
2015-10-16 17:41:19 +08:00
|
|
|
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
|
|
|
|
|
DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
|
|
|
|
DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
|
|
|
|
|
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
|
|
|
|
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
|
|
|
|
|
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CPG Clock Data
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
2018-07-11 19:28:44 +08:00
|
|
|
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
2015-10-16 17:41:19 +08:00
|
|
|
* 14 13 19 17 (MHz)
|
2018-07-11 19:28:44 +08:00
|
|
|
*-------------------------------------------------------------------------
|
|
|
|
|
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
|
|
|
|
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
2015-10-16 17:41:19 +08:00
|
|
|
* 0 0 1 0 Prohibited setting
|
2018-07-11 19:28:44 +08:00
|
|
|
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
|
|
|
|
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
|
|
|
|
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
2015-10-16 17:41:19 +08:00
|
|
|
* 0 1 1 0 Prohibited setting
|
2018-07-11 19:28:44 +08:00
|
|
|
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
|
|
|
|
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
|
|
|
|
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
2015-10-16 17:41:19 +08:00
|
|
|
* 1 0 1 0 Prohibited setting
|
2018-07-11 19:28:44 +08:00
|
|
|
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
|
|
|
|
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
|
|
|
|
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
2015-10-16 17:41:19 +08:00
|
|
|
* 1 1 1 0 Prohibited setting
|
2018-07-11 19:28:44 +08:00
|
|
|
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
2015-10-16 17:41:19 +08:00
|
|
|
*/
|
|
|
|
|
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
|
|
|
|
(((md) & BIT(13)) >> 11) | \
|
|
|
|
|
(((md) & BIT(19)) >> 18) | \
|
|
|
|
|
(((md) & BIT(17)) >> 17))
|
|
|
|
|
|
2016-05-04 20:32:56 +08:00
|
|
|
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
2018-07-11 19:28:44 +08:00
|
|
|
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
|
|
|
|
{ 1, 192, 1, 192, 1, 16, },
|
|
|
|
|
{ 1, 192, 1, 128, 1, 16, },
|
|
|
|
|
{ 0, /* Prohibited setting */ },
|
|
|
|
|
{ 1, 192, 1, 192, 1, 16, },
|
|
|
|
|
{ 1, 160, 1, 160, 1, 19, },
|
|
|
|
|
{ 1, 160, 1, 106, 1, 19, },
|
|
|
|
|
{ 0, /* Prohibited setting */ },
|
|
|
|
|
{ 1, 160, 1, 160, 1, 19, },
|
|
|
|
|
{ 1, 128, 1, 128, 1, 24, },
|
|
|
|
|
{ 1, 128, 1, 84, 1, 24, },
|
|
|
|
|
{ 0, /* Prohibited setting */ },
|
|
|
|
|
{ 1, 128, 1, 128, 1, 24, },
|
|
|
|
|
{ 2, 192, 1, 192, 1, 32, },
|
|
|
|
|
{ 2, 192, 1, 128, 1, 32, },
|
|
|
|
|
{ 0, /* Prohibited setting */ },
|
|
|
|
|
{ 2, 192, 1, 192, 1, 32, },
|
2015-10-16 17:41:19 +08:00
|
|
|
};
|
|
|
|
|
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
static const struct soc_device_attribute r8a7795es1[] __initconst = {
|
|
|
|
|
{ .soc_id = "r8a7795", .revision = "ES1.*" },
|
|
|
|
|
{ /* sentinel */ }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Fixups for R-Car H3 ES1.x
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
|
|
|
|
|
MOD_CLK_ID(326), /* USB-DMAC3-0 */
|
|
|
|
|
MOD_CLK_ID(329), /* USB-DMAC3-1 */
|
|
|
|
|
MOD_CLK_ID(700), /* EHCI/OHCI3 */
|
|
|
|
|
MOD_CLK_ID(705), /* HS-USB-IF3 */
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
|
|
|
|
|
{ MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */
|
|
|
|
|
{ MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */
|
|
|
|
|
{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
|
|
|
|
|
{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
|
|
|
|
|
{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
|
2017-10-10 19:04:28 +08:00
|
|
|
{ MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
|
|
|
|
|
{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
|
2017-05-08 17:43:49 +08:00
|
|
|
{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
{ MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
|
|
|
|
|
{ MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
|
|
|
|
|
{ MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
|
|
|
|
|
{ MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */
|
|
|
|
|
{ MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */
|
|
|
|
|
{ MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */
|
|
|
|
|
{ MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */
|
|
|
|
|
{ MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */
|
|
|
|
|
{ MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */
|
|
|
|
|
{ MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */
|
|
|
|
|
{ MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */
|
|
|
|
|
{ MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
|
|
|
|
|
{ MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */
|
|
|
|
|
{ MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */
|
|
|
|
|
{ MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */
|
|
|
|
|
{ MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */
|
|
|
|
|
{ MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */
|
|
|
|
|
{ MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */
|
|
|
|
|
{ MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */
|
|
|
|
|
{ MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */
|
|
|
|
|
{ MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */
|
|
|
|
|
{ MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */
|
|
|
|
|
{ MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */
|
|
|
|
|
{ MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */
|
|
|
|
|
{ MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */
|
|
|
|
|
{ MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */
|
|
|
|
|
{ MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */
|
|
|
|
|
{ MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
|
|
|
|
|
{ MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
|
|
|
|
|
{ MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
|
2017-05-08 17:43:49 +08:00
|
|
|
{ MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
|
|
|
|
|
{ MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
|
|
|
|
|
{ MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
|
|
|
|
|
{ MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
|
|
|
|
|
{ MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
|
|
|
|
|
{ MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
|
|
|
|
|
{ MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
|
|
|
|
|
{ MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
|
|
|
|
|
{ MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
|
|
|
|
|
{ MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
|
|
|
|
|
{ MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
|
|
|
|
|
{ MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
|
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Fixups for R-Car H3 ES2.x
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
|
|
|
|
|
MOD_CLK_ID(117), /* FDP1-2 */
|
|
|
|
|
MOD_CLK_ID(327), /* USB3-IF1 */
|
|
|
|
|
MOD_CLK_ID(600), /* FCPVD3 */
|
|
|
|
|
MOD_CLK_ID(609), /* FCPVI2 */
|
|
|
|
|
MOD_CLK_ID(613), /* FCPF2 */
|
|
|
|
|
MOD_CLK_ID(616), /* FCPCI1 */
|
|
|
|
|
MOD_CLK_ID(617), /* FCPCI0 */
|
|
|
|
|
MOD_CLK_ID(620), /* VSPD3 */
|
|
|
|
|
MOD_CLK_ID(629), /* VSPI2 */
|
|
|
|
|
MOD_CLK_ID(713), /* CSI21 */
|
|
|
|
|
};
|
|
|
|
|
|
2015-10-16 17:41:19 +08:00
|
|
|
static int __init r8a7795_cpg_mssr_init(struct device *dev)
|
|
|
|
|
{
|
2016-05-04 20:32:56 +08:00
|
|
|
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
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2016-06-01 20:54:10 +08:00
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u32 cpg_mode;
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int error;
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error = rcar_rst_read_mode_pins(&cpg_mode);
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if (error)
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return error;
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2015-10-16 17:41:19 +08:00
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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if (!cpg_pll_config->extal_div) {
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dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
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return -EINVAL;
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}
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clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
The Clock Pulse Generator / Module Standby and Software Reset module in
R-Car H3 ES2.0 differs from ES1.x in the following areas:
- More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
- Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
SYS-DMAC, VIN, VSPB, VSPI,
- Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
USB3-IF1, VSPD3, VSPI2,
- Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
The goal is twofold:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
This is achieved by:
- Updating the clock tables for the latest revision (ES2.0), but not
removing clocks that only exist on earlier revisions (ES1.x),
- Detecting the SoC revision at runtime using the new soc_device_match()
API, and fixing up the clocks tables to match the actual SoC
revision, by:
- NULLifying core and module clocks of modules that do not exist,
- Reparenting module clocks that have a different parent on ES1.x.
Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-29 20:36:11 +08:00
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if (soc_device_match(r8a7795es1)) {
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cpg_core_nullify_range(r8a7795_core_clks,
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ARRAY_SIZE(r8a7795_core_clks),
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R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
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mssr_mod_nullify(r8a7795_mod_clks,
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ARRAY_SIZE(r8a7795_mod_clks),
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r8a7795es1_mod_nullify,
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ARRAY_SIZE(r8a7795es1_mod_nullify));
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mssr_mod_reparent(r8a7795_mod_clks,
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ARRAY_SIZE(r8a7795_mod_clks),
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r8a7795es1_mod_reparent,
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ARRAY_SIZE(r8a7795es1_mod_reparent));
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} else {
|
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mssr_mod_nullify(r8a7795_mod_clks,
|
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ARRAY_SIZE(r8a7795_mod_clks),
|
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r8a7795es2_mod_nullify,
|
|
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|
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ARRAY_SIZE(r8a7795es2_mod_nullify));
|
|
|
|
|
}
|
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|
|
|
2017-03-10 18:36:33 +08:00
|
|
|
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
2015-10-16 17:41:19 +08:00
|
|
|
}
|
|
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|
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|
|
|
|
|
const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
|
|
|
|
|
/* Core Clocks */
|
|
|
|
|
.core_clks = r8a7795_core_clks,
|
|
|
|
|
.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
|
|
|
|
|
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
|
|
|
|
.num_total_core_clks = MOD_CLK_BASE,
|
|
|
|
|
|
|
|
|
|
/* Module Clocks */
|
|
|
|
|
.mod_clks = r8a7795_mod_clks,
|
|
|
|
|
.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
|
|
|
|
|
.num_hw_mod_clks = 12 * 32,
|
|
|
|
|
|
|
|
|
|
/* Critical Module Clocks */
|
|
|
|
|
.crit_mod_clks = r8a7795_crit_mod_clks,
|
|
|
|
|
.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
|
|
|
|
|
|
|
|
|
|
/* Callbacks */
|
|
|
|
|
.init = r8a7795_cpg_mssr_init,
|
2016-05-04 20:32:56 +08:00
|
|
|
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
2015-10-16 17:41:19 +08:00
|
|
|
};
|