2019-05-19 20:07:45 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2006-05-24 08:18:44 +08:00
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#
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# DMA engine configuration
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#
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2007-10-16 16:27:42 +08:00
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menuconfig DMADEVICES
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2007-11-29 08:21:43 +08:00
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bool "DMA Engine support"
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2009-06-04 05:22:28 +08:00
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depends on HAS_DMA
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2007-10-16 16:27:42 +08:00
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help
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2007-11-29 08:21:43 +08:00
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DMA engines can do asynchronous data transfers without
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involving the host CPU. Currently, this framework can be
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used to offload memory copies in the network stack and
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2008-06-27 16:21:11 +08:00
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RAID operations in the MD driver. This menu only presents
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DMA Device drivers supported by the configured arch, it may
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be empty in some cases.
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2007-10-16 16:27:42 +08:00
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2010-02-10 05:34:54 +08:00
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config DMADEVICES_DEBUG
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2019-11-21 11:19:08 +08:00
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bool "DMA Engine debugging"
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depends on DMADEVICES != n
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help
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This is an option for use by developers; most people should
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say N here. This enables DMA engine core and driver debugging.
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2010-02-10 05:34:54 +08:00
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config DMADEVICES_VDEBUG
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2019-11-21 11:19:08 +08:00
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bool "DMA Engine verbose debugging"
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depends on DMADEVICES_DEBUG != n
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help
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This is an option for use by developers; most people should
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say N here. This enables deeper (more verbose) debugging of
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the DMA engine core and drivers.
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2010-02-10 05:34:54 +08:00
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2007-10-16 16:27:42 +08:00
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if DMADEVICES
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comment "DMA Devices"
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2015-08-24 16:13:14 +08:00
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#core
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config ASYNC_TX_ENABLE_CHANNEL_SWITCH
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bool
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2014-07-12 05:04:21 +08:00
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2015-08-24 16:13:14 +08:00
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config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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bool
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2014-07-12 05:04:21 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_ENGINE
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2009-09-09 08:42:51 +08:00
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bool
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2015-08-24 16:13:14 +08:00
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config DMA_VIRTUAL_CHANNELS
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tristate
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config DMA_ACPI
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def_bool y
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depends on ACPI
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config DMA_OF
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def_bool y
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depends on OF
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select DMA_ENGINE
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#devices
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2017-07-07 20:11:19 +08:00
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config ALTERA_MSGDMA
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tristate "Altera / Intel mSGDMA Engine"
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2021-05-22 10:13:10 +08:00
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depends on HAS_IOMEM
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2017-07-07 20:11:19 +08:00
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select DMA_ENGINE
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help
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Enable support for Altera / Intel mSGDMA controller.
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2010-09-28 21:57:37 +08:00
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config AMBA_PL08X
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bool "ARM PrimeCell PL080 or PL081 support"
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2012-10-24 04:01:54 +08:00
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depends on ARM_AMBA
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2010-09-28 21:57:37 +08:00
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select DMA_ENGINE
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2012-05-26 21:09:53 +08:00
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select DMA_VIRTUAL_CHANNELS
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2010-09-28 21:57:37 +08:00
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help
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2017-05-21 05:42:53 +08:00
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Say yes if your platform has a PL08x DMAC device which can
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provide DMA engine support. This includes the original ARM
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PL080 and PL081, Samsungs PL080 derivative and Faraday
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Technology's FTDMAC020 PL080 derivative.
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2010-09-28 21:57:37 +08:00
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2015-08-24 16:13:14 +08:00
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config AMCC_PPC440SPE_ADMA
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tristate "AMCC PPC440SPe ADMA support"
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depends on 440SPe || 440SP
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2007-10-16 16:27:42 +08:00
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select DMA_ENGINE
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2013-12-10 02:33:16 +08:00
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select DMA_ENGINE_RAID
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2015-08-24 16:13:14 +08:00
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select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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2010-10-08 07:44:50 +08:00
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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2007-10-16 16:27:42 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Enable support for the AMCC PPC440SPe RAID engines.
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2007-10-16 16:27:42 +08:00
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2022-06-01 05:36:14 +08:00
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config APPLE_ADMAC
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tristate "Apple ADMAC support"
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depends on ARCH_APPLE || COMPILE_TEST
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select DMA_ENGINE
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default ARCH_APPLE
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help
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Enable support for Audio DMA Controller found on Apple Silicon SoCs.
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2009-07-04 01:24:33 +08:00
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config AT_HDMAC
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tristate "Atmel AHB DMA support"
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2012-03-15 18:31:58 +08:00
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depends on ARCH_AT91
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2009-07-04 01:24:33 +08:00
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select DMA_ENGINE
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2022-10-25 17:03:06 +08:00
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select DMA_VIRTUAL_CHANNELS
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2009-07-04 01:24:33 +08:00
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help
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2012-03-15 18:31:58 +08:00
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Support the Atmel AHB DMA controller.
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2007-10-16 16:27:42 +08:00
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2014-10-22 23:22:18 +08:00
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config AT_XDMAC
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tristate "Atmel XDMA support"
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2014-11-13 18:52:39 +08:00
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depends on ARCH_AT91
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2014-10-22 23:22:18 +08:00
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select DMA_ENGINE
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help
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Support the Atmel XDMA controller.
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2007-10-16 16:27:42 +08:00
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2015-08-24 16:13:14 +08:00
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config AXI_DMAC
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tristate "Analog Devices AXI-DMAC DMA support"
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2021-03-11 23:27:31 +08:00
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depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || COMPILE_TEST
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2007-10-16 16:27:42 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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2019-06-06 18:45:50 +08:00
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select REGMAP_MMIO
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2007-10-16 16:27:42 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
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2020-04-16 18:30:54 +08:00
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controller is often used in Analog Devices' reference designs for FPGA
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2015-08-24 16:13:14 +08:00
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platforms.
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2006-05-24 08:18:44 +08:00
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2017-05-15 13:04:54 +08:00
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config BCM_SBA_RAID
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tristate "Broadcom SBA RAID engine support"
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2017-05-18 21:25:25 +08:00
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depends on ARM64 || COMPILE_TEST
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depends on MAILBOX && RAID6_PQ
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2017-05-15 13:04:54 +08:00
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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select ASYNC_TX_DISABLE_XOR_VAL_DMA
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select ASYNC_TX_DISABLE_PQ_VAL_DMA
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2017-10-03 13:23:00 +08:00
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default m if ARCH_BCM_IPROC
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2017-05-15 13:04:54 +08:00
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help
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Enable support for Broadcom SBA RAID Engine. The SBA RAID
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engine is available on most of the Broadcom iProc SoCs. It
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has the capability to offload memcpy, xor and pq computation
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for raid5/6.
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2015-08-24 16:13:14 +08:00
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config DMA_BCM2835
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tristate "BCM2835 DMA engine support"
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depends on ARCH_BCM2835
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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config DMA_JZ4780
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tristate "JZ4780 DMA support"
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2018-08-30 05:32:48 +08:00
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depends on MIPS || COMPILE_TEST
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2015-07-27 23:04:02 +08:00
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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2015-08-24 16:13:14 +08:00
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This selects support for the DMA controller in Ingenic JZ4780 SoCs.
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If you have a board based on such a SoC and wish to use DMA for
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devices which can use the DMA controller, say Y or M here.
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2015-07-27 23:04:02 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_SA11X0
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tristate "SA-11x0 DMA support"
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2016-09-02 18:01:42 +08:00
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depends on ARCH_SA1100 || COMPILE_TEST
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2009-07-04 01:24:33 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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2009-07-04 01:24:33 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Support the DMA engine found on Intel StrongARM SA-1100 and
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SA-1110 SoCs. This DMA engine can only be used with on-chip
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devices.
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2009-07-04 01:24:33 +08:00
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2015-08-24 16:13:14 +08:00
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config DMA_SUN4I
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tristate "Allwinner A10 DMA SoCs support"
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2015-09-05 02:10:18 +08:00
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depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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2015-08-24 16:13:14 +08:00
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default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
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2014-10-22 23:22:18 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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2014-10-22 23:22:18 +08:00
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help
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2015-08-24 16:13:14 +08:00
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Enable support for the DMA controller present in the sun4i,
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sun5i and sun7i Allwinner ARM SoCs.
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config DMA_SUN6I
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tristate "Allwinner A31 SoCs DMA support"
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2022-04-25 01:27:58 +08:00
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depends on ARCH_SUNXI || COMPILE_TEST
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2015-08-24 16:13:14 +08:00
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depends on RESET_CONTROLLER
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support for the DMA engine first found in Allwinner A31 SoCs.
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2018-03-06 19:46:14 +08:00
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config DW_AXI_DMAC
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tristate "Synopsys DesignWare AXI DMA support"
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2022-08-04 04:34:48 +08:00
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depends on OF
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2021-01-25 09:32:50 +08:00
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depends on HAS_IOMEM
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2018-03-06 19:46:14 +08:00
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for Synopsys DesignWare AXI DMA controller.
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NOTE: This driver wasn't tested on 64 bit platform because
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of lack 64 bit platform with Synopsys DW AXI DMAC.
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2015-08-24 16:13:14 +08:00
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config EP93XX_DMA
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bool "Cirrus Logic EP93xx DMA support"
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2016-09-02 18:08:43 +08:00
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depends on ARCH_EP93XX || COMPILE_TEST
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2015-08-24 16:13:14 +08:00
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select DMA_ENGINE
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help
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Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
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2014-10-22 23:22:18 +08:00
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2008-03-01 22:42:48 +08:00
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config FSL_DMA
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2013-09-26 17:33:43 +08:00
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tristate "Freescale Elo series DMA support"
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2008-09-27 08:00:11 +08:00
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depends on FSL_SOC
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2008-03-01 22:42:48 +08:00
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select DMA_ENGINE
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2010-10-08 07:44:50 +08:00
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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2020-06-14 00:50:22 +08:00
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help
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2013-09-26 17:33:43 +08:00
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Enable support for the Freescale Elo series DMA controllers.
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The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
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EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
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some Txxx and Bxxx parts.
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2008-03-01 22:42:48 +08:00
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2015-08-24 16:13:14 +08:00
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config FSL_EDMA
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tristate "Freescale eDMA engine support"
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depends on OF
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support the Freescale eDMA engine with programmable channel
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multiplexing capability for DMA request sources(slot).
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This module can be found on Freescale Vybrid and LS-1 SoCs.
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2018-10-30 10:36:00 +08:00
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config FSL_QDMA
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2019-11-21 11:19:08 +08:00
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tristate "NXP Layerscape qDMA engine support"
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depends on ARM || ARM64
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select DMA_ENGINE_RAID
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select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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help
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Support the NXP Layerscape qDMA engine with command queue and legacy mode.
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Channel virtualization is supported through enqueuing of DMA jobs to,
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or dequeuing DMA jobs from, different work queues.
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This module can be found on NXP Layerscape SoCs.
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2018-10-30 10:36:00 +08:00
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The qdma driver only work on SoCs with a DPAA hardware block.
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2015-03-03 14:26:22 +08:00
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config FSL_RAID
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2019-11-21 11:19:08 +08:00
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tristate "Freescale RAID engine Support"
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depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
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select DMA_ENGINE
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select DMA_ENGINE_RAID
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2020-06-14 00:50:22 +08:00
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help
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2019-11-21 11:19:08 +08:00
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Enable support for Freescale RAID Engine. RAID Engine is
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available on some QorIQ SoCs (like P5020/P5040). It has
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the capability to offload memcpy, xor and pq computation
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2015-03-03 14:26:22 +08:00
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for raid5/6.
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2020-01-16 14:10:57 +08:00
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config HISI_DMA
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tristate "HiSilicon DMA Engine support"
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2022-11-21 23:23:53 +08:00
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depends on ARCH_HISI || COMPILE_TEST
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2020-03-28 19:41:33 +08:00
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depends on PCI_MSI
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2020-01-16 14:10:57 +08:00
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support HiSilicon Kunpeng DMA engine.
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2015-08-24 16:13:14 +08:00
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config IMG_MDC_DMA
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tristate "IMG MDC support"
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depends on MIPS || COMPILE_TEST
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depends on MFD_SYSCON
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2010-02-05 11:42:52 +08:00
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select DMA_ENGINE
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2015-08-24 16:13:14 +08:00
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for the IMG multi-threaded DMA controller (MDC).
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2012-10-12 23:52:45 +08:00
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2015-08-24 16:13:14 +08:00
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config IMX_DMA
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tristate "i.MX DMA support"
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2011-08-24 14:41:09 +08:00
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depends on ARCH_MXC
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2008-07-09 02:58:36 +08:00
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select DMA_ENGINE
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i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the i.MX DMA engine. This engine is integrated into
|
|
|
|
|
Freescale i.MX1/21/27 chips.
|
2008-07-09 02:58:36 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config IMX_SDMA
|
|
|
|
|
tristate "i.MX SDMA support"
|
2011-08-24 14:41:09 +08:00
|
|
|
depends on ARCH_MXC
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
select DMA_ENGINE
|
2018-06-20 00:57:00 +08:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the i.MX SDMA engine. This engine is integrated into
|
|
|
|
|
Freescale i.MX25/31/35/51/53/6 chips.
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
|
2015-09-22 00:48:45 +08:00
|
|
|
config INTEL_IDMA64
|
2015-09-05 02:10:18 +08:00
|
|
|
tristate "Intel integrated DMA 64-bit support"
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
help
|
2015-09-05 02:10:18 +08:00
|
|
|
Enable DMA support for Intel Low Power Subsystem such as found on
|
|
|
|
|
Intel Skylake PCH.
|
i.MX31: Image Processing Unit DMA and IRQ drivers
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.
IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20 06:36:21 +08:00
|
|
|
|
2021-07-16 02:44:41 +08:00
|
|
|
config INTEL_IDXD_BUS
|
|
|
|
|
tristate
|
|
|
|
|
default INTEL_IDXD
|
|
|
|
|
|
2020-01-22 07:43:59 +08:00
|
|
|
config INTEL_IDXD
|
|
|
|
|
tristate "Intel Data Accelerators support"
|
2021-06-25 16:38:10 +08:00
|
|
|
depends on PCI && X86_64 && !UML
|
2020-07-14 14:35:39 +08:00
|
|
|
depends on PCI_MSI
|
2021-08-20 00:34:06 +08:00
|
|
|
depends on PCI_PASID
|
2020-06-16 04:54:26 +08:00
|
|
|
depends on SBITMAP
|
2020-01-22 07:43:59 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Intel(R) data accelerators present
|
|
|
|
|
in Intel Xeon CPU.
|
|
|
|
|
|
|
|
|
|
Say Y if you have such a platform.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2021-07-16 02:44:47 +08:00
|
|
|
config INTEL_IDXD_COMPAT
|
|
|
|
|
bool "Legacy behavior for idxd driver"
|
|
|
|
|
depends on PCI && X86_64
|
|
|
|
|
select INTEL_IDXD_BUS
|
|
|
|
|
help
|
|
|
|
|
Compatible driver to support old /sys/bus/dsa/drivers/dsa behavior.
|
|
|
|
|
The old behavior performed driver bind/unbind for device and wq
|
|
|
|
|
devices all under the dsa driver. The compat driver will emulate
|
|
|
|
|
the legacy behavior in order to allow existing support apps (i.e.
|
|
|
|
|
accel-config) to continue function. It is expected that accel-config
|
|
|
|
|
v3.2 and earlier will need the compat mode. A distro with later
|
|
|
|
|
accel-config version can disable this compat config.
|
|
|
|
|
|
|
|
|
|
Say Y if you have old applications that require such behavior.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2020-10-28 01:34:35 +08:00
|
|
|
# Config symbol that collects all the dependencies that's necessary to
|
|
|
|
|
# support shared virtual memory for the devices supported by idxd.
|
|
|
|
|
config INTEL_IDXD_SVM
|
|
|
|
|
bool "Accelerator Shared Virtual Memory Support"
|
|
|
|
|
depends on INTEL_IDXD
|
|
|
|
|
depends on INTEL_IOMMU_SVM
|
|
|
|
|
depends on PCI_PRI
|
|
|
|
|
depends on PCI_PASID
|
|
|
|
|
depends on PCI_IOV
|
|
|
|
|
|
dmaengine: idxd: Add IDXD performance monitor support
Implement the IDXD performance monitor capability (named 'perfmon' in
the DSA (Data Streaming Accelerator) spec [1]), which supports the
collection of information about key events occurring during DSA and
IAX (Intel Analytics Accelerator) device execution, to assist in
performance tuning and debugging.
The idxd perfmon support is implemented as part of the IDXD driver and
interfaces with the Linux perf framework. It has several features in
common with the existing uncore pmu support:
- it does not support sampling
- does not support per-thread counting
However it also has some unique features not present in the core and
uncore support:
- all general-purpose counters are identical, thus no event constraints
- operation is always system-wide
While the core perf subsystem assumes that all counters are by default
per-cpu, the uncore pmus are socket-scoped and use a cpu mask to
restrict counting to one cpu from each socket. IDXD counters use a
similar strategy but expand the scope even further; since IDXD
counters are system-wide and can be read from any cpu, the IDXD perf
driver picks a single cpu to do the work (with cpu hotplug notifiers
to choose a different cpu if the chosen one is taken off-line).
More specifically, the perf userspace tool by default opens a counter
for each cpu for an event. However, if it finds a cpumask file
associated with the pmu under sysfs, as is the case with the uncore
pmus, it will open counters only on the cpus specified by the cpumask.
Since perfmon only needs to open a single counter per event for a
given IDXD device, the perfmon driver will create a sysfs cpumask file
for the device and insert the first cpu of the system into it. When a
user uses perf to open an event, perf will open a single counter on
the cpu specified by the cpu mask. This amounts to the default
system-wide rather than per-cpu counting mentioned previously for
perfmon pmu events. In order to keep the cpu mask up-to-date, the
driver implements cpu hotplug support for multiple devices, as IDXD
usually enumerates and registers more than one idxd device.
The perfmon driver implements basic perfmon hardware capability
discovery and configuration, and is initialized by the IDXD driver's
probe function. During initialization, the driver retrieves the total
number of supported performance counters, the pmu ID, and the device
type from idxd device, and registers itself under the Linux perf
framework.
The perf userspace tool can be used to monitor single or multiple
events depending on the given configuration, as well as event groups,
which are also supported by the perfmon driver. The user configures
events using the perf tool command-line interface by specifying the
event and corresponding event category, along with an optional set of
filters that can be used to restrict counting to specific work queues,
traffic classes, page and transfer sizes, and engines (See [1] for
specifics).
With the configuration specified by the user, the perf tool issues a
system call passing that information to the kernel, which uses it to
initialize the specified event(s). The event(s) are opened and
started, and following termination of the perf command, they're
stopped. At that point, the perfmon driver will read the latest count
for the event(s), calculate the difference between the latest counter
values and previously tracked counter values, and display the final
incremental count as the event count for the cycle. An overflow
handler registered on the IDXD irq path is used to account for counter
overflows, which are signaled by an overflow interrupt.
Below are a couple of examples of perf usage for monitoring DSA events.
The following monitors all events in the 'engine' category. Becuuse
no filters are specified, this captures all engine events for the
workload, which in this case is 19 iterations of the work generated by
the kernel dmatest module.
Details describing the events can be found in Appendix D of [1],
Performance Monitoring Events, but briefly they are:
event 0x1: total input data processed, in 32-byte units
event 0x2: total data written, in 32-byte units
event 0x4: number of work descriptors that read the source
event 0x8: number of work descriptors that write the destination
event 0x10: number of work descriptors dispatched from batch descriptors
event 0x20: number of work descriptors dispatched from work queues
# perf stat -e dsa0/event=0x1,event_category=0x1/,
dsa0/event=0x2,event_category=0x1/,
dsa0/event=0x4,event_category=0x1/,
dsa0/event=0x8,event_category=0x1/,
dsa0/event=0x10,event_category=0x1/,
dsa0/event=0x20,event_category=0x1/
modprobe dmatest channel=dma0chan0 timeout=2000
iterations=19 run=1 wait=1
Performance counter stats for 'system wide':
5,332 dsa0/event=0x1,event_category=0x1/
5,327 dsa0/event=0x2,event_category=0x1/
19 dsa0/event=0x4,event_category=0x1/
19 dsa0/event=0x8,event_category=0x1/
0 dsa0/event=0x10,event_category=0x1/
19 dsa0/event=0x20,event_category=0x1/
21.977436186 seconds time elapsed
The command below illustrates filter usage with a simple example. It
specifies that MEM_MOVE operations should be counted for the DSA
device dsa0 (event 0x8 corresponds to the EV_MEM_MOVE event - Number
of Memory Move Descriptors, which is part of event category 0x3 -
Operations. The detailed category and event IDs are available in
Appendix D, Performance Monitoring Events, of [1]). In addition to
the event and event category, a number of filters are also specified
(the detailed filter values are available in Chapter 6.4 (Filter
Support) of [1]), which will restrict counting to only those events
that meet all of the filter criteria. In this case, the filters
specify that only MEM_MOVE operations that are serviced by work queue
wq0 and specifically engine number engine0 and traffic class tc0
having sizes between 0 and 4k and page size of between 0 and 1G result
in a counter hit; anything else will be filtered out and not appear in
the final count. Note that filters are optional - any filter not
specified is assumed to be all ones and will pass anything.
# perf stat -e dsa0/filter_wq=0x1,filter_tc=0x1,filter_sz=0x7,
filter_eng=0x1,event=0x8,event_category=0x3/
modprobe dmatest channel=dma0chan0 timeout=2000
iterations=19 run=1 wait=1
Performance counter stats for 'system wide':
19 dsa0/filter_wq=0x1,filter_tc=0x1,filter_sz=0x7,
filter_eng=0x1,event=0x8,event_category=0x3/
21.865914091 seconds time elapsed
The output above reflects that the unspecified workload resulted in
the counting of 19 MEM_MOVE operation events that met the filter
criteria.
[1]: https://software.intel.com/content/www/us/en/develop/download/intel-data-streaming-accelerator-preliminary-architecture-specification.html
[ Based on work originally by Jing Lin. ]
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Tom Zanussi <tom.zanussi@linux.intel.com>
Link: https://lore.kernel.org/r/0c5080a7d541904c4ad42b848c76a1ce056ddac7.1619276133.git.zanussi@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-04-24 23:04:15 +08:00
|
|
|
config INTEL_IDXD_PERFMON
|
|
|
|
|
bool "Intel Data Accelerators performance monitor support"
|
|
|
|
|
depends on INTEL_IDXD
|
|
|
|
|
help
|
|
|
|
|
Enable performance monitor (pmu) support for the Intel(R)
|
|
|
|
|
data accelerators present in Intel Xeon CPU. With this
|
|
|
|
|
enabled, perf can be used to monitor the DSA (Intel Data
|
|
|
|
|
Streaming Accelerator) events described in the Intel DSA
|
|
|
|
|
spec.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config INTEL_IOATDMA
|
|
|
|
|
tristate "Intel I/OAT DMA support"
|
2021-08-09 17:24:09 +08:00
|
|
|
depends on PCI && X86_64 && !UML
|
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 05:29:20 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select DCA
|
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 05:29:20 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the Intel(R) I/OAT DMA engine present
|
|
|
|
|
in recent Intel Xeon chipsets.
|
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal
structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware
descriptors but linked list information
The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
dma pool allocated memory. This changes completely the way descriptors are
handled
- the architecture behind the interrupt/tasklet management was rewritten to be
more conforming to virt-dma
- the buffers alignment is handled differently
The former driver assumed that the DMA channel stopped between each
descriptor. The new one chains descriptors to let the channel running. This
is a necessary guarantee for real-time high bandwidth usecases such as video
capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining
Whenever possible, submitting a descriptor "hot chains" it to a running
channel. There is still no guarantee that the descriptor will be issued, as
the channel might be stopped just before the descriptor is submitted. Yet
this allows to submit several video buffers, and resubmit a buffer while
another is under handling.
As before, dma_async_issue_pending() is the only guarantee to have all the
buffers issued.
When an alignment issue is detected (ie. one address in a descriptor is not
a multiple of 8), if the already running channel is in "aligned mode", the
channel will stop, and restarted in "misaligned mode" to finished the issued
list.
- descriptors reusing
A submitted, issued and completed descriptor can be reused, ie resubmitted if
it was prepared with the proper flag (DMA_PREP_ACK). Only a channel
resources release will in this case release that buffer.
This allows a rolling ring of buffers to be reused, where there are several
thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced :
- debugging traces
- lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-05-26 05:29:20 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
Say Y here if you have such a chipset.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config K3_DMA
|
|
|
|
|
tristate "Hisilicon K3 DMA support"
|
2016-08-30 01:30:53 +08:00
|
|
|
depends on ARCH_HI3xxx || ARCH_HISI || COMPILE_TEST
|
2013-10-08 05:42:10 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the DMA engine for Hisilicon K3 platform
|
|
|
|
|
devices.
|
2013-10-08 05:42:10 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config LPC18XX_DMAMUX
|
|
|
|
|
bool "NXP LPC18xx/43xx DMA MUX for PL080"
|
|
|
|
|
depends on ARCH_LPC18XX || COMPILE_TEST
|
|
|
|
|
depends on OF && AMBA_PL08X
|
|
|
|
|
select MFD_SYSCON
|
|
|
|
|
help
|
|
|
|
|
Enable support for DMA on NXP LPC18xx/43xx platforms
|
|
|
|
|
with PL080 and multiplexed DMA request lines.
|
2009-09-07 11:26:23 +08:00
|
|
|
|
2018-08-20 01:27:16 +08:00
|
|
|
config MCF_EDMA
|
|
|
|
|
tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
|
|
|
|
|
depends on M5441x || COMPILE_TEST
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Support the Freescale ColdFire eDMA engine, 64-channel
|
|
|
|
|
implementation that performs complex data transfers with
|
|
|
|
|
minimal intervention from a host processor.
|
|
|
|
|
This module can be found on Freescale ColdFire mcf5441x SoCs.
|
|
|
|
|
|
2019-10-15 11:33:59 +08:00
|
|
|
config MILBEAUT_HDMAC
|
|
|
|
|
tristate "Milbeaut AHB DMA support"
|
|
|
|
|
depends on ARCH_MILBEAUT || COMPILE_TEST
|
|
|
|
|
depends on OF
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Say yes here to support the Socionext Milbeaut
|
|
|
|
|
HDMAC device.
|
|
|
|
|
|
2019-10-15 11:32:19 +08:00
|
|
|
config MILBEAUT_XDMAC
|
|
|
|
|
tristate "Milbeaut AXI DMA support"
|
|
|
|
|
depends on ARCH_MILBEAUT || COMPILE_TEST
|
|
|
|
|
depends on OF
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Say yes here to support the Socionext Milbeaut
|
|
|
|
|
XDMAC device.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MMP_PDMA
|
2021-01-21 19:03:55 +08:00
|
|
|
tristate "MMP PDMA support"
|
2016-09-02 18:25:56 +08:00
|
|
|
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
|
2009-11-20 02:49:17 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the MMP PDMA engine for PXA and MMP platform.
|
2009-11-20 02:49:17 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MMP_TDMA
|
2021-01-21 19:03:56 +08:00
|
|
|
tristate "MMP Two-Channel DMA support"
|
2016-09-02 18:27:09 +08:00
|
|
|
depends on ARCH_MMP || COMPILE_TEST
|
2010-03-30 21:33:42 +08:00
|
|
|
select DMA_ENGINE
|
2016-10-07 05:59:53 +08:00
|
|
|
select GENERIC_ALLOCATOR
|
2010-03-30 21:33:42 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the MMP Two-Channel DMA engine.
|
|
|
|
|
This engine used for MMP Audio DMA and pxa910 SQU.
|
2010-03-30 21:33:42 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MOXART_DMA
|
|
|
|
|
tristate "MOXART DMA support"
|
|
|
|
|
depends on ARCH_MOXART
|
2009-12-12 12:24:44 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
2009-12-12 12:24:44 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the MOXA ART SoC DMA controller.
|
|
|
|
|
|
|
|
|
|
Say Y here if you enabled MMP ADMA, otherwise say N.
|
2009-12-12 12:24:44 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MPC512X_DMA
|
|
|
|
|
tristate "Freescale MPC512x built-in DMA engine support"
|
|
|
|
|
depends on PPC_MPC512x || PPC_MPC831x
|
2010-03-26 02:44:21 +08:00
|
|
|
select DMA_ENGINE
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the Freescale MPC512x built-in DMA engine.
|
2010-03-26 02:44:21 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MV_XOR
|
|
|
|
|
bool "Marvell XOR engine support"
|
2016-04-29 15:49:08 +08:00
|
|
|
depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
|
2011-10-28 10:22:39 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the Marvell XOR engine.
|
2011-10-28 10:22:39 +08:00
|
|
|
|
2016-06-16 20:28:34 +08:00
|
|
|
config MV_XOR_V2
|
|
|
|
|
bool "Marvell XOR engine version 2 support "
|
|
|
|
|
depends on ARM64
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2022-11-11 21:54:40 +08:00
|
|
|
select GENERIC_MSI_IRQ
|
2020-06-14 00:50:22 +08:00
|
|
|
help
|
2016-06-16 20:28:34 +08:00
|
|
|
Enable support for the Marvell version 2 XOR engine.
|
|
|
|
|
|
|
|
|
|
This engine provides acceleration for copy, XOR and RAID6
|
|
|
|
|
operations, and is available on Marvell Armada 7K and 8K
|
|
|
|
|
platforms.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MXS_DMA
|
|
|
|
|
bool "MXS DMA support"
|
2017-06-09 06:46:23 +08:00
|
|
|
depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST
|
2015-08-24 16:13:14 +08:00
|
|
|
select STMP_DEVICE
|
2011-10-28 10:22:39 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the MXS DMA engine. This engine including APBH-DMA
|
2017-06-16 22:58:46 +08:00
|
|
|
and APBX-DMA is integrated into some Freescale chips.
|
2011-10-28 10:22:39 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MX3_IPU
|
|
|
|
|
bool "MX3x Image Processing Unit support"
|
|
|
|
|
depends on ARCH_MXC
|
2012-08-23 09:09:34 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
default y
|
2012-08-23 09:09:34 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
If you plan to use the Image Processing unit in the i.MX3x, say
|
|
|
|
|
Y here. If unsure, select Y.
|
2015-04-09 17:35:49 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config MX3_IPU_IRQS
|
|
|
|
|
int "Number of dynamically mapped interrupts for IPU"
|
|
|
|
|
depends on MX3_IPU
|
|
|
|
|
range 2 137
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
|
|
|
|
|
To avoid bloating the irq_desc[] array we allocate a sufficient
|
|
|
|
|
number of IRQ slots and map them dynamically to specific sources.
|
2009-12-12 12:24:44 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config NBPFAXI_DMA
|
|
|
|
|
tristate "Renesas Type-AXI NBPF DMA support"
|
2010-05-24 11:28:19 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
depends on ARM || COMPILE_TEST
|
2010-05-24 11:28:19 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support for "Type-AXI" NBPF DMA IPs from Renesas
|
2010-05-24 11:28:19 +08:00
|
|
|
|
2018-07-26 13:06:57 +08:00
|
|
|
config OWL_DMA
|
|
|
|
|
tristate "Actions Semi Owl SoCs DMA support"
|
|
|
|
|
depends on ARCH_ACTIONS
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Actions Semi Owl SoCs DMA controller.
|
|
|
|
|
|
2010-07-30 16:23:03 +08:00
|
|
|
config PCH_DMA
|
2011-11-17 15:14:23 +08:00
|
|
|
tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
|
2014-05-16 22:17:37 +08:00
|
|
|
depends on PCI && (X86_32 || COMPILE_TEST)
|
2010-07-30 16:23:03 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2011-01-05 16:43:52 +08:00
|
|
|
Enable support for Intel EG20T PCH DMA engine.
|
|
|
|
|
|
2011-11-17 15:14:22 +08:00
|
|
|
This driver also can be used for LAPIS Semiconductor IOH(Input/
|
2011-11-17 15:14:23 +08:00
|
|
|
Output Hub), ML7213, ML7223 and ML7831.
|
|
|
|
|
ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
|
|
|
|
|
for MP(Media Phone) use and ML7831 IOH is for general purpose use.
|
|
|
|
|
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
|
|
|
|
|
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
|
2010-07-30 16:23:03 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config PL330_DMA
|
|
|
|
|
tristate "DMA API Driver for PL330"
|
2010-09-30 21:56:34 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
depends on ARM_AMBA
|
2010-09-30 21:56:34 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Select if your platform has one or more PL330 DMACs.
|
|
|
|
|
You need to provide platform specific settings via
|
|
|
|
|
platform_data for a dma-pl330 device.
|
2010-09-30 21:56:34 +08:00
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config PXA_DMA
|
|
|
|
|
bool "PXA DMA support"
|
|
|
|
|
depends on (ARCH_MMP || ARCH_PXA)
|
2010-10-06 16:25:55 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_VIRTUAL_CHANNELS
|
2010-10-06 16:25:55 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the DMA engine for PXA. It is also compatible with MMP PDMA
|
|
|
|
|
platform. The internal DMA IP of all PXA variants is supported, with
|
|
|
|
|
16 to 32 channels for peripheral to memory or memory to memory
|
|
|
|
|
transfers.
|
2010-10-06 16:25:55 +08:00
|
|
|
|
2020-01-04 05:20:19 +08:00
|
|
|
config PLX_DMA
|
|
|
|
|
tristate "PLX ExpressLane PEX Switch DMA Engine Support"
|
|
|
|
|
depends on PCI
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Some PLX ExpressLane PCI Switches support additional DMA engines.
|
|
|
|
|
These are exposed via extra functions on the switch's
|
|
|
|
|
upstream port. Each function exposes one DMA channel.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config STE_DMA40
|
|
|
|
|
bool "ST-Ericsson DMA40 support"
|
|
|
|
|
depends on ARCH_U8500
|
2011-05-29 18:10:02 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support for ST-Ericsson DMA40 controller
|
2011-05-29 18:10:02 +08:00
|
|
|
|
2016-10-18 17:39:11 +08:00
|
|
|
config ST_FDMA
|
|
|
|
|
tristate "ST FDMA dmaengine support"
|
|
|
|
|
depends on ARCH_STI
|
2016-11-17 17:53:01 +08:00
|
|
|
depends on REMOTEPROC
|
2016-10-18 17:39:11 +08:00
|
|
|
select ST_SLIM_REMOTEPROC
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for ST FDMA controller.
|
|
|
|
|
It supports 16 independent DMA channels, accepts up to 32 DMA requests
|
|
|
|
|
|
|
|
|
|
Say Y here if you have such a chipset.
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2015-10-16 21:59:14 +08:00
|
|
|
config STM32_DMA
|
|
|
|
|
bool "STMicroelectronics STM32 DMA support"
|
2016-09-02 18:27:51 +08:00
|
|
|
depends on ARCH_STM32 || COMPILE_TEST
|
2015-10-16 21:59:14 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the on-chip DMA controller on STMicroelectronics
|
|
|
|
|
STM32 MCUs.
|
2016-12-13 21:40:44 +08:00
|
|
|
If you have a board based on such a MCU and wish to use DMA say Y
|
2015-10-16 21:59:14 +08:00
|
|
|
here.
|
|
|
|
|
|
2017-09-22 15:31:30 +08:00
|
|
|
config STM32_DMAMUX
|
|
|
|
|
bool "STMicroelectronics STM32 dma multiplexer support"
|
|
|
|
|
depends on STM32_DMA || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
Enable support for the on-chip DMA multiplexer on STMicroelectronics
|
|
|
|
|
STM32 MCUs.
|
|
|
|
|
If you have a board based on such a MCU and wish to use DMAMUX say Y
|
|
|
|
|
here.
|
|
|
|
|
|
2017-09-28 23:36:41 +08:00
|
|
|
config STM32_MDMA
|
|
|
|
|
bool "STMicroelectronics STM32 master dma support"
|
|
|
|
|
depends on ARCH_STM32 || COMPILE_TEST
|
2017-10-11 22:00:04 +08:00
|
|
|
depends on OF
|
2017-09-28 23:36:41 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the on-chip MDMA controller on STMicroelectronics
|
|
|
|
|
STM32 platforms.
|
|
|
|
|
If you have a board based on STM32 SoC and wish to use the master DMA
|
|
|
|
|
say Y here.
|
|
|
|
|
|
2017-10-24 13:47:50 +08:00
|
|
|
config SPRD_DMA
|
|
|
|
|
tristate "Spreadtrum DMA support"
|
|
|
|
|
depends on ARCH_SPRD || COMPILE_TEST
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the on-chip DMA controller on Spreadtrum platform.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TXX9_DMAC
|
|
|
|
|
tristate "Toshiba TXx9 SoC DMA support"
|
2022-02-22 17:04:28 +08:00
|
|
|
depends on MACH_TX49XX
|
2012-06-15 11:04:08 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Support the TXx9 SoC internal DMA controller. This can be
|
|
|
|
|
integrated in chips such as the Toshiba TX4927/38/39.
|
2012-06-15 11:04:08 +08:00
|
|
|
|
2022-02-25 21:20:44 +08:00
|
|
|
config TEGRA186_GPC_DMA
|
|
|
|
|
tristate "NVIDIA Tegra GPC DMA support"
|
|
|
|
|
depends on (ARCH_TEGRA || COMPILE_TEST) && ARCH_DMA_ADDR_T_64BIT
|
2022-05-05 17:32:36 +08:00
|
|
|
depends on IOMMU_API
|
2022-02-25 21:20:44 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Support for the NVIDIA Tegra General Purpose Central DMA controller.
|
|
|
|
|
The DMA controller has multiple DMA channels which can be configured
|
|
|
|
|
for different peripherals like UART, SPI, etc which are on APB bus.
|
|
|
|
|
This DMA controller transfers data from memory to peripheral FIFO
|
|
|
|
|
or vice versa. It also supports memory to memory data transfer.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TEGRA20_APB_DMA
|
2020-02-10 00:33:52 +08:00
|
|
|
tristate "NVIDIA Tegra20 APB DMA support"
|
2020-02-10 00:33:54 +08:00
|
|
|
depends on ARCH_TEGRA || COMPILE_TEST
|
2012-04-13 19:10:24 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
help
|
|
|
|
|
Support for the NVIDIA Tegra20 APB DMA controller driver. The
|
|
|
|
|
DMA controller is having multiple DMA channel which can be
|
|
|
|
|
configured for different peripherals like audio, UART, SPI,
|
|
|
|
|
I2C etc which is in APB bus.
|
|
|
|
|
This DMA controller transfers data from memory to peripheral fifo
|
|
|
|
|
or vice versa. It does not support memory to memory data transfer.
|
2012-04-13 19:10:24 +08:00
|
|
|
|
2016-05-13 01:02:23 +08:00
|
|
|
config TEGRA210_ADMA
|
2016-10-23 06:25:10 +08:00
|
|
|
tristate "NVIDIA Tegra210 ADMA support"
|
2019-06-20 23:54:19 +08:00
|
|
|
depends on (ARCH_TEGRA_210_SOC || COMPILE_TEST)
|
2016-05-13 01:02:23 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Support for the NVIDIA Tegra210 ADMA controller driver. The
|
|
|
|
|
DMA controller has multiple DMA channels and is used to service
|
|
|
|
|
various audio clients in the Tegra210 audio processing engine
|
|
|
|
|
(APE). This DMA controller transfers data from memory to
|
|
|
|
|
peripheral and vice versa. It does not support memory to
|
|
|
|
|
memory data transfer.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config TIMB_DMA
|
|
|
|
|
tristate "Timberdale FPGA DMA support"
|
2016-09-02 18:37:05 +08:00
|
|
|
depends on MFD_TIMBERDALE || COMPILE_TEST
|
2014-01-07 03:18:24 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
help
|
|
|
|
|
Enable support for the Timberdale FPGA DMA engine.
|
2014-01-07 03:18:24 +08:00
|
|
|
|
2018-10-12 00:41:03 +08:00
|
|
|
config UNIPHIER_MDMAC
|
|
|
|
|
tristate "UniPhier MIO DMAC"
|
|
|
|
|
depends on ARCH_UNIPHIER || COMPILE_TEST
|
|
|
|
|
depends on OF
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the MIO DMAC (Media I/O DMA controller) on the
|
|
|
|
|
UniPhier platform. This DMA controller is used as the external
|
|
|
|
|
DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
|
|
|
|
|
|
2020-02-21 15:52:30 +08:00
|
|
|
config UNIPHIER_XDMAC
|
|
|
|
|
tristate "UniPhier XDMAC support"
|
|
|
|
|
depends on ARCH_UNIPHIER || COMPILE_TEST
|
|
|
|
|
depends on OF
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for the XDMAC (external DMA controller) on the
|
|
|
|
|
UniPhier platform. This DMA controller can transfer data from
|
|
|
|
|
memory to memory, memory to peripheral and peripheral to memory.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
config XGENE_DMA
|
|
|
|
|
tristate "APM X-Gene DMA support"
|
|
|
|
|
depends on ARCH_XGENE || COMPILE_TEST
|
2014-02-18 10:17:12 +08:00
|
|
|
select DMA_ENGINE
|
2015-08-24 16:13:14 +08:00
|
|
|
select DMA_ENGINE_RAID
|
|
|
|
|
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2014-02-18 10:17:12 +08:00
|
|
|
help
|
2015-08-24 16:13:14 +08:00
|
|
|
Enable support for the APM X-Gene SoC DMA engine.
|
2014-01-17 16:46:05 +08:00
|
|
|
|
2016-06-24 13:21:25 +08:00
|
|
|
config XILINX_DMA
|
|
|
|
|
tristate "Xilinx AXI DMAS Engine"
|
2016-04-06 13:08:08 +08:00
|
|
|
depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
|
2014-04-23 22:53:26 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for Xilinx AXI VDMA Soft IP.
|
|
|
|
|
|
2016-06-24 13:21:25 +08:00
|
|
|
AXI VDMA engine provides high-bandwidth direct memory access
|
2014-04-23 22:53:26 +08:00
|
|
|
between memory and AXI4-Stream video type target
|
|
|
|
|
peripherals including peripherals which support AXI4-
|
|
|
|
|
Stream Video Protocol. It has two stream interfaces/
|
|
|
|
|
channels, Memory Mapped to Stream (MM2S) and Stream to
|
|
|
|
|
Memory Mapped (S2MM) for the data transfers.
|
2016-06-24 13:21:25 +08:00
|
|
|
AXI CDMA engine provides high-bandwidth direct memory access
|
|
|
|
|
between a memory-mapped source address and a memory-mapped
|
|
|
|
|
destination address.
|
|
|
|
|
AXI DMA engine provides high-bandwidth one dimensional direct
|
|
|
|
|
memory access between memory and AXI4-Stream target peripherals.
|
2019-10-23 01:00:22 +08:00
|
|
|
AXI MCDMA engine provides high-bandwidth direct memory access
|
|
|
|
|
between memory and AXI4-Stream target peripherals. It provides
|
|
|
|
|
the scatter gather interface with multiple channels independent
|
|
|
|
|
configuration support.
|
2014-04-23 22:53:26 +08:00
|
|
|
|
2023-01-20 00:32:05 +08:00
|
|
|
config XILINX_XDMA
|
|
|
|
|
tristate "Xilinx DMA/Bridge Subsystem DMA Engine"
|
|
|
|
|
depends on HAS_IOMEM
|
|
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
select REGMAP_MMIO
|
|
|
|
|
help
|
|
|
|
|
Enable support for Xilinx DMA/Bridge Subsystem DMA engine. The DMA
|
|
|
|
|
provides high performance block data movement between Host memory
|
|
|
|
|
and the DMA subsystem. These direct memory transfers can be both in
|
|
|
|
|
the Host to Card (H2C) and Card to Host (C2H) transfers.
|
|
|
|
|
The core also provides up to 16 user interrupt wires that generate
|
|
|
|
|
interrupts to the host.
|
|
|
|
|
|
2016-07-01 19:37:06 +08:00
|
|
|
config XILINX_ZYNQMP_DMA
|
|
|
|
|
tristate "Xilinx ZynqMP DMA Engine"
|
2021-08-26 17:47:38 +08:00
|
|
|
depends on ARCH_ZYNQ || MICROBLAZE || ARM64 || COMPILE_TEST
|
2016-07-01 19:37:06 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
help
|
|
|
|
|
Enable support for Xilinx ZynqMP DMA controller.
|
2014-04-23 22:53:26 +08:00
|
|
|
|
2020-07-17 09:33:35 +08:00
|
|
|
config XILINX_ZYNQMP_DPDMA
|
|
|
|
|
tristate "Xilinx DPDMA Engine"
|
2021-05-20 23:24:17 +08:00
|
|
|
depends on HAS_IOMEM && OF
|
2020-07-17 09:33:35 +08:00
|
|
|
select DMA_ENGINE
|
|
|
|
|
select DMA_VIRTUAL_CHANNELS
|
|
|
|
|
help
|
|
|
|
|
Enable support for Xilinx ZynqMP DisplayPort DMA. Choose this option
|
|
|
|
|
if you have a Xilinx ZynqMP SoC with a DisplayPort subsystem. The
|
|
|
|
|
driver provides the dmaengine required by the DisplayPort subsystem
|
|
|
|
|
display driver.
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
# driver files
|
|
|
|
|
source "drivers/dma/bestcomm/Kconfig"
|
2006-05-24 08:18:44 +08:00
|
|
|
|
2018-03-15 15:40:36 +08:00
|
|
|
source "drivers/dma/mediatek/Kconfig"
|
|
|
|
|
|
2021-08-17 21:55:57 +08:00
|
|
|
source "drivers/dma/ptdma/Kconfig"
|
|
|
|
|
|
2016-02-05 12:34:32 +08:00
|
|
|
source "drivers/dma/qcom/Kconfig"
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
source "drivers/dma/dw/Kconfig"
|
2012-04-13 19:07:23 +08:00
|
|
|
|
dmaengine: Add Synopsys eDMA IP core driver
Add Synopsys PCIe Endpoint eDMA IP core driver to kernel.
This IP is generally distributed with Synopsys PCIe Endpoint IP (depends
of the use and licensing agreement).
This core driver, initializes and configures the eDMA IP using vma-helpers
functions and dma-engine subsystem.
This driver can be compile as built-in or external module in kernel.
To enable this driver just select DW_EDMA option in kernel configuration,
however it requires and selects automatically DMA_ENGINE and
DMA_VIRTUAL_CHANNELS option too.
In order to transfer data from point A to B as fast as possible this IP
requires a dedicated memory space containing linked list of elements.
All elements of this linked list are continuous and each one describes a
data transfer (source and destination addresses, length and a control
variable).
For the sake of simplicity, lets assume a memory space for channel write
0 which allows about 42 elements.
+---------+
| Desc #0 |-+
+---------+ |
V
+----------+
| Chunk #0 |-+
| CB = 1 | | +----------+ +-----+ +-----------+ +-----+
+----------+ +->| Burst #0 |->| ... |->| Burst #41 |->| llp |
| +----------+ +-----+ +-----------+ +-----+
V
+----------+
| Chunk #1 |-+
| CB = 0 | | +-----------+ +-----+ +-----------+ +-----+
+----------+ +->| Burst #42 |->| ... |->| Burst #83 |->| llp |
| +-----------+ +-----+ +-----------+ +-----+
V
+----------+
| Chunk #2 |-+
| CB = 1 | | +-----------+ +-----+ +------------+ +-----+
+----------+ +->| Burst #84 |->| ... |->| Burst #125 |->| llp |
| +-----------+ +-----+ +------------+ +-----+
V
+----------+
| Chunk #3 |-+
| CB = 0 | | +------------+ +-----+ +------------+ +-----+
+----------+ +->| Burst #126 |->| ... |->| Burst #129 |->| llp |
+------------+ +-----+ +------------+ +-----+
Legend:
- Linked list, also know as Chunk
- Linked list element*, also know as Burst *CB*, also know as Change Bit,
it's a control bit (and typically is toggled) that allows to easily
identify and differentiate between the current linked list and the
previous or the next one.
- LLP, is a special element that indicates the end of the linked list
element stream also informs that the next CB should be toggle
On every last Burst of the Chunk (Burst #41, Burst #83, Burst #125 or
even Burst #129) is set some flags on their control variable (RIE and
LIE bits) that will trigger the send of "done" interruption.
On the interruptions callback, is decided whether to recycle the linked
list memory space by writing a new set of Bursts elements (if still
exists Chunks to transfer) or is considered completed (if there is no
Chunks available to transfer).
On scatter-gather transfer mode, the client will submit a scatter-gather
list of n (on this case 130) elements, that will be divide in multiple
Chunks, each Chunk will have (on this case 42) a limited number of
Bursts and after transferring all Bursts, an interrupt will be
triggered, which will allow to recycle the all linked list dedicated
memory again with the new information relative to the next Chunk and
respective Burst associated and repeat the whole cycle again.
On cyclic transfer mode, the client will submit a buffer pointer, length
of it and number of repetitions, in this case each burst will correspond
directly to each repetition.
Each Burst can describes a data transfer from point A(source) to point
B(destination) with a length that can be from 1 byte up to 4 GB. Since
dedicated the memory space where the linked list will reside is limited,
the whole n burst elements will be organized in several Chunks, that
will be used later to recycle the dedicated memory space to initiate a
new sequence of data transfers.
The whole transfer is considered has completed when it was transferred
all bursts.
Currently this IP has a set well-known register map, which includes
support for legacy and unroll modes. Legacy mode is version of this
register map that has multiplexer register that allows to switch
registers between all write and read channels and the unroll modes
repeats all write and read channels registers with an offset between
them. This register map is called v0.
The IP team is creating a new register map more suitable to the latest
PCIe features, that very likely will change the map register, which this
version will be called v1. As soon as this new version is released by
the IP team the support for this version in be included on this driver.
According to the logic, patches 1, 2 and 3 should be squashed into 1
unique patch, but for the sake of simplicity of review, it was divided
in this 3 patches files.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <rmk+kernel@armlinux.org.uk>
Cc: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-06-04 21:29:22 +08:00
|
|
|
source "drivers/dma/dw-edma/Kconfig"
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
source "drivers/dma/hsu/Kconfig"
|
2013-04-09 19:05:43 +08:00
|
|
|
|
2019-11-07 16:49:21 +08:00
|
|
|
source "drivers/dma/sf-pdma/Kconfig"
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
source "drivers/dma/sh/Kconfig"
|
2013-02-13 01:15:02 +08:00
|
|
|
|
2018-04-25 16:45:03 +08:00
|
|
|
source "drivers/dma/ti/Kconfig"
|
|
|
|
|
|
2019-09-30 10:04:40 +08:00
|
|
|
source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
|
|
|
|
|
|
2020-12-03 12:10:44 +08:00
|
|
|
source "drivers/dma/lgm/Kconfig"
|
|
|
|
|
|
2015-08-24 16:13:14 +08:00
|
|
|
# clients
|
2006-06-18 12:24:58 +08:00
|
|
|
comment "DMA Clients"
|
2007-10-16 16:27:42 +08:00
|
|
|
depends on DMA_ENGINE
|
2006-06-18 12:24:58 +08:00
|
|
|
|
2009-03-26 00:13:25 +08:00
|
|
|
config ASYNC_TX_DMA
|
|
|
|
|
bool "Async_tx: Offload support for the async_tx api"
|
2009-09-09 06:06:10 +08:00
|
|
|
depends on DMA_ENGINE
|
2009-03-26 00:13:25 +08:00
|
|
|
help
|
|
|
|
|
This allows the async_tx api to take advantage of offload engines for
|
|
|
|
|
memcpy, memset, xor, and raid6 p+q operations. If your platform has
|
|
|
|
|
a dma engine that can perform raid operations and you have enabled
|
|
|
|
|
MD_RAID456 say Y.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2008-07-09 02:58:45 +08:00
|
|
|
config DMATEST
|
|
|
|
|
tristate "DMA Test client"
|
|
|
|
|
depends on DMA_ENGINE
|
2017-04-27 20:21:40 +08:00
|
|
|
select DMA_ENGINE_RAID
|
2008-07-09 02:58:45 +08:00
|
|
|
help
|
|
|
|
|
Simple DMA test client. Say N unless you're debugging a
|
|
|
|
|
DMA Device driver.
|
|
|
|
|
|
2013-12-10 02:33:16 +08:00
|
|
|
config DMA_ENGINE_RAID
|
|
|
|
|
bool
|
|
|
|
|
|
2007-10-16 16:27:42 +08:00
|
|
|
endif
|