98 lines
3.2 KiB
Plaintext
98 lines
3.2 KiB
Plaintext
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* Rockchip Pinmux Controller
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The Rockchip Pinmux Controller, enables the IC
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to share one PAD to several functional blocks. The sharing is done by
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multiplexing the PAD input/output signals. For each PAD there are up to
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4 muxing options with option 0 being the use as a GPIO.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The Rockchip pin configuration node is a node of a group of pins which can be
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used for a specific device or function. This node represents both mux and
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config of the pins in that group. The 'pins' selects the function mode(also
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named pin mode) this pin can work on and the 'config' configures various pad
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settings such as pull-up, etc.
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The pins are grouped into up to 5 individual pin banks which need to be
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defined as gpio sub-nodes of the pinmux controller.
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Required properties for iomux controller:
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- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
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"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
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Required properties for gpio sub nodes:
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- compatible: "rockchip,gpio-bank"
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- reg: register of the gpio bank (different than the iomux registerset)
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- interrupts: base interrupt of the gpio bank in the interrupt controller
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- clocks: clock that drives this bank
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- gpio-controller: identifies the node as a gpio controller and pin bank.
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- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
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binding is used, the amount of cells must be specified as 2. See generic
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GPIO binding documentation for description of particular cells.
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- interrupt-controller: identifies the controller node as interrupt-parent.
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- #interrupt-cells: the value of this property should be 2 and the interrupt
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cells should use the standard two-cell scheme described in
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bindings/interrupt-controller/interrupts.txt
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Required properties for pin configuration node:
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- rockchip,pins: 3 integers array, represents a group of pins mux and config
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setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
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The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
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The phandle of a node containing the generic pinconfig options
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to use, as described in pinctrl-bindings.txt in this directory.
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Examples:
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#include <dt-bindings/pinctrl/rockchip.h>
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...
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pinctrl@20008000 {
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compatible = "rockchip,rk3066a-pinctrl";
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reg = <0x20008000 0x150>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@20034000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20034000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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...
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pcfg_pull_default: pcfg_pull_default {
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bias-pull-pin-default
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
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<RK_GPIO1 9 1 &pcfg_pull_default>;
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};
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};
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};
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uart2: serial@20064000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20064000 0x400>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&mux_uart2>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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};
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