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OpenCloudOS-Kernel/drivers/clk/microchip/clk-pic32mzda.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445 Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 24 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.872212424@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-01 16:08:59 +08:00
// SPDX-License-Identifier: GPL-2.0-only
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
/*
* Purna Chandra Mandal,<purna.mandal@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#include <dt-bindings/clock/microchip,pic32-clock.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
clk: Remove io.h from clk-provider.h Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-19 06:20:22 +08:00
#include <linux/io.h>
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <asm/traps.h>
#include "clk-core.h"
/* FRC Postscaler */
#define OSC_FRCDIV_MASK 0x07
#define OSC_FRCDIV_SHIFT 24
/* SPLL fields */
#define PLL_ICLK_MASK 0x01
#define PLL_ICLK_SHIFT 7
#define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \
{ \
.ctrl_reg = (__reg), \
.init_data = { \
.name = (__clk_name), \
.parent_names = (const char *[]) { \
"sys_clk" \
}, \
.num_parents = 1, \
.ops = &pic32_pbclk_ops, \
.flags = (__flags), \
}, \
}
#define DECLARE_REFO_CLOCK(__clkid, __reg) \
{ \
.ctrl_reg = (__reg), \
.init_data = { \
.name = "refo" #__clkid "_clk", \
.parent_names = (const char *[]) { \
"sys_clk", "pb1_clk", "posc_clk", \
"frc_clk", "lprc_clk", "sosc_clk", \
"sys_pll", "refi" #__clkid "_clk", \
"bfrc_clk", \
}, \
.num_parents = 9, \
.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
.ops = &pic32_roclk_ops, \
}, \
.parent_map = (const u32[]) { \
0, 1, 2, 3, 4, 5, 7, 8, 9 \
}, \
}
static const struct pic32_ref_osc_data ref_clks[] = {
DECLARE_REFO_CLOCK(1, 0x80),
DECLARE_REFO_CLOCK(2, 0xa0),
DECLARE_REFO_CLOCK(3, 0xc0),
DECLARE_REFO_CLOCK(4, 0xe0),
DECLARE_REFO_CLOCK(5, 0x100),
};
static const struct pic32_periph_clk_data periph_clocks[] = {
DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
};
static const struct pic32_sys_clk_data sys_mux_clk = {
.slew_reg = 0x1c0,
.slew_div = 2, /* step of div_4 -> div_2 -> no_div */
.init_data = {
.name = "sys_clk",
.parent_names = (const char *[]) {
"frcdiv_clk", "sys_pll", "posc_clk",
"sosc_clk", "lprc_clk", "frcdiv_clk",
},
.num_parents = 6,
.ops = &pic32_sclk_ops,
},
.parent_map = (const u32[]) {
0, 1, 2, 4, 5, 7,
},
};
static const struct pic32_sys_pll_data sys_pll = {
.ctrl_reg = 0x020,
.status_reg = 0x1d0,
.lock_mask = BIT(7),
.init_data = {
.name = "sys_pll",
.parent_names = (const char *[]) {
"spll_mux_clk"
},
.num_parents = 1,
.ops = &pic32_spll_ops,
},
};
static const struct pic32_sec_osc_data sosc_clk = {
.status_reg = 0x1d0,
.enable_mask = BIT(1),
.status_mask = BIT(4),
clk: microchip: Initialize SOSC clock rate for PIC32MZDA. Optional SOSC is an external fixed clock running at 32768HZ. So Initialize SOSC rate as per PIC32MZDA datasheet. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-17 13:05:51 +08:00
.fixed_rate = 32768,
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
.init_data = {
.name = "sosc_clk",
.parent_names = NULL,
.ops = &pic32_sosc_ops,
},
};
static int pic32mzda_critical_clks[] = {
PB2CLK, PB7CLK
};
/* PIC32MZDA clock data */
struct pic32mzda_clk_data {
struct clk *clks[MAXCLKS];
struct pic32_clk_common core;
struct clk_onecell_data onecell_data;
struct notifier_block failsafe_notifier;
};
static int pic32_fscm_nmi(struct notifier_block *nb,
unsigned long action, void *data)
{
struct pic32mzda_clk_data *cd;
cd = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
/* SYSCLK is now running from BFRCCLK. Report clock failure. */
if (readl(cd->core.iobase) & BIT(2))
pr_alert("pic32-clk: FSCM detected clk failure.\n");
/* TODO: detect reason of failure and recover accordingly */
return NOTIFY_OK;
}
static int pic32mzda_clk_probe(struct platform_device *pdev)
{
const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
struct device_node *np = pdev->dev.of_node;
struct pic32mzda_clk_data *cd;
struct pic32_clk_common *core;
struct clk *pll_mux_clk, *clk;
struct clk **clks;
int nr_clks, i, ret;
cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
if (!cd)
return -ENOMEM;
core = &cd->core;
core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
if (IS_ERR(core->iobase)) {
dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
return PTR_ERR(core->iobase);
}
spin_lock_init(&core->reg_lock);
core->dev = &pdev->dev;
clks = &cd->clks[0];
/* register fixed rate clocks */
clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
clk: microchip: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 05:52:54 +08:00
0, 24000000);
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
clk: microchip: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 05:52:54 +08:00
0, 8000000);
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
clk: microchip: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 05:52:54 +08:00
0, 8000000);
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
clk: microchip: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 05:52:54 +08:00
0, 32000);
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
clk: microchip: Remove CLK_IS_ROOT This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate CLK_IS_ROOT", 2016-02-02) so remove it. Cc: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: <linux-mips@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 05:52:54 +08:00
0, 24000000);
CLK: microchip: Add Microchip PIC32 clock driver. This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:52:40 +08:00
/* fixed rate (optional) clock */
if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
pr_info("pic32-clk: dt requests SOSC.\n");
clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
}
/* divider clock */
clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
"frc_clk", 0,
core->iobase,
OSC_FRCDIV_SHIFT,
OSC_FRCDIV_MASK,
CLK_DIVIDER_POWER_OF_TWO,
&core->reg_lock);
/* PLL ICLK mux */
pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
pll_mux_parents, 2, 0,
core->iobase + 0x020,
PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
if (IS_ERR(pll_mux_clk))
pr_err("spll_mux_clk: clk register failed\n");
/* PLL */
clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
/* SYSTEM clock */
clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
/* Peripheral bus clocks */
for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
core);
/* Reference oscillator clock */
for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
/* register clkdev */
for (i = 0; i < MAXCLKS; i++) {
if (IS_ERR(clks[i]))
continue;
clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
}
/* register clock provider */
cd->onecell_data.clks = clks;
cd->onecell_data.clk_num = MAXCLKS;
ret = of_clk_add_provider(np, of_clk_src_onecell_get,
&cd->onecell_data);
if (ret)
return ret;
/* force enable critical clocks */
for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
clk = clks[pic32mzda_critical_clks[i]];
if (clk_prepare_enable(clk))
dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
__clk_get_name(clk));
}
/* register NMI for failsafe clock monitor */
cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
return register_nmi_notifier(&cd->failsafe_notifier);
}
static const struct of_device_id pic32mzda_clk_match_table[] = {
{ .compatible = "microchip,pic32mzda-clk", },
{ }
};
MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
static struct platform_driver pic32mzda_clk_driver = {
.probe = pic32mzda_clk_probe,
.driver = {
.name = "clk-pic32mzda",
.of_match_table = pic32mzda_clk_match_table,
},
};
static int __init microchip_pic32mzda_clk_init(void)
{
return platform_driver_register(&pic32mzda_clk_driver);
}
core_initcall(microchip_pic32mzda_clk_init);
MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:clk-pic32mzda");