License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-10-23 13:26:29 +08:00
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#ifndef _ASM_X86_PGTABLE_64_H
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#define _ASM_X86_PGTABLE_64_H
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2005-04-17 06:20:36 +08:00
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2007-05-08 15:31:11 +08:00
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#include <linux/const.h>
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2009-02-09 10:50:52 +08:00
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#include <asm/pgtable_64_types.h>
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2007-05-03 01:27:06 +08:00
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#ifndef __ASSEMBLY__
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2005-04-17 06:20:36 +08:00
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/*
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* This file contains the functions and defines necessary to modify and use
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* the x86-64 page table tree.
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*/
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#include <asm/processor.h>
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2007-10-19 14:40:25 +08:00
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#include <linux/bitops.h>
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2005-04-17 06:20:36 +08:00
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#include <linux/threads.h>
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2018-09-20 10:58:28 +08:00
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#include <asm/fixmap.h>
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2005-04-17 06:20:36 +08:00
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2017-06-06 19:31:28 +08:00
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extern p4d_t level4_kernel_pgt[512];
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extern p4d_t level4_ident_pgt[512];
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2005-04-17 06:20:36 +08:00
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extern pud_t level3_kernel_pgt[512];
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extern pud_t level3_ident_pgt[512];
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extern pmd_t level2_kernel_pgt[512];
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2008-07-09 06:06:50 +08:00
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extern pmd_t level2_fixmap_pgt[512];
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extern pmd_t level2_ident_pgt[512];
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2018-09-20 10:58:28 +08:00
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extern pte_t level1_fixmap_pgt[512 * FIXMAP_PMD_NUM];
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2017-06-06 19:31:27 +08:00
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extern pgd_t init_top_pgt[];
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2005-04-17 06:20:36 +08:00
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2017-06-06 19:31:27 +08:00
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#define swapper_pg_dir init_top_pgt
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2005-04-17 06:20:36 +08:00
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extern void paging_init(void);
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2018-03-01 04:14:26 +08:00
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static inline void sync_initial_page_table(void) { }
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2005-04-17 06:20:36 +08:00
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2008-03-23 16:03:11 +08:00
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#define pte_ERROR(e) \
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2012-05-22 10:50:07 +08:00
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pr_err("%s:%d: bad pte %p(%016lx)\n", \
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2008-03-23 16:03:11 +08:00
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__FILE__, __LINE__, &(e), pte_val(e))
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#define pmd_ERROR(e) \
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2012-05-22 10:50:07 +08:00
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pr_err("%s:%d: bad pmd %p(%016lx)\n", \
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2008-03-23 16:03:11 +08:00
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pud_ERROR(e) \
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2012-05-22 10:50:07 +08:00
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pr_err("%s:%d: bad pud %p(%016lx)\n", \
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2008-03-23 16:03:11 +08:00
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__FILE__, __LINE__, &(e), pud_val(e))
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2017-03-30 16:07:29 +08:00
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#if CONFIG_PGTABLE_LEVELS >= 5
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#define p4d_ERROR(e) \
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pr_err("%s:%d: bad p4d %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), p4d_val(e))
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#endif
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2008-03-23 16:03:11 +08:00
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#define pgd_ERROR(e) \
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2012-05-22 10:50:07 +08:00
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pr_err("%s:%d: bad pgd %p(%016lx)\n", \
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2008-03-23 16:03:11 +08:00
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__FILE__, __LINE__, &(e), pgd_val(e))
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2005-04-17 06:20:36 +08:00
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2008-01-30 20:32:58 +08:00
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struct mm_struct;
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2020-06-05 07:47:12 +08:00
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#define mm_p4d_folded mm_p4d_folded
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static inline bool mm_p4d_folded(struct mm_struct *mm)
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{
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return !pgtable_l5_enabled();
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}
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2017-03-18 02:55:15 +08:00
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void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte);
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2008-06-25 12:19:22 +08:00
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void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte);
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2018-09-03 02:14:50 +08:00
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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2005-04-17 06:20:36 +08:00
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{
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2018-09-03 02:14:50 +08:00
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WRITE_ONCE(*ptep, pte);
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2008-01-30 20:32:58 +08:00
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}
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2005-04-17 06:20:36 +08:00
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2018-09-03 02:14:50 +08:00
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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2005-04-17 06:20:36 +08:00
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{
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2018-09-03 02:14:50 +08:00
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native_set_pte(ptep, native_make_pte(0));
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2008-01-30 20:32:58 +08:00
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}
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2005-04-17 06:20:36 +08:00
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2008-01-30 20:34:01 +08:00
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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2011-01-14 07:46:41 +08:00
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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2018-09-03 02:14:50 +08:00
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WRITE_ONCE(*pmdp, pmd);
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2011-01-14 07:46:41 +08:00
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}
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static inline void native_pmd_clear(pmd_t *pmd)
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{
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native_set_pmd(pmd, native_make_pmd(0));
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}
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2008-01-30 20:32:58 +08:00
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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2005-04-17 06:20:36 +08:00
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{
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2008-01-30 20:32:58 +08:00
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#ifdef CONFIG_SMP
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return native_make_pte(xchg(&xp->pte, 0));
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#else
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2008-03-23 16:03:11 +08:00
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/* native_local_ptep_get_and_clear,
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but duplicated because of cyclic dependency */
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2008-01-30 20:32:58 +08:00
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pte_t ret = *xp;
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native_pte_clear(NULL, 0, xp);
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return ret;
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#endif
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2005-04-17 06:20:36 +08:00
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}
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2011-01-14 07:46:41 +08:00
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
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2005-04-17 06:20:36 +08:00
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{
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2011-01-14 07:46:41 +08:00
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#ifdef CONFIG_SMP
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return native_make_pmd(xchg(&xp->pmd, 0));
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#else
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/* native_local_pmdp_get_and_clear,
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but duplicated because of cyclic dependency */
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pmd_t ret = *xp;
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native_pmd_clear(xp);
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return ret;
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#endif
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2008-01-30 20:32:58 +08:00
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}
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2005-04-17 06:20:36 +08:00
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2008-01-30 20:32:58 +08:00
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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2005-04-17 06:20:36 +08:00
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{
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2018-09-03 02:14:50 +08:00
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WRITE_ONCE(*pudp, pud);
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2005-04-17 06:20:36 +08:00
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}
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2008-01-30 20:32:58 +08:00
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static inline void native_pud_clear(pud_t *pud)
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{
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native_set_pud(pud, native_make_pud(0));
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}
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2005-09-04 06:55:06 +08:00
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2017-02-25 06:57:02 +08:00
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static inline pud_t native_pudp_get_and_clear(pud_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pud(xchg(&xp->pud, 0));
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#else
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/* native_local_pudp_get_and_clear,
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* but duplicated because of cyclic dependency
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*/
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pud_t ret = *xp;
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native_pud_clear(xp);
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return ret;
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#endif
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2017-03-18 02:55:15 +08:00
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}
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2018-06-26 18:03:41 +08:00
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static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d)
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2017-03-18 02:55:15 +08:00
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{
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2018-02-15 02:25:41 +08:00
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pgd_t pgd;
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2018-05-18 18:35:24 +08:00
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if (pgtable_l5_enabled() || !IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) {
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2018-09-03 02:14:50 +08:00
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WRITE_ONCE(*p4dp, p4d);
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2018-02-15 02:25:41 +08:00
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return;
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}
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2018-03-05 16:16:41 +08:00
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pgd = native_make_pgd(native_p4d_val(p4d));
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2018-07-18 17:40:52 +08:00
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pgd = pti_set_user_pgtbl((pgd_t *)p4dp, pgd);
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2018-09-03 02:14:50 +08:00
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WRITE_ONCE(*p4dp, native_make_p4d(native_pgd_val(pgd)));
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2017-03-18 02:55:15 +08:00
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}
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2018-06-26 18:03:41 +08:00
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static inline void native_p4d_clear(p4d_t *p4d)
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2017-03-18 02:55:15 +08:00
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{
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2017-03-30 16:07:29 +08:00
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native_set_p4d(p4d, native_make_p4d(0));
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2017-02-25 06:57:02 +08:00
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}
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2008-01-30 20:32:58 +08:00
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static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
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{
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2018-09-03 02:14:50 +08:00
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WRITE_ONCE(*pgdp, pti_set_user_pgtbl(pgdp, pgd));
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2008-01-30 20:32:58 +08:00
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}
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2005-11-07 16:59:43 +08:00
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2008-03-23 16:03:11 +08:00
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static inline void native_pgd_clear(pgd_t *pgd)
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2005-09-04 06:55:06 +08:00
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{
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2008-01-30 20:32:58 +08:00
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native_set_pgd(pgd, native_make_pgd(0));
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2005-09-04 06:55:06 +08:00
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}
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2005-04-17 06:20:36 +08:00
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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2020-07-24 19:44:18 +08:00
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/* PGD - Level 4 access */
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2005-04-17 06:20:36 +08:00
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2020-07-24 19:44:18 +08:00
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/* PUD - Level 3 access */
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2005-04-17 06:20:36 +08:00
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2020-07-24 19:44:18 +08:00
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/* PMD - Level 2 access */
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2005-04-17 06:20:36 +08:00
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2020-07-24 19:44:18 +08:00
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/* PTE - Level 1 access */
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2005-04-17 06:20:36 +08:00
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2016-07-08 08:19:11 +08:00
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/*
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* Encode and de-code a swap entry
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*
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2017-09-09 07:10:46 +08:00
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* | ... | 11| 10| 9|8|7|6|5| 4| 3|2| 1|0| <- bit number
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* | ... |SW3|SW2|SW1|G|L|D|A|CD|WT|U| W|P| <- bit names
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2020-04-07 11:05:33 +08:00
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* | TYPE (59-63) | ~OFFSET (9-58) |0|0|X|X| X| X|F|SD|0| <- swp entry
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2016-07-08 08:19:11 +08:00
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*
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* G (8) is aliased and used as a PROT_NONE indicator for
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* !present ptes. We need to start storing swap entries above
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* there. We also need to avoid using A and D because of an
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* erratum where they can be incorrectly set by hardware on
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* non-present PTEs.
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2017-09-09 07:10:46 +08:00
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*
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2020-04-07 11:05:33 +08:00
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* SD Bits 1-4 are not used in non-present format and available for
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* special use described below:
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*
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2017-09-09 07:10:46 +08:00
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* SD (1) in swp entry is used to store soft dirty bit, which helps us
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* remember soft dirty over page migration
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*
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2020-04-07 11:05:33 +08:00
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* F (2) in swp entry is used to record when a pagetable is
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* writeprotected by userfaultfd WP support.
|
|
|
|
*
|
2017-09-09 07:10:46 +08:00
|
|
|
* Bit 7 in swp entry should be 0 because pmd_present checks not only P,
|
|
|
|
* but also L and G.
|
2018-06-14 06:48:23 +08:00
|
|
|
*
|
|
|
|
* The offset is inverted by a binary not operation to make the high
|
|
|
|
* physical bits set.
|
2016-07-08 08:19:11 +08:00
|
|
|
*/
|
x86/speculation/l1tf: Change order of offset/type in swap entry
If pages are swapped out, the swap entry is stored in the corresponding
PTE, which has the Present bit cleared. CPUs vulnerable to L1TF speculate
on PTE entries which have the present bit set and would treat the swap
entry as phsyical address (PFN). To mitigate that the upper bits of the PTE
must be set so the PTE points to non existent memory.
The swap entry stores the type and the offset of a swapped out page in the
PTE. type is stored in bit 9-13 and offset in bit 14-63. The hardware
ignores the bits beyond the phsyical address space limit, so to make the
mitigation effective its required to start 'offset' at the lowest possible
bit so that even large swap offsets do not reach into the physical address
space limit bits.
Move offset to bit 9-58 and type to bit 59-63 which are the bits that
hardware generally doesn't care about.
That, in turn, means that if you on desktop chip with only 40 bits of
physical addressing, now that the offset starts at bit 9, there needs to be
30 bits of offset actually *in use* until bit 39 ends up being set, which
means when inverted it will again point into existing memory.
So that's 4 terabyte of swap space (because the offset is counted in pages,
so 30 bits of offset is 42 bits of actual coverage). With bigger physical
addressing, that obviously grows further, until the limit of the offset is
hit (at 50 bits of offset - 62 bits of actual swap file coverage).
This is a preparatory change for the actual swap entry inversion to protect
against L1TF.
[ AK: Updated description and minor tweaks. Split into two parts ]
[ tglx: Massaged changelog ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Acked-by: Vlastimil Babka <vbabka@suse.cz>
Acked-by: Dave Hansen <dave.hansen@intel.com>
2018-06-14 06:48:22 +08:00
|
|
|
#define SWP_TYPE_BITS 5
|
|
|
|
|
|
|
|
#define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
|
|
|
|
|
|
|
|
/* We always extract/encode the offset by shifting it all the way up, and then down again */
|
|
|
|
#define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT+SWP_TYPE_BITS)
|
2008-12-16 19:35:24 +08:00
|
|
|
|
|
|
|
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
|
|
|
|
|
x86/speculation/l1tf: Change order of offset/type in swap entry
If pages are swapped out, the swap entry is stored in the corresponding
PTE, which has the Present bit cleared. CPUs vulnerable to L1TF speculate
on PTE entries which have the present bit set and would treat the swap
entry as phsyical address (PFN). To mitigate that the upper bits of the PTE
must be set so the PTE points to non existent memory.
The swap entry stores the type and the offset of a swapped out page in the
PTE. type is stored in bit 9-13 and offset in bit 14-63. The hardware
ignores the bits beyond the phsyical address space limit, so to make the
mitigation effective its required to start 'offset' at the lowest possible
bit so that even large swap offsets do not reach into the physical address
space limit bits.
Move offset to bit 9-58 and type to bit 59-63 which are the bits that
hardware generally doesn't care about.
That, in turn, means that if you on desktop chip with only 40 bits of
physical addressing, now that the offset starts at bit 9, there needs to be
30 bits of offset actually *in use* until bit 39 ends up being set, which
means when inverted it will again point into existing memory.
So that's 4 terabyte of swap space (because the offset is counted in pages,
so 30 bits of offset is 42 bits of actual coverage). With bigger physical
addressing, that obviously grows further, until the limit of the offset is
hit (at 50 bits of offset - 62 bits of actual swap file coverage).
This is a preparatory change for the actual swap entry inversion to protect
against L1TF.
[ AK: Updated description and minor tweaks. Split into two parts ]
[ tglx: Massaged changelog ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Acked-by: Vlastimil Babka <vbabka@suse.cz>
Acked-by: Dave Hansen <dave.hansen@intel.com>
2018-06-14 06:48:22 +08:00
|
|
|
/* Extract the high bits for type */
|
|
|
|
#define __swp_type(x) ((x).val >> (64 - SWP_TYPE_BITS))
|
|
|
|
|
|
|
|
/* Shift up (to get rid of type), then down to get value */
|
2018-06-14 06:48:23 +08:00
|
|
|
#define __swp_offset(x) (~(x).val << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT)
|
x86/speculation/l1tf: Change order of offset/type in swap entry
If pages are swapped out, the swap entry is stored in the corresponding
PTE, which has the Present bit cleared. CPUs vulnerable to L1TF speculate
on PTE entries which have the present bit set and would treat the swap
entry as phsyical address (PFN). To mitigate that the upper bits of the PTE
must be set so the PTE points to non existent memory.
The swap entry stores the type and the offset of a swapped out page in the
PTE. type is stored in bit 9-13 and offset in bit 14-63. The hardware
ignores the bits beyond the phsyical address space limit, so to make the
mitigation effective its required to start 'offset' at the lowest possible
bit so that even large swap offsets do not reach into the physical address
space limit bits.
Move offset to bit 9-58 and type to bit 59-63 which are the bits that
hardware generally doesn't care about.
That, in turn, means that if you on desktop chip with only 40 bits of
physical addressing, now that the offset starts at bit 9, there needs to be
30 bits of offset actually *in use* until bit 39 ends up being set, which
means when inverted it will again point into existing memory.
So that's 4 terabyte of swap space (because the offset is counted in pages,
so 30 bits of offset is 42 bits of actual coverage). With bigger physical
addressing, that obviously grows further, until the limit of the offset is
hit (at 50 bits of offset - 62 bits of actual swap file coverage).
This is a preparatory change for the actual swap entry inversion to protect
against L1TF.
[ AK: Updated description and minor tweaks. Split into two parts ]
[ tglx: Massaged changelog ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Acked-by: Vlastimil Babka <vbabka@suse.cz>
Acked-by: Dave Hansen <dave.hansen@intel.com>
2018-06-14 06:48:22 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Shift the offset up "too far" by TYPE bits, then down again
|
2018-06-14 06:48:23 +08:00
|
|
|
* The offset is inverted by a binary not operation to make the high
|
|
|
|
* physical bits set.
|
x86/speculation/l1tf: Change order of offset/type in swap entry
If pages are swapped out, the swap entry is stored in the corresponding
PTE, which has the Present bit cleared. CPUs vulnerable to L1TF speculate
on PTE entries which have the present bit set and would treat the swap
entry as phsyical address (PFN). To mitigate that the upper bits of the PTE
must be set so the PTE points to non existent memory.
The swap entry stores the type and the offset of a swapped out page in the
PTE. type is stored in bit 9-13 and offset in bit 14-63. The hardware
ignores the bits beyond the phsyical address space limit, so to make the
mitigation effective its required to start 'offset' at the lowest possible
bit so that even large swap offsets do not reach into the physical address
space limit bits.
Move offset to bit 9-58 and type to bit 59-63 which are the bits that
hardware generally doesn't care about.
That, in turn, means that if you on desktop chip with only 40 bits of
physical addressing, now that the offset starts at bit 9, there needs to be
30 bits of offset actually *in use* until bit 39 ends up being set, which
means when inverted it will again point into existing memory.
So that's 4 terabyte of swap space (because the offset is counted in pages,
so 30 bits of offset is 42 bits of actual coverage). With bigger physical
addressing, that obviously grows further, until the limit of the offset is
hit (at 50 bits of offset - 62 bits of actual swap file coverage).
This is a preparatory change for the actual swap entry inversion to protect
against L1TF.
[ AK: Updated description and minor tweaks. Split into two parts ]
[ tglx: Massaged changelog ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Acked-by: Vlastimil Babka <vbabka@suse.cz>
Acked-by: Dave Hansen <dave.hansen@intel.com>
2018-06-14 06:48:22 +08:00
|
|
|
*/
|
|
|
|
#define __swp_entry(type, offset) ((swp_entry_t) { \
|
2018-06-14 06:48:23 +08:00
|
|
|
(~(unsigned long)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
|
x86/speculation/l1tf: Change order of offset/type in swap entry
If pages are swapped out, the swap entry is stored in the corresponding
PTE, which has the Present bit cleared. CPUs vulnerable to L1TF speculate
on PTE entries which have the present bit set and would treat the swap
entry as phsyical address (PFN). To mitigate that the upper bits of the PTE
must be set so the PTE points to non existent memory.
The swap entry stores the type and the offset of a swapped out page in the
PTE. type is stored in bit 9-13 and offset in bit 14-63. The hardware
ignores the bits beyond the phsyical address space limit, so to make the
mitigation effective its required to start 'offset' at the lowest possible
bit so that even large swap offsets do not reach into the physical address
space limit bits.
Move offset to bit 9-58 and type to bit 59-63 which are the bits that
hardware generally doesn't care about.
That, in turn, means that if you on desktop chip with only 40 bits of
physical addressing, now that the offset starts at bit 9, there needs to be
30 bits of offset actually *in use* until bit 39 ends up being set, which
means when inverted it will again point into existing memory.
So that's 4 terabyte of swap space (because the offset is counted in pages,
so 30 bits of offset is 42 bits of actual coverage). With bigger physical
addressing, that obviously grows further, until the limit of the offset is
hit (at 50 bits of offset - 62 bits of actual swap file coverage).
This is a preparatory change for the actual swap entry inversion to protect
against L1TF.
[ AK: Updated description and minor tweaks. Split into two parts ]
[ tglx: Massaged changelog ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Acked-by: Vlastimil Babka <vbabka@suse.cz>
Acked-by: Dave Hansen <dave.hansen@intel.com>
2018-06-14 06:48:22 +08:00
|
|
|
| ((unsigned long)(type) << (64-SWP_TYPE_BITS)) })
|
|
|
|
|
2008-03-23 16:03:11 +08:00
|
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) })
|
2017-09-09 07:10:57 +08:00
|
|
|
#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val((pmd)) })
|
2008-01-30 20:32:57 +08:00
|
|
|
#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
|
2017-09-09 07:10:57 +08:00
|
|
|
#define __swp_entry_to_pmd(x) ((pmd_t) { .pmd = (x).val })
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-03-23 16:03:11 +08:00
|
|
|
extern int kern_addr_valid(unsigned long addr);
|
2008-02-16 00:29:12 +08:00
|
|
|
extern void cleanup_highmap(void);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#define HAVE_ARCH_UNMAPPED_AREA
|
2008-01-30 20:31:07 +08:00
|
|
|
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#define PAGE_AGP PAGE_KERNEL_NOCACHE
|
|
|
|
#define HAVE_PAGE_AGP 1
|
|
|
|
|
|
|
|
/* fs/proc/kcore.c */
|
|
|
|
#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
|
x86, 64-bit: Clean up user address masking
The discussion about using "access_ok()" in get_user_pages_fast() (see
commit 7f8189068726492950bf1a2dcfd9b51314560abf: "x86: don't use
'access_ok()' as a range check in get_user_pages_fast()" for details and
end result), made us notice that x86-64 was really being very sloppy
about virtual address checking.
So be way more careful and straightforward about masking x86-64 virtual
addresses:
- All the VIRTUAL_MASK* variants now cover half of the address
space, it's not like we can use the full mask on a signed
integer, and the larger mask just invites mistakes when
applying it to either half of the 48-bit address space.
- /proc/kcore's kc_offset_to_vaddr() becomes a lot more
obvious when it transforms a file offset into a
(kernel-half) virtual address.
- Unify/simplify the 32-bit and 64-bit USER_DS definition to
be based on TASK_SIZE_MAX.
This cleanup and more careful/obvious user virtual address checking also
uncovered a buglet in the x86-64 implementation of strnlen_user(): it
would do an "access_ok()" check on the whole potential area, even if the
string itself was much shorter, and thus return an error even for valid
strings. Our sloppy checking had hidden this.
So this fixes 'strnlen_user()' to do this properly, the same way we
already handled user strings in 'strncpy_from_user()'. Namely by just
checking the first byte, and then relying on fault handling for the
rest. That always works, since we impose a guard page that cannot be
mapped at the end of the user space address space (and even if we
didn't, we'd have the address space hole).
Acked-by: Ingo Molnar <mingo@elte.hu>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Nick Piggin <npiggin@suse.de>
Cc: Hugh Dickins <hugh.dickins@tiscali.co.uk>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-06-21 06:40:00 +08:00
|
|
|
#define kc_offset_to_vaddr(o) ((o) | ~__VIRTUAL_MASK)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTE_SAME
|
2011-01-14 07:46:40 +08:00
|
|
|
|
2012-11-17 05:53:09 +08:00
|
|
|
#define vmemmap ((struct page *)VMEMMAP_START)
|
|
|
|
|
|
|
|
extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
|
|
|
|
extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
|
|
|
|
|
2017-06-06 19:31:20 +08:00
|
|
|
#define gup_fast_permitted gup_fast_permitted
|
2019-07-12 11:56:45 +08:00
|
|
|
static inline bool gup_fast_permitted(unsigned long start, unsigned long end)
|
2017-06-06 19:31:20 +08:00
|
|
|
{
|
|
|
|
if (end >> __VIRTUAL_MASK_SHIFT)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
2017-04-23 17:37:17 +08:00
|
|
|
|
2018-06-14 06:48:24 +08:00
|
|
|
#include <asm/pgtable-invert.h>
|
|
|
|
|
2017-06-06 19:31:20 +08:00
|
|
|
#endif /* !__ASSEMBLY__ */
|
2008-10-23 13:26:29 +08:00
|
|
|
#endif /* _ASM_X86_PGTABLE_64_H */
|