2023-07-11 20:10:47 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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* Copyright (C) 2023 Ventana Micro Systems Inc.
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*
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* Authors:
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* Anup Patel <apatel@ventanamicro.com>
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/uaccess.h>
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#include <linux/kvm_host.h>
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#include <asm/cacheflush.h>
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#include <asm/hwcap.h>
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#include <asm/kvm_vcpu_vector.h>
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#include <asm/vector.h>
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#define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0)
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#define KVM_ISA_EXT_ARR(ext) \
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[KVM_RISCV_ISA_EXT_##ext] = RISCV_ISA_EXT_##ext
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/* Mapping between KVM ISA Extension ID & Host ISA extension ID */
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static const unsigned long kvm_isa_ext_arr[] = {
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2023-07-12 18:03:12 +08:00
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/* Single letter extensions (alphabetically sorted) */
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2023-07-11 20:10:47 +08:00
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[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
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[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
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[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
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[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
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[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
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[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
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[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
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[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
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2023-07-12 18:03:12 +08:00
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/* Multi letter extensions (alphabetically sorted) */
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2023-07-11 20:10:47 +08:00
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KVM_ISA_EXT_ARR(SSAIA),
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KVM_ISA_EXT_ARR(SSTC),
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KVM_ISA_EXT_ARR(SVINVAL),
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KVM_ISA_EXT_ARR(SVNAPOT),
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KVM_ISA_EXT_ARR(SVPBMT),
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2023-07-12 15:08:11 +08:00
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KVM_ISA_EXT_ARR(ZBA),
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2023-07-11 20:10:47 +08:00
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KVM_ISA_EXT_ARR(ZBB),
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KVM_ISA_EXT_ARR(ZBS),
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KVM_ISA_EXT_ARR(ZICBOM),
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KVM_ISA_EXT_ARR(ZICBOZ),
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2023-07-12 15:23:50 +08:00
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KVM_ISA_EXT_ARR(ZICNTR),
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KVM_ISA_EXT_ARR(ZICSR),
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KVM_ISA_EXT_ARR(ZIFENCEI),
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2023-07-11 20:10:47 +08:00
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KVM_ISA_EXT_ARR(ZIHINTPAUSE),
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KVM_ISA_EXT_ARR(ZIHPM),
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2023-07-11 20:10:47 +08:00
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};
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static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
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{
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unsigned long i;
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for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
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if (kvm_isa_ext_arr[i] == base_ext)
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return i;
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}
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return KVM_RISCV_ISA_EXT_MAX;
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}
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static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_H:
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return false;
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case KVM_RISCV_ISA_EXT_V:
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return riscv_v_vstate_ctrl_user_allowed();
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default:
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break;
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}
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return true;
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}
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static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_A:
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case KVM_RISCV_ISA_EXT_C:
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case KVM_RISCV_ISA_EXT_I:
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case KVM_RISCV_ISA_EXT_M:
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case KVM_RISCV_ISA_EXT_SSAIA:
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case KVM_RISCV_ISA_EXT_SSTC:
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case KVM_RISCV_ISA_EXT_SVINVAL:
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case KVM_RISCV_ISA_EXT_SVNAPOT:
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2023-07-12 18:03:12 +08:00
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case KVM_RISCV_ISA_EXT_ZBA:
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case KVM_RISCV_ISA_EXT_ZBB:
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case KVM_RISCV_ISA_EXT_ZBS:
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2023-07-12 15:23:50 +08:00
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case KVM_RISCV_ISA_EXT_ZICNTR:
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case KVM_RISCV_ISA_EXT_ZICSR:
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case KVM_RISCV_ISA_EXT_ZIFENCEI:
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2023-07-11 20:10:47 +08:00
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case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
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2023-07-12 15:23:50 +08:00
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case KVM_RISCV_ISA_EXT_ZIHPM:
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2023-07-11 20:10:47 +08:00
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return false;
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default:
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break;
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}
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return true;
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}
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void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu)
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{
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unsigned long host_isa, i;
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for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
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host_isa = kvm_isa_ext_arr[i];
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if (__riscv_isa_extension_available(NULL, host_isa) &&
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kvm_riscv_vcpu_isa_enable_allowed(i))
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set_bit(host_isa, vcpu->arch.isa);
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}
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}
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static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
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2023-08-04 00:32:54 +08:00
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return -ENOENT;
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2023-07-11 20:10:47 +08:00
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reg_val = riscv_cbom_block_size;
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
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2023-08-04 00:32:54 +08:00
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return -ENOENT;
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2023-07-11 20:10:47 +08:00
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reg_val = riscv_cboz_block_size;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mvendorid):
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reg_val = vcpu->arch.mvendorid;
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break;
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case KVM_REG_RISCV_CONFIG_REG(marchid):
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reg_val = vcpu->arch.marchid;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mimpid):
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reg_val = vcpu->arch.mimpid;
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break;
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2023-07-29 05:01:22 +08:00
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case KVM_REG_RISCV_CONFIG_REG(satp_mode):
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reg_val = satp_mode >> SATP_MODE_SHIFT;
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break;
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2023-07-11 20:10:47 +08:00
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default:
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2023-08-04 00:32:53 +08:00
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return -ENOENT;
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2023-07-11 20:10:47 +08:00
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}
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long i, isa_ext, reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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/*
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* This ONE REG interface is only defined for
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* single letter extensions.
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*/
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if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
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return -EINVAL;
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2023-08-04 00:32:58 +08:00
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/*
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* Return early (i.e. do nothing) if reg_val is the same
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* value retrievable via kvm_riscv_vcpu_get_reg_config().
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*/
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if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK))
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break;
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2023-07-11 20:10:47 +08:00
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if (!vcpu->arch.ran_atleast_once) {
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/* Ignore the enable/disable request for certain extensions */
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for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
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isa_ext = kvm_riscv_vcpu_base2isa_ext(i);
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if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) {
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reg_val &= ~BIT(i);
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continue;
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}
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if (!kvm_riscv_vcpu_isa_enable_allowed(isa_ext))
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if (reg_val & BIT(i))
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reg_val &= ~BIT(i);
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if (!kvm_riscv_vcpu_isa_disable_allowed(isa_ext))
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if (!(reg_val & BIT(i)))
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reg_val |= BIT(i);
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}
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reg_val &= riscv_isa_extension_base(NULL);
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/* Do not modify anything beyond single letter extensions */
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reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |
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(reg_val & KVM_RISCV_BASE_ISA_MASK);
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vcpu->arch.isa[0] = reg_val;
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kvm_riscv_vcpu_fp_reset(vcpu);
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} else {
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2023-08-04 00:32:57 +08:00
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return -EBUSY;
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2023-07-11 20:10:47 +08:00
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}
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
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2023-08-04 00:32:55 +08:00
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
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return -ENOENT;
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if (reg_val != riscv_cbom_block_size)
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return -EINVAL;
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break;
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2023-07-11 20:10:47 +08:00
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case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
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2023-08-04 00:32:55 +08:00
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
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return -ENOENT;
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if (reg_val != riscv_cboz_block_size)
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return -EINVAL;
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break;
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2023-07-11 20:10:47 +08:00
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case KVM_REG_RISCV_CONFIG_REG(mvendorid):
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2023-08-04 00:32:59 +08:00
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if (reg_val == vcpu->arch.mvendorid)
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break;
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2023-07-11 20:10:47 +08:00
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.mvendorid = reg_val;
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else
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return -EBUSY;
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break;
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case KVM_REG_RISCV_CONFIG_REG(marchid):
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2023-08-04 00:32:59 +08:00
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if (reg_val == vcpu->arch.marchid)
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break;
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2023-07-11 20:10:47 +08:00
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.marchid = reg_val;
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else
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return -EBUSY;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mimpid):
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2023-08-04 00:32:59 +08:00
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if (reg_val == vcpu->arch.mimpid)
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break;
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2023-07-11 20:10:47 +08:00
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.mimpid = reg_val;
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else
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return -EBUSY;
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break;
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2023-07-29 05:01:22 +08:00
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case KVM_REG_RISCV_CONFIG_REG(satp_mode):
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if (reg_val != (satp_mode >> SATP_MODE_SHIFT))
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return -EINVAL;
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break;
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2023-07-11 20:10:47 +08:00
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default:
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2023-08-04 00:32:53 +08:00
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return -ENOENT;
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2023-07-11 20:10:47 +08:00
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}
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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2023-08-04 00:32:53 +08:00
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return -ENOENT;
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2023-07-11 20:10:47 +08:00
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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reg_val = cntx->sepc;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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reg_val = ((unsigned long *)cntx)[reg_num];
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
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reg_val = (cntx->sstatus & SR_SPP) ?
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KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
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else
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2023-08-04 00:32:53 +08:00
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return -ENOENT;
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2023-07-11 20:10:47 +08:00
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
|
|
|
|
unsigned long __user *uaddr =
|
|
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
|
|
KVM_REG_SIZE_MASK |
|
|
|
|
KVM_REG_RISCV_CORE);
|
|
|
|
unsigned long reg_val;
|
|
|
|
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
|
|
return -EINVAL;
|
|
|
|
if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
|
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
|
|
|
|
cntx->sepc = reg_val;
|
|
|
|
else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
|
|
|
|
reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
|
|
|
|
((unsigned long *)cntx)[reg_num] = reg_val;
|
|
|
|
else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
|
|
|
|
if (reg_val == KVM_RISCV_MODE_S)
|
|
|
|
cntx->sstatus |= SR_SPP;
|
|
|
|
else
|
|
|
|
cntx->sstatus &= ~SR_SPP;
|
|
|
|
} else
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long reg_num,
|
|
|
|
unsigned long *out_val)
|
|
|
|
{
|
|
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
|
|
|
|
if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
|
|
|
if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
|
|
|
|
kvm_riscv_vcpu_flush_interrupts(vcpu);
|
|
|
|
*out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
|
|
|
|
*out_val |= csr->hvip & ~IRQ_LOCAL_MASK;
|
|
|
|
} else
|
|
|
|
*out_val = ((unsigned long *)csr)[reg_num];
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long reg_num,
|
|
|
|
unsigned long reg_val)
|
|
|
|
{
|
|
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
|
|
|
|
if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
|
|
|
if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
|
|
|
|
reg_val &= VSIP_VALID_MASK;
|
|
|
|
reg_val <<= VSIP_TO_HVIP_SHIFT;
|
|
|
|
}
|
|
|
|
|
|
|
|
((unsigned long *)csr)[reg_num] = reg_val;
|
|
|
|
|
|
|
|
if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
|
|
|
|
WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
unsigned long __user *uaddr =
|
|
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
|
|
KVM_REG_SIZE_MASK |
|
|
|
|
KVM_REG_RISCV_CSR);
|
|
|
|
unsigned long reg_val, reg_subtype;
|
|
|
|
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
switch (reg_subtype) {
|
|
|
|
case KVM_REG_RISCV_CSR_GENERAL:
|
|
|
|
rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, ®_val);
|
|
|
|
break;
|
|
|
|
case KVM_REG_RISCV_CSR_AIA:
|
|
|
|
rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, ®_val);
|
|
|
|
break;
|
|
|
|
default:
|
2023-08-04 00:32:53 +08:00
|
|
|
rc = -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
unsigned long __user *uaddr =
|
|
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
|
|
KVM_REG_SIZE_MASK |
|
|
|
|
KVM_REG_RISCV_CSR);
|
|
|
|
unsigned long reg_val, reg_subtype;
|
|
|
|
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
switch (reg_subtype) {
|
|
|
|
case KVM_REG_RISCV_CSR_GENERAL:
|
|
|
|
rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);
|
|
|
|
break;
|
|
|
|
case KVM_REG_RISCV_CSR_AIA:
|
|
|
|
rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);
|
|
|
|
break;
|
|
|
|
default:
|
2023-08-04 00:32:53 +08:00
|
|
|
rc = -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-07-12 00:41:16 +08:00
|
|
|
static int riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long reg_num,
|
|
|
|
unsigned long *reg_val)
|
2023-07-11 20:10:47 +08:00
|
|
|
{
|
|
|
|
unsigned long host_isa_ext;
|
|
|
|
|
|
|
|
if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
|
|
|
|
reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
2023-07-12 00:41:16 +08:00
|
|
|
*reg_val = 0;
|
2023-07-11 20:10:47 +08:00
|
|
|
host_isa_ext = kvm_isa_ext_arr[reg_num];
|
|
|
|
if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext))
|
2023-07-12 00:41:16 +08:00
|
|
|
*reg_val = 1; /* Mark the given extension as available */
|
2023-07-11 20:10:47 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-07-12 00:41:16 +08:00
|
|
|
static int riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long reg_num,
|
|
|
|
unsigned long reg_val)
|
2023-07-11 20:10:47 +08:00
|
|
|
{
|
|
|
|
unsigned long host_isa_ext;
|
|
|
|
|
|
|
|
if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
|
|
|
|
reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
|
|
|
host_isa_ext = kvm_isa_ext_arr[reg_num];
|
|
|
|
if (!__riscv_isa_extension_available(NULL, host_isa_ext))
|
2023-08-04 00:32:54 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
|
2023-08-04 00:33:00 +08:00
|
|
|
if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa))
|
|
|
|
return 0;
|
|
|
|
|
2023-07-11 20:10:47 +08:00
|
|
|
if (!vcpu->arch.ran_atleast_once) {
|
|
|
|
/*
|
|
|
|
* All multi-letter extension and a few single letter
|
|
|
|
* extension can be disabled
|
|
|
|
*/
|
|
|
|
if (reg_val == 1 &&
|
|
|
|
kvm_riscv_vcpu_isa_enable_allowed(reg_num))
|
|
|
|
set_bit(host_isa_ext, vcpu->arch.isa);
|
|
|
|
else if (!reg_val &&
|
|
|
|
kvm_riscv_vcpu_isa_disable_allowed(reg_num))
|
|
|
|
clear_bit(host_isa_ext, vcpu->arch.isa);
|
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
kvm_riscv_vcpu_fp_reset(vcpu);
|
|
|
|
} else {
|
2023-08-04 00:32:57 +08:00
|
|
|
return -EBUSY;
|
2023-07-11 20:10:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-07-12 00:41:16 +08:00
|
|
|
static int riscv_vcpu_get_isa_ext_multi(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long reg_num,
|
|
|
|
unsigned long *reg_val)
|
|
|
|
{
|
|
|
|
unsigned long i, ext_id, ext_val;
|
|
|
|
|
|
|
|
if (reg_num > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-12 00:41:16 +08:00
|
|
|
|
|
|
|
for (i = 0; i < BITS_PER_LONG; i++) {
|
|
|
|
ext_id = i + reg_num * BITS_PER_LONG;
|
|
|
|
if (ext_id >= KVM_RISCV_ISA_EXT_MAX)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ext_val = 0;
|
|
|
|
riscv_vcpu_get_isa_ext_single(vcpu, ext_id, &ext_val);
|
|
|
|
if (ext_val)
|
|
|
|
*reg_val |= KVM_REG_RISCV_ISA_MULTI_MASK(ext_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int riscv_vcpu_set_isa_ext_multi(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long reg_num,
|
|
|
|
unsigned long reg_val, bool enable)
|
|
|
|
{
|
|
|
|
unsigned long i, ext_id;
|
|
|
|
|
|
|
|
if (reg_num > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-12 00:41:16 +08:00
|
|
|
|
|
|
|
for_each_set_bit(i, ®_val, BITS_PER_LONG) {
|
|
|
|
ext_id = i + reg_num * BITS_PER_LONG;
|
|
|
|
if (ext_id >= KVM_RISCV_ISA_EXT_MAX)
|
|
|
|
break;
|
|
|
|
|
|
|
|
riscv_vcpu_set_isa_ext_single(vcpu, ext_id, enable);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
unsigned long __user *uaddr =
|
|
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
|
|
KVM_REG_SIZE_MASK |
|
|
|
|
KVM_REG_RISCV_ISA_EXT);
|
|
|
|
unsigned long reg_val, reg_subtype;
|
|
|
|
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
|
|
|
|
reg_val = 0;
|
|
|
|
switch (reg_subtype) {
|
|
|
|
case KVM_REG_RISCV_ISA_SINGLE:
|
|
|
|
rc = riscv_vcpu_get_isa_ext_single(vcpu, reg_num, ®_val);
|
|
|
|
break;
|
|
|
|
case KVM_REG_RISCV_ISA_MULTI_EN:
|
|
|
|
case KVM_REG_RISCV_ISA_MULTI_DIS:
|
|
|
|
rc = riscv_vcpu_get_isa_ext_multi(vcpu, reg_num, ®_val);
|
|
|
|
if (!rc && reg_subtype == KVM_REG_RISCV_ISA_MULTI_DIS)
|
|
|
|
reg_val = ~reg_val;
|
|
|
|
break;
|
|
|
|
default:
|
2023-08-04 00:32:53 +08:00
|
|
|
rc = -ENOENT;
|
2023-07-12 00:41:16 +08:00
|
|
|
}
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
unsigned long __user *uaddr =
|
|
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
|
|
KVM_REG_SIZE_MASK |
|
|
|
|
KVM_REG_RISCV_ISA_EXT);
|
|
|
|
unsigned long reg_val, reg_subtype;
|
|
|
|
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
|
|
|
|
|
|
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
switch (reg_subtype) {
|
|
|
|
case KVM_REG_RISCV_ISA_SINGLE:
|
|
|
|
return riscv_vcpu_set_isa_ext_single(vcpu, reg_num, reg_val);
|
|
|
|
case KVM_REG_RISCV_SBI_MULTI_EN:
|
|
|
|
return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, true);
|
|
|
|
case KVM_REG_RISCV_SBI_MULTI_DIS:
|
|
|
|
return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false);
|
|
|
|
default:
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-12 00:41:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-07-25 16:41:38 +08:00
|
|
|
static int copy_config_reg_indices(const struct kvm_vcpu *vcpu,
|
|
|
|
u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int n = 0;
|
|
|
|
|
|
|
|
for (int i = 0; i < sizeof(struct kvm_riscv_config)/sizeof(unsigned long);
|
|
|
|
i++) {
|
|
|
|
u64 size;
|
|
|
|
u64 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Avoid reporting config reg if the corresponding extension
|
|
|
|
* was not available.
|
|
|
|
*/
|
|
|
|
if (i == KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) &&
|
|
|
|
!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
|
|
|
|
continue;
|
|
|
|
else if (i == KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) &&
|
|
|
|
!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CONFIG | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long num_config_regs(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return copy_config_reg_indices(vcpu, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_core_regs(void)
|
|
|
|
{
|
|
|
|
return sizeof(struct kvm_riscv_core) / sizeof(unsigned long);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_core_reg_indices(u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int n = num_core_regs();
|
|
|
|
|
|
|
|
for (int i = 0; i < n; i++) {
|
|
|
|
u64 size = IS_ENABLED(CONFIG_32BIT) ?
|
|
|
|
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CORE | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_csr_regs(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
unsigned long n = sizeof(struct kvm_riscv_csr) / sizeof(unsigned long);
|
|
|
|
|
|
|
|
if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA))
|
|
|
|
n += sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long);
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_csr_reg_indices(const struct kvm_vcpu *vcpu,
|
|
|
|
u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int n1 = sizeof(struct kvm_riscv_csr) / sizeof(unsigned long);
|
|
|
|
int n2 = 0;
|
|
|
|
|
|
|
|
/* copy general csr regs */
|
|
|
|
for (int i = 0; i < n1; i++) {
|
|
|
|
u64 size = IS_ENABLED(CONFIG_32BIT) ?
|
|
|
|
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR |
|
|
|
|
KVM_REG_RISCV_CSR_GENERAL | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copy AIA csr regs */
|
|
|
|
if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) {
|
|
|
|
n2 = sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long);
|
|
|
|
|
|
|
|
for (int i = 0; i < n2; i++) {
|
|
|
|
u64 size = IS_ENABLED(CONFIG_32BIT) ?
|
|
|
|
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR |
|
|
|
|
KVM_REG_RISCV_CSR_AIA | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return n1 + n2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_timer_regs(void)
|
|
|
|
{
|
|
|
|
return sizeof(struct kvm_riscv_timer) / sizeof(u64);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_timer_reg_indices(u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int n = num_timer_regs();
|
|
|
|
|
|
|
|
for (int i = 0; i < n; i++) {
|
|
|
|
u64 reg = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
|
|
|
|
KVM_REG_RISCV_TIMER | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_fp_f_regs(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
|
|
|
|
|
|
|
|
if (riscv_isa_extension_available(vcpu->arch.isa, f))
|
|
|
|
return sizeof(cntx->fp.f) / sizeof(u32);
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_fp_f_reg_indices(const struct kvm_vcpu *vcpu,
|
|
|
|
u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int n = num_fp_f_regs(vcpu);
|
|
|
|
|
|
|
|
for (int i = 0; i < n; i++) {
|
|
|
|
u64 reg = KVM_REG_RISCV | KVM_REG_SIZE_U32 |
|
|
|
|
KVM_REG_RISCV_FP_F | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_fp_d_regs(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
|
|
|
|
|
|
|
|
if (riscv_isa_extension_available(vcpu->arch.isa, d))
|
|
|
|
return sizeof(cntx->fp.d.f) / sizeof(u64) + 1;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_fp_d_reg_indices(const struct kvm_vcpu *vcpu,
|
|
|
|
u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int n = num_fp_d_regs(vcpu);
|
|
|
|
u64 reg;
|
|
|
|
|
|
|
|
/* copy fp.d.f indices */
|
|
|
|
for (i = 0; i < n-1; i++) {
|
|
|
|
reg = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
|
|
|
|
KVM_REG_RISCV_FP_D | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copy fp.d.fcsr indices */
|
|
|
|
reg = KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | i;
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu,
|
|
|
|
u64 __user *uindices)
|
|
|
|
{
|
|
|
|
unsigned int n = 0;
|
|
|
|
unsigned long isa_ext;
|
|
|
|
|
|
|
|
for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
|
|
|
|
u64 size = IS_ENABLED(CONFIG_32BIT) ?
|
|
|
|
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i;
|
|
|
|
|
|
|
|
isa_ext = kvm_isa_ext_arr[i];
|
|
|
|
if (!__riscv_isa_extension_available(vcpu->arch.isa, isa_ext))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_isa_ext_regs(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return copy_isa_ext_reg_indices(vcpu, NULL);;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long num_sbi_ext_regs(void)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* number of KVM_REG_RISCV_SBI_SINGLE +
|
|
|
|
* 2 x (number of KVM_REG_RISCV_SBI_MULTI)
|
|
|
|
*/
|
|
|
|
return KVM_RISCV_SBI_EXT_MAX + 2*(KVM_REG_RISCV_SBI_MULTI_REG_LAST+1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int copy_sbi_ext_reg_indices(u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int n;
|
|
|
|
|
|
|
|
/* copy KVM_REG_RISCV_SBI_SINGLE */
|
|
|
|
n = KVM_RISCV_SBI_EXT_MAX;
|
|
|
|
for (int i = 0; i < n; i++) {
|
|
|
|
u64 size = IS_ENABLED(CONFIG_32BIT) ?
|
|
|
|
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
|
|
|
|
KVM_REG_RISCV_SBI_SINGLE | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copy KVM_REG_RISCV_SBI_MULTI */
|
|
|
|
n = KVM_REG_RISCV_SBI_MULTI_REG_LAST + 1;
|
|
|
|
for (int i = 0; i < n; i++) {
|
|
|
|
u64 size = IS_ENABLED(CONFIG_32BIT) ?
|
|
|
|
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
|
|
|
|
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
|
|
|
|
KVM_REG_RISCV_SBI_MULTI_EN | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg = KVM_REG_RISCV | size | KVM_REG_RISCV_SBI_EXT |
|
|
|
|
KVM_REG_RISCV_SBI_MULTI_DIS | i;
|
|
|
|
|
|
|
|
if (uindices) {
|
|
|
|
if (put_user(reg, uindices))
|
|
|
|
return -EFAULT;
|
|
|
|
uindices++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return num_sbi_ext_regs();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
|
|
|
|
*
|
|
|
|
* This is for all registers.
|
|
|
|
*/
|
|
|
|
unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
unsigned long res = 0;
|
|
|
|
|
|
|
|
res += num_config_regs(vcpu);
|
|
|
|
res += num_core_regs();
|
|
|
|
res += num_csr_regs(vcpu);
|
|
|
|
res += num_timer_regs();
|
|
|
|
res += num_fp_f_regs(vcpu);
|
|
|
|
res += num_fp_d_regs(vcpu);
|
|
|
|
res += num_isa_ext_regs(vcpu);
|
|
|
|
res += num_sbi_ext_regs();
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* kvm_riscv_vcpu_copy_reg_indices - get indices of all registers.
|
|
|
|
*/
|
|
|
|
int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,
|
|
|
|
u64 __user *uindices)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = copy_config_reg_indices(vcpu, uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_core_reg_indices(uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_csr_reg_indices(vcpu, uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_timer_reg_indices(uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_fp_f_reg_indices(vcpu, uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_fp_d_reg_indices(vcpu, uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_isa_ext_reg_indices(vcpu, uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
uindices += ret;
|
|
|
|
|
|
|
|
ret = copy_sbi_ext_reg_indices(uindices);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-07-11 20:10:47 +08:00
|
|
|
int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
|
|
|
|
case KVM_REG_RISCV_CONFIG:
|
|
|
|
return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_CORE:
|
|
|
|
return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_CSR:
|
|
|
|
return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_TIMER:
|
|
|
|
return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_FP_F:
|
|
|
|
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
|
|
|
|
KVM_REG_RISCV_FP_F);
|
|
|
|
case KVM_REG_RISCV_FP_D:
|
|
|
|
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
|
|
|
|
KVM_REG_RISCV_FP_D);
|
|
|
|
case KVM_REG_RISCV_ISA_EXT:
|
|
|
|
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_SBI_EXT:
|
|
|
|
return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_VECTOR:
|
2023-08-04 21:56:18 +08:00
|
|
|
return kvm_riscv_vcpu_set_reg_vector(vcpu, reg);
|
2023-07-11 20:10:47 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
|
|
|
|
const struct kvm_one_reg *reg)
|
|
|
|
{
|
|
|
|
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
|
|
|
|
case KVM_REG_RISCV_CONFIG:
|
|
|
|
return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_CORE:
|
|
|
|
return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_CSR:
|
|
|
|
return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_TIMER:
|
|
|
|
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_FP_F:
|
|
|
|
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
|
|
|
|
KVM_REG_RISCV_FP_F);
|
|
|
|
case KVM_REG_RISCV_FP_D:
|
|
|
|
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
|
|
|
|
KVM_REG_RISCV_FP_D);
|
|
|
|
case KVM_REG_RISCV_ISA_EXT:
|
|
|
|
return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_SBI_EXT:
|
|
|
|
return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg);
|
|
|
|
case KVM_REG_RISCV_VECTOR:
|
2023-08-04 21:56:18 +08:00
|
|
|
return kvm_riscv_vcpu_get_reg_vector(vcpu, reg);
|
2023-07-11 20:10:47 +08:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2023-08-04 00:32:53 +08:00
|
|
|
return -ENOENT;
|
2023-07-11 20:10:47 +08:00
|
|
|
}
|