2019-05-27 14:55:05 +08:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2009-01-20 14:15:18 +08:00
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/*
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* linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
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*
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* PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core.
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*
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* Heavily based on proc-arm926.S and proc-xsc3.S
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be flushed. If the
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* area is larger than this, then we flush the whole cache.
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*/
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#define CACHE_DLIMIT 32768
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/*
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* The cache line size of the L1 D cache.
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*/
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#define CACHE_DLINESIZE 32
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/*
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* cpu_mohawk_proc_init()
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*/
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ENTRY(cpu_mohawk_proc_init)
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* cpu_mohawk_proc_fin()
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*/
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ENTRY(cpu_mohawk_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1800 @ ...iz...........
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* cpu_mohawk_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*
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* (same as arm926)
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*/
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.align 5
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2011-11-15 21:25:04 +08:00
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.pushsection .idmap.text, "ax"
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2009-01-20 14:15:18 +08:00
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ENTRY(cpu_mohawk_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x0007 @ .............cam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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2014-06-30 23:29:12 +08:00
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ret r0
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2011-11-15 21:25:04 +08:00
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ENDPROC(cpu_mohawk_reset)
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.popsection
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2009-01-20 14:15:18 +08:00
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/*
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* cpu_mohawk_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 5
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ENTRY(cpu_mohawk_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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2011-06-24 00:22:29 +08:00
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(mohawk_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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2014-06-30 23:29:12 +08:00
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ret lr
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2011-06-24 00:22:29 +08:00
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ENDPROC(mohawk_flush_icache_all)
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2009-01-20 14:15:18 +08:00
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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ENTRY(mohawk_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(mohawk_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*
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* (same as arm926)
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*/
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ENTRY(mohawk_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(mohawk_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as arm926)
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*/
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ENTRY(mohawk_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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2012-04-27 20:08:53 +08:00
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mov r0, #0
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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2009-11-26 20:56:21 +08:00
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* flush_kern_dcache_area(void *addr, size_t size)
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2009-01-20 14:15:18 +08:00
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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2009-11-26 20:56:21 +08:00
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* - addr - kernel address
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* - size - region size
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2009-01-20 14:15:18 +08:00
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*/
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2009-11-26 20:56:21 +08:00
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ENTRY(mohawk_flush_kern_dcache_area)
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add r1, r0, r1
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2009-01-20 14:15:18 +08:00
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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2009-11-27 00:24:19 +08:00
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mohawk_dma_inv_range:
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2009-01-20 14:15:18 +08:00
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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2009-11-27 00:24:19 +08:00
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mohawk_dma_clean_range:
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2009-01-20 14:15:18 +08:00
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(mohawk_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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2009-11-27 00:19:58 +08:00
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(mohawk_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq mohawk_dma_clean_range
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bcs mohawk_dma_inv_range
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b mohawk_dma_flush_range
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ENDPROC(mohawk_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(mohawk_dma_unmap_area)
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-11-27 00:19:58 +08:00
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ENDPROC(mohawk_dma_unmap_area)
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2012-09-06 21:05:13 +08:00
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.globl mohawk_flush_kern_cache_louis
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.equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
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2011-06-24 00:22:29 +08:00
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions mohawk
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2009-01-20 14:15:18 +08:00
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ENTRY(cpu_mohawk_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* cpu_mohawk_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_mohawk_switch_mm)
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mov ip, #0
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mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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orr r0, r0, #0x18 @ cache the page table in L2
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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2014-06-30 23:29:12 +08:00
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ret lr
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2009-01-20 14:15:18 +08:00
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/*
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* cpu_mohawk_set_pte_ext(ptep, pte, ext)
|
|
|
|
*
|
|
|
|
* Set a PTE and flush it out
|
|
|
|
*/
|
|
|
|
.align 5
|
|
|
|
ENTRY(cpu_mohawk_set_pte_ext)
|
2014-04-16 15:54:02 +08:00
|
|
|
#ifdef CONFIG_MMU
|
2009-01-20 14:15:18 +08:00
|
|
|
armv3_set_pte_ext
|
|
|
|
mov r0, r0
|
|
|
|
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
2014-06-30 23:29:12 +08:00
|
|
|
ret lr
|
2014-04-16 15:54:02 +08:00
|
|
|
#endif
|
2009-01-20 14:15:18 +08:00
|
|
|
|
2012-05-07 11:23:58 +08:00
|
|
|
.globl cpu_mohawk_suspend_size
|
|
|
|
.equ cpu_mohawk_suspend_size, 4 * 6
|
2013-04-08 18:44:57 +08:00
|
|
|
#ifdef CONFIG_ARM_CPU_SUSPEND
|
2012-05-07 11:23:58 +08:00
|
|
|
ENTRY(cpu_mohawk_do_suspend)
|
|
|
|
stmfd sp!, {r4 - r9, lr}
|
|
|
|
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
|
|
|
|
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
|
|
|
mrc p15, 0, r6, c13, c0, 0 @ PID
|
|
|
|
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
|
|
|
mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
|
|
|
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
|
|
|
bic r4, r4, #2 @ clear frequency change bit
|
|
|
|
stmia r0, {r4 - r9} @ store cp regs
|
|
|
|
ldmia sp!, {r4 - r9, pc}
|
|
|
|
ENDPROC(cpu_mohawk_do_suspend)
|
|
|
|
|
|
|
|
ENTRY(cpu_mohawk_do_resume)
|
|
|
|
ldmia r0, {r4 - r9} @ load cp regs
|
|
|
|
mov ip, #0
|
|
|
|
mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
|
|
|
|
mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
|
|
|
|
mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
|
|
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
|
|
|
mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
|
|
|
|
mcr p15, 0, r5, c15, c1, 0 @ CP access reg
|
|
|
|
mcr p15, 0, r6, c13, c0, 0 @ PID
|
|
|
|
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
|
|
|
orr r1, r1, #0x18 @ cache the page table in L2
|
|
|
|
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
|
|
|
mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
|
|
|
mov r0, r9 @ control register
|
|
|
|
b cpu_resume_mmu
|
|
|
|
ENDPROC(cpu_mohawk_do_resume)
|
|
|
|
#endif
|
|
|
|
|
2009-01-20 14:15:18 +08:00
|
|
|
.type __mohawk_setup, #function
|
|
|
|
__mohawk_setup:
|
|
|
|
mov r0, #0
|
|
|
|
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
|
|
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
|
|
|
|
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
|
|
|
|
orr r4, r4, #0x18 @ cache the page table in L2
|
|
|
|
mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
|
|
|
|
|
|
|
|
mov r0, #0 @ don't allow CP access
|
|
|
|
mcr p15, 0, r0, c15, c1, 0 @ write CP access register
|
|
|
|
|
|
|
|
adr r5, mohawk_crval
|
|
|
|
ldmia r5, {r5, r6}
|
|
|
|
mrc p15, 0, r0, c1, c0 @ get control register
|
|
|
|
bic r0, r0, r5
|
|
|
|
orr r0, r0, r6
|
2014-06-30 23:29:12 +08:00
|
|
|
ret lr
|
2009-01-20 14:15:18 +08:00
|
|
|
|
|
|
|
.size __mohawk_setup, . - __mohawk_setup
|
|
|
|
|
|
|
|
/*
|
|
|
|
* R
|
|
|
|
* .RVI ZFRS BLDP WCAM
|
|
|
|
* .011 1001 ..00 0101
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
.type mohawk_crval, #object
|
|
|
|
mohawk_crval:
|
|
|
|
crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134
|
|
|
|
|
|
|
|
__INITDATA
|
|
|
|
|
2011-06-24 00:22:29 +08:00
|
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
|
|
|
define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
|
2009-01-20 14:15:18 +08:00
|
|
|
|
|
|
|
.section ".rodata"
|
|
|
|
|
2011-06-24 00:22:29 +08:00
|
|
|
string cpu_arch_name, "armv5te"
|
|
|
|
string cpu_elf_name, "v5"
|
|
|
|
string cpu_mohawk_name, "Marvell 88SV331x"
|
2009-01-20 14:15:18 +08:00
|
|
|
|
|
|
|
.align
|
|
|
|
|
2019-11-05 02:31:45 +08:00
|
|
|
.section ".proc.info.init", "a"
|
2009-01-20 14:15:18 +08:00
|
|
|
|
|
|
|
.type __88sv331x_proc_info,#object
|
|
|
|
__88sv331x_proc_info:
|
|
|
|
.long 0x56158000 @ Marvell 88SV331x (MOHAWK)
|
|
|
|
.long 0xfffff000
|
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_SECT_BUFFERABLE | \
|
|
|
|
PMD_SECT_CACHEABLE | \
|
|
|
|
PMD_BIT4 | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
|
|
|
.long PMD_TYPE_SECT | \
|
|
|
|
PMD_BIT4 | \
|
|
|
|
PMD_SECT_AP_WRITE | \
|
|
|
|
PMD_SECT_AP_READ
|
2015-03-18 14:29:32 +08:00
|
|
|
initfn __mohawk_setup, __88sv331x_proc_info
|
2009-01-20 14:15:18 +08:00
|
|
|
.long cpu_arch_name
|
|
|
|
.long cpu_elf_name
|
|
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
|
|
.long cpu_mohawk_name
|
|
|
|
.long mohawk_processor_functions
|
|
|
|
.long v4wbi_tlb_fns
|
|
|
|
.long v4wb_user_fns
|
|
|
|
.long mohawk_cache_fns
|
|
|
|
.size __88sv331x_proc_info, . - __88sv331x_proc_info
|