2018-03-28 23:46:15 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2015-09-22 20:47:14 +08:00
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/*
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* Intel(R) Trace Hub data structures
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*/
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#ifndef __INTEL_TH_H__
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#define __INTEL_TH_H__
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2019-05-03 16:44:41 +08:00
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#include <linux/irqreturn.h>
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2015-09-22 20:47:14 +08:00
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/* intel_th_device device types */
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enum {
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/* Devices that generate trace data */
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INTEL_TH_SOURCE = 0,
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/* Output ports (MSC, PTI) */
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INTEL_TH_OUTPUT,
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/* Switch, the Global Trace Hub (GTH) */
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INTEL_TH_SWITCH,
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};
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2019-05-03 16:44:46 +08:00
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struct intel_th_device;
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2015-09-22 20:47:14 +08:00
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/**
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* struct intel_th_output - descriptor INTEL_TH_OUTPUT type devices
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* @port: output port number, assigned by the switch
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* @type: GTH_{MSU,CTP,PTI}
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2016-02-16 01:11:55 +08:00
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* @scratchpad: scratchpad bits to flag when this output is enabled
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2015-09-22 20:47:14 +08:00
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* @multiblock: true for multiblock output configuration
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* @active: true when this output is enabled
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2019-05-03 16:44:46 +08:00
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* @wait_empty: wait for device pipeline to be empty
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2015-09-22 20:47:14 +08:00
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*
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* Output port descriptor, used by switch driver to tell which output
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* port this output device corresponds to. Filled in at output device's
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* probe time by switch::assign(). Passed from output device driver to
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* switch related code to enable/disable its port.
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*/
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struct intel_th_output {
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int port;
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unsigned int type;
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2016-02-16 01:11:55 +08:00
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unsigned int scratchpad;
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2015-09-22 20:47:14 +08:00
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bool multiblock;
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bool active;
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};
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2017-08-18 22:57:35 +08:00
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/**
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* struct intel_th_drvdata - describes hardware capabilities and quirks
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* @tscu_enable: device needs SW to enable time stamping unit
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2019-05-03 16:44:42 +08:00
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* @has_mintctl: device has interrupt control (MINTCTL) register
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2017-08-23 14:52:00 +08:00
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* @host_mode_only: device can only operate in 'host debugger' mode
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2017-08-18 22:57:35 +08:00
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*/
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struct intel_th_drvdata {
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2017-08-23 14:52:00 +08:00
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unsigned int tscu_enable : 1,
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2019-05-03 16:44:42 +08:00
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has_mintctl : 1,
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2017-08-23 14:52:00 +08:00
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host_mode_only : 1;
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2017-08-18 22:57:35 +08:00
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};
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#define INTEL_TH_CAP(_th, _cap) ((_th)->drvdata ? (_th)->drvdata->_cap : 0)
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2015-09-22 20:47:14 +08:00
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/**
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* struct intel_th_device - device on the intel_th bus
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* @dev: device
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2017-08-18 22:57:35 +08:00
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* @drvdata: hardware capabilities/quirks
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2015-09-22 20:47:14 +08:00
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* @resource: array of resources available to this device
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* @num_resources: number of resources in @resource array
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* @type: INTEL_TH_{SOURCE,OUTPUT,SWITCH}
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* @id: device instance or -1
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2016-09-19 22:07:47 +08:00
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* @host_mode: Intel TH is controlled by an external debug host
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2015-09-22 20:47:14 +08:00
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* @output: output descriptor for INTEL_TH_OUTPUT devices
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* @name: device name to match the driver
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*/
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struct intel_th_device {
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2017-08-18 22:57:35 +08:00
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struct device dev;
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struct intel_th_drvdata *drvdata;
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struct resource *resource;
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unsigned int num_resources;
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unsigned int type;
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int id;
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2015-09-22 20:47:14 +08:00
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2016-09-19 22:07:47 +08:00
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/* INTEL_TH_SWITCH specific */
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bool host_mode;
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2015-09-22 20:47:14 +08:00
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/* INTEL_TH_OUTPUT specific */
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struct intel_th_output output;
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char name[];
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};
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#define to_intel_th_device(_d) \
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container_of((_d), struct intel_th_device, dev)
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/**
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* intel_th_device_get_resource() - obtain @num'th resource of type @type
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* @thdev: the device to search the resource for
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* @type: resource type
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* @num: number of the resource
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*/
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static inline struct resource *
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intel_th_device_get_resource(struct intel_th_device *thdev, unsigned int type,
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unsigned int num)
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{
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int i;
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for (i = 0; i < thdev->num_resources; i++)
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if (resource_type(&thdev->resource[i]) == type && !num--)
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return &thdev->resource[i];
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return NULL;
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}
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2016-11-18 20:51:05 +08:00
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/*
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* GTH, output ports configuration
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*/
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enum {
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GTH_NONE = 0,
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GTH_MSU, /* memory/usb */
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GTH_CTP, /* Common Trace Port */
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2016-11-11 18:09:11 +08:00
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GTH_LPP, /* Low Power Path */
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GTH_PTI, /* MIPI-PTI */
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2016-11-18 20:51:05 +08:00
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};
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2015-09-22 20:47:14 +08:00
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/**
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* intel_th_output_assigned() - if an output device is assigned to a switch port
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* @thdev: the output device
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*
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* Return: true if the device is INTEL_TH_OUTPUT *and* is assigned a port
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*/
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static inline bool
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intel_th_output_assigned(struct intel_th_device *thdev)
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{
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return thdev->type == INTEL_TH_OUTPUT &&
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2016-11-18 20:51:05 +08:00
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(thdev->output.port >= 0 ||
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thdev->output.type == GTH_NONE);
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2015-09-22 20:47:14 +08:00
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}
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/**
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* struct intel_th_driver - driver for an intel_th_device device
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* @driver: generic driver
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* @probe: probe method
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* @remove: remove method
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* @assign: match a given output type device against available outputs
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* @unassign: deassociate an output type device from an output port
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* @enable: enable tracing for a given output device
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* @disable: disable tracing for a given output device
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2016-06-30 00:35:22 +08:00
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* @irq: interrupt callback
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* @activate: enable tracing on the output's side
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* @deactivate: disable tracing on the output's side
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2015-09-22 20:47:14 +08:00
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* @fops: file operations for device nodes
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2016-03-05 01:42:48 +08:00
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* @attr_group: attributes provided by the driver
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2015-09-22 20:47:14 +08:00
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*
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* Callbacks @probe and @remove are required for all device types.
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* Switch device driver needs to fill in @assign, @enable and @disable
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* callbacks.
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*/
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struct intel_th_driver {
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struct device_driver driver;
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int (*probe)(struct intel_th_device *thdev);
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void (*remove)(struct intel_th_device *thdev);
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/* switch (GTH) ops */
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int (*assign)(struct intel_th_device *thdev,
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struct intel_th_device *othdev);
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void (*unassign)(struct intel_th_device *thdev,
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struct intel_th_device *othdev);
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void (*enable)(struct intel_th_device *thdev,
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struct intel_th_output *output);
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2019-05-03 16:44:48 +08:00
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void (*trig_switch)(struct intel_th_device *thdev,
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struct intel_th_output *output);
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2015-09-22 20:47:14 +08:00
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void (*disable)(struct intel_th_device *thdev,
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struct intel_th_output *output);
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/* output ops */
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2019-05-03 16:44:41 +08:00
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irqreturn_t (*irq)(struct intel_th_device *thdev);
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2019-05-03 16:44:46 +08:00
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void (*wait_empty)(struct intel_th_device *thdev);
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2015-09-22 20:47:14 +08:00
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int (*activate)(struct intel_th_device *thdev);
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void (*deactivate)(struct intel_th_device *thdev);
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/* file_operations for those who want a device node */
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const struct file_operations *fops;
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2016-03-05 01:42:48 +08:00
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/* optional attributes */
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struct attribute_group *attr_group;
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2015-09-22 20:47:14 +08:00
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/* source ops */
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int (*set_output)(struct intel_th_device *thdev,
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unsigned int master);
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};
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#define to_intel_th_driver(_d) \
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container_of((_d), struct intel_th_driver, driver)
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2016-03-07 23:04:45 +08:00
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#define to_intel_th_driver_or_null(_d) \
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((_d) ? to_intel_th_driver(_d) : NULL)
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2016-11-18 21:36:39 +08:00
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/*
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* Subdevice tree structure is as follows:
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* + struct intel_th device (pci; dev_{get,set}_drvdata()
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* + struct intel_th_device INTEL_TH_SWITCH (GTH)
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* + struct intel_th_device INTEL_TH_OUTPUT (MSU, PTI)
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* + struct intel_th_device INTEL_TH_SOURCE (STH)
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*
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* In other words, INTEL_TH_OUTPUT devices are children of INTEL_TH_SWITCH;
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* INTEL_TH_SWITCH and INTEL_TH_SOURCE are children of the intel_th device.
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*/
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2015-09-22 20:47:14 +08:00
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static inline struct intel_th_device *
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2016-11-18 21:05:01 +08:00
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to_intel_th_parent(struct intel_th_device *thdev)
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2015-09-22 20:47:14 +08:00
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{
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struct device *parent = thdev->dev.parent;
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if (!parent)
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return NULL;
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return to_intel_th_device(parent);
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}
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2016-11-18 21:05:01 +08:00
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static inline struct intel_th *to_intel_th(struct intel_th_device *thdev)
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{
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2016-11-18 21:36:39 +08:00
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if (thdev->type == INTEL_TH_OUTPUT)
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thdev = to_intel_th_parent(thdev);
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2016-11-18 21:05:01 +08:00
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2016-11-18 21:36:39 +08:00
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if (WARN_ON_ONCE(!thdev || thdev->type == INTEL_TH_OUTPUT))
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2016-11-18 21:05:01 +08:00
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return NULL;
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return dev_get_drvdata(thdev->dev.parent);
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}
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2015-09-22 20:47:14 +08:00
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struct intel_th *
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2017-08-18 22:57:35 +08:00
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intel_th_alloc(struct device *dev, struct intel_th_drvdata *drvdata,
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2019-05-03 16:44:39 +08:00
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struct resource *devres, unsigned int ndevres);
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2015-09-22 20:47:14 +08:00
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void intel_th_free(struct intel_th *th);
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int intel_th_driver_register(struct intel_th_driver *thdrv);
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void intel_th_driver_unregister(struct intel_th_driver *thdrv);
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int intel_th_trace_enable(struct intel_th_device *thdev);
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2019-05-03 16:44:48 +08:00
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int intel_th_trace_switch(struct intel_th_device *thdev);
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2015-09-22 20:47:14 +08:00
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int intel_th_trace_disable(struct intel_th_device *thdev);
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int intel_th_set_output(struct intel_th_device *thdev,
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unsigned int master);
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2017-08-10 23:28:38 +08:00
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int intel_th_output_enable(struct intel_th *th, unsigned int otype);
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2015-09-22 20:47:14 +08:00
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2019-05-03 16:44:36 +08:00
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enum th_mmio_idx {
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2015-09-22 20:47:14 +08:00
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TH_MMIO_CONFIG = 0,
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2019-05-03 16:44:36 +08:00
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TH_MMIO_SW = 1,
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2019-05-03 16:44:38 +08:00
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TH_MMIO_RTIT = 2,
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2015-09-22 20:47:14 +08:00
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TH_MMIO_END,
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};
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#define TH_POSSIBLE_OUTPUTS 8
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2017-08-10 23:28:38 +08:00
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/* Total number of possible subdevices: outputs + GTH + STH */
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#define TH_SUBDEVICE_MAX (TH_POSSIBLE_OUTPUTS + 2)
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2015-09-22 20:47:14 +08:00
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#define TH_CONFIGURABLE_MASTERS 256
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#define TH_MSC_MAX 2
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2019-05-03 16:44:40 +08:00
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/* Maximum IRQ vectors */
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#define TH_NVEC_MAX 8
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2015-09-22 20:47:14 +08:00
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/**
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* struct intel_th - Intel TH controller
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* @dev: driver core's device
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* @thdev: subdevices
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* @hub: "switch" subdevice (GTH)
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2017-08-10 23:28:38 +08:00
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* @resource: resources of the entire controller
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* @num_thdevs: number of devices in the @thdev array
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2019-05-03 16:44:36 +08:00
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* @num_resources: number of resources in the @resource array
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2017-08-10 23:28:38 +08:00
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* @irq: irq number
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2015-09-22 20:47:14 +08:00
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* @id: this Intel TH controller's device ID in the system
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* @major: device node major for output devices
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*/
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struct intel_th {
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struct device *dev;
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struct intel_th_device *thdev[TH_SUBDEVICE_MAX];
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struct intel_th_device *hub;
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2017-08-18 22:57:35 +08:00
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struct intel_th_drvdata *drvdata;
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2015-09-22 20:47:14 +08:00
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2019-05-03 16:44:36 +08:00
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struct resource resource[TH_MMIO_END];
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2017-08-25 20:47:22 +08:00
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int (*activate)(struct intel_th *);
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void (*deactivate)(struct intel_th *);
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2017-08-10 23:28:38 +08:00
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unsigned int num_thdevs;
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unsigned int num_resources;
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int irq;
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2015-09-22 20:47:14 +08:00
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int id;
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int major;
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2016-06-30 16:51:44 +08:00
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#ifdef CONFIG_MODULES
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struct work_struct request_module_work;
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#endif /* CONFIG_MODULES */
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2015-09-22 20:47:14 +08:00
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#ifdef CONFIG_INTEL_TH_DEBUG
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struct dentry *dbg;
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#endif
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};
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2016-11-18 21:36:39 +08:00
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static inline struct intel_th_device *
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to_intel_th_hub(struct intel_th_device *thdev)
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{
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if (thdev->type == INTEL_TH_SWITCH)
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return thdev;
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else if (thdev->type == INTEL_TH_OUTPUT)
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return to_intel_th_parent(thdev);
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return to_intel_th(thdev)->hub;
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}
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2015-09-22 20:47:14 +08:00
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/*
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* Register windows
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*/
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enum {
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/* Global Trace Hub (GTH) */
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REG_GTH_OFFSET = 0x0000,
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REG_GTH_LENGTH = 0x2000,
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2017-02-24 22:09:40 +08:00
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/* Timestamp counter unit (TSCU) */
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REG_TSCU_OFFSET = 0x2000,
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REG_TSCU_LENGTH = 0x1000,
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2019-05-03 16:44:48 +08:00
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REG_CTS_OFFSET = 0x3000,
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REG_CTS_LENGTH = 0x1000,
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2015-09-22 20:47:14 +08:00
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/* Software Trace Hub (STH) [0x4000..0x4fff] */
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REG_STH_OFFSET = 0x4000,
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REG_STH_LENGTH = 0x2000,
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/* Memory Storage Unit (MSU) [0xa0000..0xa1fff] */
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|
|
REG_MSU_OFFSET = 0xa0000,
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|
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REG_MSU_LENGTH = 0x02000,
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|
|
|
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|
|
/* Internal MSU trace buffer [0x80000..0x9ffff] */
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|
|
|
BUF_MSU_OFFSET = 0x80000,
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|
|
BUF_MSU_LENGTH = 0x20000,
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|
|
|
|
|
|
/* PTI output == same window as GTH */
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|
|
|
REG_PTI_OFFSET = REG_GTH_OFFSET,
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|
|
REG_PTI_LENGTH = REG_GTH_LENGTH,
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|
|
|
|
|
|
|
/* DCI Handler (DCIH) == some window as MSU */
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|
|
|
REG_DCIH_OFFSET = REG_MSU_OFFSET,
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|
|
|
REG_DCIH_LENGTH = REG_MSU_LENGTH,
|
|
|
|
};
|
|
|
|
|
2016-02-16 01:11:55 +08:00
|
|
|
/*
|
|
|
|
* Scratchpad bits: tell firmware and external debuggers
|
|
|
|
* what we are up to.
|
|
|
|
*/
|
|
|
|
enum {
|
|
|
|
/* Memory is the primary destination */
|
|
|
|
SCRPD_MEM_IS_PRIM_DEST = BIT(0),
|
|
|
|
/* XHCI DbC is the primary destination */
|
|
|
|
SCRPD_DBC_IS_PRIM_DEST = BIT(1),
|
|
|
|
/* PTI is the primary destination */
|
|
|
|
SCRPD_PTI_IS_PRIM_DEST = BIT(2),
|
|
|
|
/* BSSB is the primary destination */
|
|
|
|
SCRPD_BSSB_IS_PRIM_DEST = BIT(3),
|
|
|
|
/* PTI is the alternate destination */
|
|
|
|
SCRPD_PTI_IS_ALT_DEST = BIT(4),
|
|
|
|
/* BSSB is the alternate destination */
|
|
|
|
SCRPD_BSSB_IS_ALT_DEST = BIT(5),
|
|
|
|
/* DeepSx exit occurred */
|
|
|
|
SCRPD_DEEPSX_EXIT = BIT(6),
|
|
|
|
/* S4 exit occurred */
|
|
|
|
SCRPD_S4_EXIT = BIT(7),
|
|
|
|
/* S5 exit occurred */
|
|
|
|
SCRPD_S5_EXIT = BIT(8),
|
|
|
|
/* MSU controller 0/1 is enabled */
|
|
|
|
SCRPD_MSC0_IS_ENABLED = BIT(9),
|
|
|
|
SCRPD_MSC1_IS_ENABLED = BIT(10),
|
|
|
|
/* Sx exit occurred */
|
|
|
|
SCRPD_SX_EXIT = BIT(11),
|
|
|
|
/* Trigger Unit is enabled */
|
|
|
|
SCRPD_TRIGGER_IS_ENABLED = BIT(12),
|
|
|
|
SCRPD_ODLA_IS_ENABLED = BIT(13),
|
|
|
|
SCRPD_SOCHAP_IS_ENABLED = BIT(14),
|
|
|
|
SCRPD_STH_IS_ENABLED = BIT(15),
|
|
|
|
SCRPD_DCIH_IS_ENABLED = BIT(16),
|
|
|
|
SCRPD_VER_IS_ENABLED = BIT(17),
|
|
|
|
/* External debugger is using Intel TH */
|
|
|
|
SCRPD_DEBUGGER_IN_USE = BIT(24),
|
|
|
|
};
|
|
|
|
|
2015-09-22 20:47:14 +08:00
|
|
|
#endif
|