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OpenCloudOS-Kernel/arch/arm/mach-sunxi/Kconfig

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ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
config ARCH_SUNXI
bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER The A31 has a reset controller, and we have to select this option to have access to the reset controller framework. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-09-24 16:09:55 +08:00
select ARCH_HAS_RESET_CONTROLLER
ARM: sunxi: select ARCH_REQUIRE_GPIOLIB CONFIG_ARCH_SUNXI currently doesn't enable a gpiolib, which causes build problems when building a kernel with only the sunxi platform enabled. Select ARCH_REQUIRE_GPIOLIB to solve this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar>
2013-05-12 21:06:51 +08:00
select ARCH_REQUIRE_GPIOLIB
ARM: sunxi: Order Kconfig options alphabetically Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-09-24 16:09:19 +08:00
select ARM_GIC
ARM: sunxi: select ARM_PSCI On Allwinner sun7i (A20) SoCs, the SMP operations are implemented in u-boot, and exposed to the kernel through PSCI. We thus need to enable PSCI support for Allwinner SoCs so that the kernel uses it to bring up the additionnal cores. Signed-off-by: Signed-off-by: Zalan Blenessy <zalan.blenessy@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-01-02 01:02:55 +08:00
select ARM_PSCI
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
ARM: sunxi: Select HAVE_ARM_ARCH_TIMER In order for the architected timers support to be enabled in the kernel, this option has to be enabled. Otherwise, the architected timers driver won't be compiled in, and we will not get to use them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
2014-03-27 23:27:41 +08:00
select HAVE_ARM_ARCH_TIMER
ARM: sunxi: Add basic support for Allwinner A1x SoCs Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stefan Roese <sr@denx.de>
2012-11-08 19:40:16 +08:00
select PINCTRL
ARM: sunxi: Order Kconfig options alphabetically Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-09-24 16:09:19 +08:00
select PINCTRL_SUNXI
ARM: sunxi: Select RESET_CONTROLLER The current code selects ARCH_HAS_RESET_CONTROLLER, that enables the RESET_CONTROLLER option by default, but doesn't select it, so a configuration might unselect it, leading to compilation error. Explictly select RESET_CONTROLLER so that we can't have this breakage anymore. Reported-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-30 23:37:29 +08:00
select RESET_CONTROLLER
clocksource: sunxi: Rename sunxi to sun4i During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that looks pretty much the same, but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-03-24 18:49:25 +08:00
select SUN4I_TIMER
clocksource: Add Allwinner SoCs HS timers driver Most of the Allwinner SoCs (at this time, all but the A10) also have a High Speed timers that are not using the 24MHz oscillator as a source but rather the AHB clock running much faster. The IP is slightly different between the A10s/A13 and the one used in the A20/A31, since the latter have 4 timers available, while the former have only 2 of them. [dlezcano] : Fixed conflict with b788beda "Order Kconfig options alphabetically" Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2013-11-07 19:01:48 +08:00
select SUN5I_HSTIMER