2012-08-15 20:59:49 +08:00
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/*
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* Copyright (C) 2012 Russell King
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* Rewritten from the dovefb driver, and Armada510 manuals.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <drm/drmP.h>
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2015-06-15 17:17:57 +08:00
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#include <drm/drm_plane_helper.h>
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2012-08-15 20:59:49 +08:00
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#include "armada_crtc.h"
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#include "armada_drm.h"
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#include "armada_fb.h"
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#include "armada_gem.h"
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#include "armada_hw.h"
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#include <drm/armada_drm.h>
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#include "armada_ioctlP.h"
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2016-05-17 20:51:08 +08:00
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#include "armada_trace.h"
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2012-08-15 20:59:49 +08:00
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2015-07-16 01:11:23 +08:00
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struct armada_ovl_plane_properties {
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2012-08-15 20:59:49 +08:00
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uint32_t colorkey_yr;
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uint32_t colorkey_ug;
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uint32_t colorkey_vb;
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#define K2R(val) (((val) >> 0) & 0xff)
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#define K2G(val) (((val) >> 8) & 0xff)
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#define K2B(val) (((val) >> 16) & 0xff)
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int16_t brightness;
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uint16_t contrast;
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uint16_t saturation;
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uint32_t colorkey_mode;
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};
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2015-07-16 01:11:23 +08:00
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struct armada_ovl_plane {
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2015-07-16 01:11:24 +08:00
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struct armada_plane base;
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2017-07-08 17:22:10 +08:00
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struct armada_plane_work work;
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2015-07-16 01:11:23 +08:00
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struct armada_ovl_plane_properties prop;
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2012-08-15 20:59:49 +08:00
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};
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2015-07-16 01:11:24 +08:00
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#define drm_to_armada_ovl_plane(p) \
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container_of(p, struct armada_ovl_plane, base.base)
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2012-08-15 20:59:49 +08:00
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static void
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2015-07-16 01:11:23 +08:00
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armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
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2012-08-15 20:59:49 +08:00
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struct armada_crtc *dcrtc)
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{
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writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
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writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
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writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
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writel_relaxed(prop->brightness << 16 | prop->contrast,
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dcrtc->base + LCD_SPU_CONTRAST);
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/* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
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writel_relaxed(prop->saturation << 16,
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dcrtc->base + LCD_SPU_SATURATION);
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writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
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spin_lock_irq(&dcrtc->irq_lock);
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armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
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CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
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dcrtc->base + LCD_SPU_DMA_CTRL1);
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armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
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spin_unlock_irq(&dcrtc->irq_lock);
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}
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/* === Plane support === */
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2015-08-07 16:33:05 +08:00
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static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
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2017-07-07 22:55:53 +08:00
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struct armada_plane_work *work)
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2012-08-15 20:59:49 +08:00
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{
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2017-07-08 17:16:48 +08:00
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unsigned long flags;
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2012-08-15 20:59:49 +08:00
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2017-07-07 22:55:53 +08:00
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trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane);
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2016-05-17 20:51:08 +08:00
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2017-07-08 17:16:48 +08:00
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spin_lock_irqsave(&dcrtc->irq_lock, flags);
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2017-07-08 17:22:10 +08:00
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armada_drm_crtc_update_regs(dcrtc, work->regs);
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2017-07-08 17:16:48 +08:00
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spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
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2012-08-15 20:59:49 +08:00
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}
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static int
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2015-07-16 01:11:23 +08:00
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armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
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2012-08-15 20:59:49 +08:00
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struct drm_framebuffer *fb,
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int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
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2017-03-23 05:50:41 +08:00
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uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
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struct drm_modeset_acquire_ctx *ctx)
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2012-08-15 20:59:49 +08:00
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{
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2015-07-16 01:11:23 +08:00
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struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
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2012-08-15 20:59:49 +08:00
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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2017-07-08 17:22:10 +08:00
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struct armada_plane_work *work = &dplane->work;
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2017-12-08 20:16:22 +08:00
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const struct drm_format_info *format;
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2017-07-08 17:22:20 +08:00
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struct drm_plane_state state = {
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.plane = plane,
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.crtc = crtc,
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.fb = fb,
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.src_x = src_x,
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.src_y = src_y,
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.src_w = src_w,
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.src_h = src_h,
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.crtc_x = crtc_x,
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.crtc_y = crtc_y,
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.crtc_w = crtc_w,
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.crtc_h = crtc_h,
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.rotation = DRM_MODE_ROTATE_0,
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2015-06-15 17:17:57 +08:00
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};
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const struct drm_rect clip = {
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.x2 = crtc->mode.hdisplay,
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.y2 = crtc->mode.vdisplay,
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};
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2012-08-15 20:59:49 +08:00
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uint32_t val, ctrl0;
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unsigned idx = 0;
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2017-07-08 17:22:20 +08:00
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bool fb_changed;
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2012-08-15 20:59:49 +08:00
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int ret;
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2016-05-17 20:51:08 +08:00
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trace_armada_ovl_plane_update(plane, crtc, fb,
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crtc_x, crtc_y, crtc_w, crtc_h,
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src_x, src_y, src_w, src_h);
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2017-07-08 17:22:20 +08:00
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ret = drm_plane_helper_check_state(&state, &clip, 0, INT_MAX, true,
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false);
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2015-06-15 17:17:57 +08:00
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if (ret)
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return ret;
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2012-08-15 20:59:49 +08:00
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ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
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CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
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2017-07-08 17:22:19 +08:00
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CFG_CBSH_ENA;
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2017-07-08 17:22:20 +08:00
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if (state.visible)
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2017-07-08 17:22:19 +08:00
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ctrl0 |= CFG_DMA_ENA;
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2017-07-08 17:22:20 +08:00
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if (drm_rect_width(&state.src) >> 16 != drm_rect_width(&state.dst))
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2017-07-08 17:22:19 +08:00
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ctrl0 |= CFG_DMA_HSMOOTH;
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2012-08-15 20:59:49 +08:00
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2017-12-08 20:16:22 +08:00
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/*
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* Shifting a YUV packed format image by one pixel causes the U/V
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* planes to swap. Compensate for it by also toggling the UV swap.
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*/
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format = fb->format;
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2017-07-08 17:22:20 +08:00
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if (format->num_planes == 1 && state.src.x1 >> 16 & (format->hsub - 1))
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2017-12-08 20:16:22 +08:00
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ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
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fb_changed = plane->fb != fb ||
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2017-07-08 17:22:20 +08:00
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dplane->base.state.src_x != state.src.x1 >> 16 ||
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dplane->base.state.src_y != state.src.y1 >> 16;
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2017-12-08 20:16:22 +08:00
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2012-08-15 20:59:49 +08:00
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if (!dcrtc->plane) {
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dcrtc->plane = plane;
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armada_ovl_update_attr(&dplane->prop, dcrtc);
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}
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/* FIXME: overlay on an interlaced display */
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/* Just updating the position/size? */
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2017-12-08 20:16:22 +08:00
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if (!fb_changed && dplane->base.state.ctrl0 == ctrl0) {
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2017-07-08 17:22:20 +08:00
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val = (drm_rect_height(&state.src) & 0xffff0000) |
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drm_rect_width(&state.src) >> 16;
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2016-08-17 05:09:08 +08:00
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dplane->base.state.src_hw = val;
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2012-08-15 20:59:49 +08:00
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writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
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2015-06-15 17:17:57 +08:00
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2017-07-08 17:22:20 +08:00
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val = drm_rect_height(&state.dst) << 16 |
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drm_rect_width(&state.dst);
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2016-08-17 05:09:08 +08:00
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dplane->base.state.dst_hw = val;
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2012-08-15 20:59:49 +08:00
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writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
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2015-06-15 17:17:57 +08:00
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2017-07-08 17:22:20 +08:00
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val = state.dst.y1 << 16 | state.dst.x1;
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2016-08-17 05:09:08 +08:00
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dplane->base.state.dst_yx = val;
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2012-08-15 20:59:49 +08:00
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writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
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2015-06-15 17:17:57 +08:00
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2012-08-15 20:59:49 +08:00
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return 0;
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2016-08-17 05:09:08 +08:00
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} else if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
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2012-08-15 20:59:49 +08:00
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/* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
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2017-07-08 17:22:15 +08:00
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armada_reg_queue_mod(work->regs, idx,
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0, CFG_PDWN16x66 | CFG_PDWN32x66,
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LCD_SPU_SRAM_PARA1);
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2012-08-15 20:59:49 +08:00
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}
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2015-08-07 16:33:05 +08:00
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if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
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armada_drm_plane_work_cancel(dcrtc, &dplane->base);
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2012-08-15 20:59:49 +08:00
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2017-12-08 20:16:22 +08:00
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if (fb_changed) {
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u32 addrs[3];
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2012-08-15 20:59:49 +08:00
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/*
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* Take a reference on the new framebuffer - we want to
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* hold on to it while the hardware is displaying it.
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*/
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2017-09-21 02:57:16 +08:00
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drm_framebuffer_get(fb);
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2012-08-15 20:59:49 +08:00
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2017-07-08 17:22:10 +08:00
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work->old_fb = plane->fb;
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2012-08-15 20:59:49 +08:00
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2017-07-08 17:22:20 +08:00
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dplane->base.state.src_y = src_y = state.src.y1 >> 16;
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dplane->base.state.src_x = src_x = state.src.x1 >> 16;
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2015-06-15 17:18:02 +08:00
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2016-08-17 05:09:11 +08:00
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armada_drm_plane_calc_addrs(addrs, fb, src_x, src_y);
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, addrs[0],
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_START_ADDR_Y0);
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, addrs[1],
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_START_ADDR_U0);
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, addrs[2],
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_START_ADDR_V0);
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, addrs[0],
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_START_ADDR_Y1);
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, addrs[1],
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_START_ADDR_U1);
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, addrs[2],
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_START_ADDR_V1);
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val = fb->pitches[0] << 16 | fb->pitches[0];
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, val,
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_PITCH_YC);
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val = fb->pitches[1] << 16 | fb->pitches[2];
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, val,
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_PITCH_UV);
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2017-07-08 17:16:52 +08:00
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} else {
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2017-07-08 17:22:10 +08:00
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work->old_fb = NULL;
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2012-08-15 20:59:49 +08:00
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}
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2017-07-08 17:22:20 +08:00
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val = (drm_rect_height(&state.src) & 0xffff0000) |
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drm_rect_width(&state.src) >> 16;
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2016-08-17 05:09:08 +08:00
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if (dplane->base.state.src_hw != val) {
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dplane->base.state.src_hw = val;
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, val,
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_HPXL_VLN);
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}
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2015-06-15 17:17:57 +08:00
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2017-07-08 17:22:20 +08:00
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val = drm_rect_height(&state.dst) << 16 | drm_rect_width(&state.dst);
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2016-08-17 05:09:08 +08:00
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if (dplane->base.state.dst_hw != val) {
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dplane->base.state.dst_hw = val;
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, val,
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DZM_HPXL_VLN);
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}
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2015-06-15 17:17:57 +08:00
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2017-07-08 17:22:20 +08:00
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val = state.dst.y1 << 16 | state.dst.x1;
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2016-08-17 05:09:08 +08:00
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if (dplane->base.state.dst_yx != val) {
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dplane->base.state.dst_yx = val;
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_set(work->regs, idx, val,
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2012-08-15 20:59:49 +08:00
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LCD_SPU_DMA_OVSA_HPXL_VLN);
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}
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2015-06-15 17:17:57 +08:00
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2016-08-17 05:09:08 +08:00
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if (dplane->base.state.ctrl0 != ctrl0) {
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dplane->base.state.ctrl0 = ctrl0;
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_mod(work->regs, idx, ctrl0,
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2012-08-15 20:59:49 +08:00
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CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
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CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
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CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
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CFG_YUV2RGB) | CFG_DMA_ENA,
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LCD_SPU_DMA_CTRL0);
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}
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if (idx) {
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2017-07-08 17:22:10 +08:00
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armada_reg_queue_end(work->regs, idx);
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2017-07-07 22:55:53 +08:00
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|
|
/* Queue it for update on the next interrupt if we are enabled */
|
2017-07-08 17:22:23 +08:00
|
|
|
ret = armada_drm_plane_work_queue(dcrtc, work);
|
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("failed to queue plane work: %d\n", ret);
|
2012-08-15 20:59:49 +08:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-03-23 05:50:43 +08:00
|
|
|
static int armada_ovl_plane_disable(struct drm_plane *plane,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx)
|
2012-08-15 20:59:49 +08:00
|
|
|
{
|
2017-07-08 17:16:42 +08:00
|
|
|
armada_drm_plane_disable(plane, ctx);
|
2012-08-15 20:59:49 +08:00
|
|
|
|
2017-07-08 17:16:52 +08:00
|
|
|
if (plane->crtc)
|
|
|
|
drm_to_armada_crtc(plane->crtc)->plane = NULL;
|
2012-08-15 20:59:49 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-07-16 01:11:23 +08:00
|
|
|
static void armada_ovl_plane_destroy(struct drm_plane *plane)
|
2012-08-15 20:59:49 +08:00
|
|
|
{
|
2015-07-16 01:11:23 +08:00
|
|
|
struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
|
2015-06-15 17:13:30 +08:00
|
|
|
|
|
|
|
drm_plane_cleanup(plane);
|
|
|
|
|
|
|
|
kfree(dplane);
|
2012-08-15 20:59:49 +08:00
|
|
|
}
|
|
|
|
|
2015-07-16 01:11:23 +08:00
|
|
|
static int armada_ovl_plane_set_property(struct drm_plane *plane,
|
2012-08-15 20:59:49 +08:00
|
|
|
struct drm_property *property, uint64_t val)
|
|
|
|
{
|
|
|
|
struct armada_private *priv = plane->dev->dev_private;
|
2015-07-16 01:11:23 +08:00
|
|
|
struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
|
2012-08-15 20:59:49 +08:00
|
|
|
bool update_attr = false;
|
|
|
|
|
|
|
|
if (property == priv->colorkey_prop) {
|
|
|
|
#define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
|
|
|
|
dplane->prop.colorkey_yr = CCC(K2R(val));
|
|
|
|
dplane->prop.colorkey_ug = CCC(K2G(val));
|
|
|
|
dplane->prop.colorkey_vb = CCC(K2B(val));
|
|
|
|
#undef CCC
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->colorkey_min_prop) {
|
|
|
|
dplane->prop.colorkey_yr &= ~0x00ff0000;
|
|
|
|
dplane->prop.colorkey_yr |= K2R(val) << 16;
|
|
|
|
dplane->prop.colorkey_ug &= ~0x00ff0000;
|
|
|
|
dplane->prop.colorkey_ug |= K2G(val) << 16;
|
|
|
|
dplane->prop.colorkey_vb &= ~0x00ff0000;
|
|
|
|
dplane->prop.colorkey_vb |= K2B(val) << 16;
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->colorkey_max_prop) {
|
|
|
|
dplane->prop.colorkey_yr &= ~0xff000000;
|
|
|
|
dplane->prop.colorkey_yr |= K2R(val) << 24;
|
|
|
|
dplane->prop.colorkey_ug &= ~0xff000000;
|
|
|
|
dplane->prop.colorkey_ug |= K2G(val) << 24;
|
|
|
|
dplane->prop.colorkey_vb &= ~0xff000000;
|
|
|
|
dplane->prop.colorkey_vb |= K2B(val) << 24;
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->colorkey_val_prop) {
|
|
|
|
dplane->prop.colorkey_yr &= ~0x0000ff00;
|
|
|
|
dplane->prop.colorkey_yr |= K2R(val) << 8;
|
|
|
|
dplane->prop.colorkey_ug &= ~0x0000ff00;
|
|
|
|
dplane->prop.colorkey_ug |= K2G(val) << 8;
|
|
|
|
dplane->prop.colorkey_vb &= ~0x0000ff00;
|
|
|
|
dplane->prop.colorkey_vb |= K2B(val) << 8;
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->colorkey_alpha_prop) {
|
|
|
|
dplane->prop.colorkey_yr &= ~0x000000ff;
|
|
|
|
dplane->prop.colorkey_yr |= K2R(val);
|
|
|
|
dplane->prop.colorkey_ug &= ~0x000000ff;
|
|
|
|
dplane->prop.colorkey_ug |= K2G(val);
|
|
|
|
dplane->prop.colorkey_vb &= ~0x000000ff;
|
|
|
|
dplane->prop.colorkey_vb |= K2B(val);
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->colorkey_mode_prop) {
|
|
|
|
dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
|
|
|
|
dplane->prop.colorkey_mode |= CFG_CKMODE(val);
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->brightness_prop) {
|
|
|
|
dplane->prop.brightness = val - 256;
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->contrast_prop) {
|
|
|
|
dplane->prop.contrast = val;
|
|
|
|
update_attr = true;
|
|
|
|
} else if (property == priv->saturation_prop) {
|
|
|
|
dplane->prop.saturation = val;
|
|
|
|
update_attr = true;
|
|
|
|
}
|
|
|
|
|
2015-07-16 01:11:24 +08:00
|
|
|
if (update_attr && dplane->base.base.crtc)
|
2012-08-15 20:59:49 +08:00
|
|
|
armada_ovl_update_attr(&dplane->prop,
|
2015-07-16 01:11:24 +08:00
|
|
|
drm_to_armada_crtc(dplane->base.base.crtc));
|
2012-08-15 20:59:49 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-07-16 01:11:23 +08:00
|
|
|
static const struct drm_plane_funcs armada_ovl_plane_funcs = {
|
|
|
|
.update_plane = armada_ovl_plane_update,
|
|
|
|
.disable_plane = armada_ovl_plane_disable,
|
|
|
|
.destroy = armada_ovl_plane_destroy,
|
|
|
|
.set_property = armada_ovl_plane_set_property,
|
2012-08-15 20:59:49 +08:00
|
|
|
};
|
|
|
|
|
2015-07-16 01:11:23 +08:00
|
|
|
static const uint32_t armada_ovl_formats[] = {
|
2012-08-15 20:59:49 +08:00
|
|
|
DRM_FORMAT_UYVY,
|
|
|
|
DRM_FORMAT_YUYV,
|
|
|
|
DRM_FORMAT_YUV420,
|
|
|
|
DRM_FORMAT_YVU420,
|
|
|
|
DRM_FORMAT_YUV422,
|
|
|
|
DRM_FORMAT_YVU422,
|
|
|
|
DRM_FORMAT_VYUY,
|
|
|
|
DRM_FORMAT_YVYU,
|
|
|
|
DRM_FORMAT_ARGB8888,
|
|
|
|
DRM_FORMAT_ABGR8888,
|
|
|
|
DRM_FORMAT_XRGB8888,
|
|
|
|
DRM_FORMAT_XBGR8888,
|
|
|
|
DRM_FORMAT_RGB888,
|
|
|
|
DRM_FORMAT_BGR888,
|
|
|
|
DRM_FORMAT_ARGB1555,
|
|
|
|
DRM_FORMAT_ABGR1555,
|
|
|
|
DRM_FORMAT_RGB565,
|
|
|
|
DRM_FORMAT_BGR565,
|
|
|
|
};
|
|
|
|
|
2017-07-01 18:54:42 +08:00
|
|
|
static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
|
2012-08-15 20:59:49 +08:00
|
|
|
{ CKMODE_DISABLE, "disabled" },
|
|
|
|
{ CKMODE_Y, "Y component" },
|
|
|
|
{ CKMODE_U, "U component" },
|
|
|
|
{ CKMODE_V, "V component" },
|
|
|
|
{ CKMODE_RGB, "RGB" },
|
|
|
|
{ CKMODE_R, "R component" },
|
|
|
|
{ CKMODE_G, "G component" },
|
|
|
|
{ CKMODE_B, "B component" },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int armada_overlay_create_properties(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct armada_private *priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (priv->colorkey_prop)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
priv->colorkey_prop = drm_property_create_range(dev, 0,
|
|
|
|
"colorkey", 0, 0xffffff);
|
|
|
|
priv->colorkey_min_prop = drm_property_create_range(dev, 0,
|
|
|
|
"colorkey_min", 0, 0xffffff);
|
|
|
|
priv->colorkey_max_prop = drm_property_create_range(dev, 0,
|
|
|
|
"colorkey_max", 0, 0xffffff);
|
|
|
|
priv->colorkey_val_prop = drm_property_create_range(dev, 0,
|
|
|
|
"colorkey_val", 0, 0xffffff);
|
|
|
|
priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
|
|
|
|
"colorkey_alpha", 0, 0xffffff);
|
|
|
|
priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
|
|
|
|
"colorkey_mode",
|
|
|
|
armada_drm_colorkey_enum_list,
|
|
|
|
ARRAY_SIZE(armada_drm_colorkey_enum_list));
|
|
|
|
priv->brightness_prop = drm_property_create_range(dev, 0,
|
|
|
|
"brightness", 0, 256 + 255);
|
|
|
|
priv->contrast_prop = drm_property_create_range(dev, 0,
|
|
|
|
"contrast", 0, 0x7fff);
|
|
|
|
priv->saturation_prop = drm_property_create_range(dev, 0,
|
|
|
|
"saturation", 0, 0x7fff);
|
|
|
|
|
|
|
|
if (!priv->colorkey_prop)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
|
|
|
|
{
|
|
|
|
struct armada_private *priv = dev->dev_private;
|
|
|
|
struct drm_mode_object *mobj;
|
2015-07-16 01:11:23 +08:00
|
|
|
struct armada_ovl_plane *dplane;
|
2012-08-15 20:59:49 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = armada_overlay_create_properties(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
|
|
|
|
if (!dplane)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-07-16 01:11:25 +08:00
|
|
|
ret = armada_drm_plane_init(&dplane->base);
|
|
|
|
if (ret) {
|
|
|
|
kfree(dplane);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-07-08 17:22:10 +08:00
|
|
|
dplane->work.plane = &dplane->base.base;
|
|
|
|
dplane->work.fn = armada_ovl_plane_work;
|
2012-08-15 20:59:49 +08:00
|
|
|
|
2015-07-16 01:11:24 +08:00
|
|
|
ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
|
2015-07-16 01:11:24 +08:00
|
|
|
&armada_ovl_plane_funcs,
|
|
|
|
armada_ovl_formats,
|
|
|
|
ARRAY_SIZE(armada_ovl_formats),
|
2017-07-24 11:46:38 +08:00
|
|
|
NULL,
|
drm: Pass 'name' to drm_universal_plane_init()
Done with coccinelle for the most part. It choked on
msm/mdp/mdp5/mdp5_plane.c like so:
"BAD:!!!!! enum drm_plane_type type;"
No idea how to deal with that, so I just fixed that up
by hand.
Also it thinks '...' is part of the semantic patch, so I put an
'int DOTDOTDOT' placeholder in its place and got rid of it with
sed afterwards.
I didn't convert drm_plane_init() since passing the varargs through
would mean either cpp macros or va_list, and I figured we don't
care about these legacy functions enough to warrant the extra pain.
@@
typedef uint32_t;
identifier dev, plane, possible_crtcs, funcs, formats, format_count, type;
@@
int drm_universal_plane_init(struct drm_device *dev,
struct drm_plane *plane,
unsigned long possible_crtcs,
const struct drm_plane_funcs *funcs,
const uint32_t *formats,
unsigned int format_count,
enum drm_plane_type type
+ ,const char *name, int DOTDOTDOT
)
{ ... }
@@
identifier dev, plane, possible_crtcs, funcs, formats, format_count, type;
@@
int drm_universal_plane_init(struct drm_device *dev,
struct drm_plane *plane,
unsigned long possible_crtcs,
const struct drm_plane_funcs *funcs,
const uint32_t *formats,
unsigned int format_count,
enum drm_plane_type type
+ ,const char *name, int DOTDOTDOT
);
@@
expression E1, E2, E3, E4, E5, E6, E7;
@@
drm_universal_plane_init(E1, E2, E3, E4, E5, E6, E7
+ ,NULL
)
v2: Split crtc and plane changes apart
Pass NUL for no-name instead of ""
Leave drm_plane_init() alone
v3: Add ', or NULL...' to @name kernel doc (Jani)
Annotate the function with __printf() attribute (Jani)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449670795-2853-1-git-send-email-ville.syrjala@linux.intel.com
2015-12-09 22:19:55 +08:00
|
|
|
DRM_PLANE_TYPE_OVERLAY, NULL);
|
2015-07-16 01:11:23 +08:00
|
|
|
if (ret) {
|
|
|
|
kfree(dplane);
|
|
|
|
return ret;
|
|
|
|
}
|
2012-08-15 20:59:49 +08:00
|
|
|
|
|
|
|
dplane->prop.colorkey_yr = 0xfefefe00;
|
|
|
|
dplane->prop.colorkey_ug = 0x01010100;
|
|
|
|
dplane->prop.colorkey_vb = 0x01010100;
|
|
|
|
dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
|
|
|
|
dplane->prop.brightness = 0;
|
|
|
|
dplane->prop.contrast = 0x4000;
|
|
|
|
dplane->prop.saturation = 0x4000;
|
|
|
|
|
2015-07-16 01:11:24 +08:00
|
|
|
mobj = &dplane->base.base.base;
|
2012-08-15 20:59:49 +08:00
|
|
|
drm_object_attach_property(mobj, priv->colorkey_prop,
|
|
|
|
0x0101fe);
|
|
|
|
drm_object_attach_property(mobj, priv->colorkey_min_prop,
|
|
|
|
0x0101fe);
|
|
|
|
drm_object_attach_property(mobj, priv->colorkey_max_prop,
|
|
|
|
0x0101fe);
|
|
|
|
drm_object_attach_property(mobj, priv->colorkey_val_prop,
|
|
|
|
0x0101fe);
|
|
|
|
drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
|
|
|
|
0x000000);
|
|
|
|
drm_object_attach_property(mobj, priv->colorkey_mode_prop,
|
|
|
|
CKMODE_RGB);
|
|
|
|
drm_object_attach_property(mobj, priv->brightness_prop, 256);
|
|
|
|
drm_object_attach_property(mobj, priv->contrast_prop,
|
|
|
|
dplane->prop.contrast);
|
|
|
|
drm_object_attach_property(mobj, priv->saturation_prop,
|
|
|
|
dplane->prop.saturation);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|