2018-04-19 06:05:18 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2016-08-12 00:20:56 +08:00
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*/
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#ifndef _LINUX_CORESIGHT_PMU_H
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#define _LINUX_CORESIGHT_PMU_H
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#define CORESIGHT_ETM_PMU_NAME "cs_etm"
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#define CORESIGHT_ETM_PMU_SEED 0x10
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/* ETMv3.5/PTM's ETMCR config bit */
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#define ETM_OPT_CYCACC 12
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2019-04-26 03:52:52 +08:00
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#define ETM_OPT_CTXTID 14
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2016-08-12 00:20:56 +08:00
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#define ETM_OPT_TS 28
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2017-08-03 00:22:01 +08:00
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#define ETM_OPT_RETSTK 29
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2016-08-12 00:20:56 +08:00
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2017-08-03 00:22:19 +08:00
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/* ETMv4 CONFIGR programming bits for the ETM OPTs */
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#define ETM4_CFG_BIT_CYCACC 4
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2019-04-26 03:52:52 +08:00
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#define ETM4_CFG_BIT_CTXTID 6
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2017-08-03 00:22:19 +08:00
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#define ETM4_CFG_BIT_TS 11
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#define ETM4_CFG_BIT_RETSTK 12
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2016-08-12 00:20:56 +08:00
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static inline int coresight_get_trace_id(int cpu)
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{
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/*
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* A trace ID of value 0 is invalid, so let's start at some
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* random value that fits in 7 bits and go from there. Since
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* the common convention is to have data trace IDs be I(N) + 1,
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* set instruction trace IDs as a function of the CPU number.
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*/
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return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
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}
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#endif
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