2005-10-20 14:56:38 +08:00
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/*
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* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/kernel_stat.h>
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#include <asm/errno.h>
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2006-10-08 02:44:33 +08:00
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#include <asm/irq_regs.h>
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2005-10-20 14:56:38 +08:00
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#include <asm/signal.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/bcm1480_int.h>
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#include <asm/sibyte/bcm1480_scd.h>
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#include <asm/sibyte/sb1250_uart.h>
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#include <asm/sibyte/sb1250.h>
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/*
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* These are the routines that handle all the low level interrupt stuff.
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* Actions handled here are: initialization of the interrupt map, requesting of
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* interrupt lines by handlers, dispatching if interrupts to handlers, probing
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* for interrupt lines
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*/
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#define shutdown_bcm1480_irq disable_bcm1480_irq
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static void end_bcm1480_irq(unsigned int irq);
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static void enable_bcm1480_irq(unsigned int irq);
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static void disable_bcm1480_irq(unsigned int irq);
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static unsigned int startup_bcm1480_irq(unsigned int irq);
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static void ack_bcm1480_irq(unsigned int irq);
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#ifdef CONFIG_SMP
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static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
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#endif
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#ifdef CONFIG_PCI
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extern unsigned long ht_eoi_space;
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#endif
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#ifdef CONFIG_KGDB
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#include <asm/gdb-stub.h>
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extern void breakpoint(void);
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static int kgdb_irq;
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#ifdef CONFIG_GDB_CONSOLE
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extern void register_gdb_console(void);
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#endif
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/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
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static int kgdb_flag = 1;
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static int __init nokgdb(char *str)
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{
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kgdb_flag = 0;
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return 1;
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}
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__setup("nokgdb", nokgdb);
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/* Default to UART1 */
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int kgdb_port = 1;
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#ifdef CONFIG_SIBYTE_SB1250_DUART
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extern char sb1250_duart_present[];
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#endif
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#endif
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2006-07-02 21:41:42 +08:00
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static struct irq_chip bcm1480_irq_type = {
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2005-10-20 14:56:38 +08:00
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.typename = "BCM1480-IMR",
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.startup = startup_bcm1480_irq,
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.shutdown = shutdown_bcm1480_irq,
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.enable = enable_bcm1480_irq,
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.disable = disable_bcm1480_irq,
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.ack = ack_bcm1480_irq,
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.end = end_bcm1480_irq,
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#ifdef CONFIG_SMP
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.set_affinity = bcm1480_set_affinity
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#endif
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};
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/* Store the CPU id (not the logical number) */
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int bcm1480_irq_owner[BCM1480_NR_IRQS];
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DEFINE_SPINLOCK(bcm1480_imr_lock);
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void bcm1480_mask_irq(int cpu, int irq)
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{
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unsigned long flags;
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u64 cur_ints,hl_spacing;
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spin_lock_irqsave(&bcm1480_imr_lock, flags);
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hl_spacing = 0;
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if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
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hl_spacing = BCM1480_IMR_HL_SPACING;
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irq -= BCM1480_NR_IRQS_HALF;
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}
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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cur_ints |= (((u64) 1) << irq);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
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}
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void bcm1480_unmask_irq(int cpu, int irq)
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{
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unsigned long flags;
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u64 cur_ints,hl_spacing;
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spin_lock_irqsave(&bcm1480_imr_lock, flags);
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hl_spacing = 0;
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if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
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hl_spacing = BCM1480_IMR_HL_SPACING;
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irq -= BCM1480_NR_IRQS_HALF;
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}
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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cur_ints &= ~(((u64) 1) << irq);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
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spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
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}
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#ifdef CONFIG_SMP
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static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
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{
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2006-02-20 12:57:00 +08:00
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int i = 0, old_cpu, cpu, int_on, k;
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2005-10-20 14:56:38 +08:00
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u64 cur_ints;
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2006-07-02 21:41:42 +08:00
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struct irq_desc *desc = irq_desc + irq;
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2005-10-20 14:56:38 +08:00
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unsigned long flags;
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unsigned int irq_dirty;
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i = first_cpu(mask);
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if (next_cpu(i, mask) <= NR_CPUS) {
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printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
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return;
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}
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/* Convert logical CPU to physical CPU */
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cpu = cpu_logical_map(i);
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/* Protect against other affinity changers and IMR manipulation */
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spin_lock_irqsave(&desc->lock, flags);
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spin_lock(&bcm1480_imr_lock);
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/* Swizzle each CPU's IMR (but leave the IP selection alone) */
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old_cpu = bcm1480_irq_owner[irq];
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irq_dirty = irq;
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if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
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irq_dirty -= BCM1480_NR_IRQS_HALF;
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}
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for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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int_on = !(cur_ints & (((u64) 1) << irq_dirty));
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if (int_on) {
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/* If it was on, mask it */
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cur_ints |= (((u64) 1) << irq_dirty);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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}
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bcm1480_irq_owner[irq] = cpu;
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if (int_on) {
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/* unmask for the new CPU */
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cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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cur_ints &= ~(((u64) 1) << irq_dirty);
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____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
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}
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}
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spin_unlock(&bcm1480_imr_lock);
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spin_unlock_irqrestore(&desc->lock, flags);
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}
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#endif
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/*****************************************************************************/
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static unsigned int startup_bcm1480_irq(unsigned int irq)
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{
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bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
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return 0; /* never anything pending */
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}
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static void disable_bcm1480_irq(unsigned int irq)
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{
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bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
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}
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static void enable_bcm1480_irq(unsigned int irq)
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{
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bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
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}
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static void ack_bcm1480_irq(unsigned int irq)
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{
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u64 pending;
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unsigned int irq_dirty;
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2006-02-20 12:57:00 +08:00
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int k;
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2005-10-20 14:56:38 +08:00
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/*
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* If the interrupt was an HT interrupt, now is the time to
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* clear it. NOTE: we assume the HT bridge was set up to
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* deliver the interrupts to all CPUs (which makes affinity
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* changing easier for us)
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*/
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irq_dirty = irq;
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if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
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irq_dirty -= BCM1480_NR_IRQS_HALF;
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}
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for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
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pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
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R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
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pending &= ((u64)1 << (irq_dirty));
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if (pending) {
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#ifdef CONFIG_SMP
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int i;
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for (i=0; i<NR_CPUS; i++) {
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/*
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* Clear for all CPUs so an affinity switch
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* doesn't find an old status
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*/
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__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
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R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
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}
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#else
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__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
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#endif
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/*
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* Generate EOI. For Pass 1 parts, EOI is a nop. For
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* Pass 2, the LDT world may be edge-triggered, but
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* this EOI shouldn't hurt. If they are
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* level-sensitive, the EOI is required.
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*/
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#ifdef CONFIG_PCI
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if (ht_eoi_space)
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*(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
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#endif
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}
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}
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bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
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}
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static void end_bcm1480_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
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}
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}
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void __init init_bcm1480_irqs(void)
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{
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int i;
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for (i = 0; i < NR_IRQS; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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if (i < BCM1480_NR_IRQS) {
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 17:24:36 +08:00
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irq_desc[i].chip = &bcm1480_irq_type;
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2005-10-20 14:56:38 +08:00
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bcm1480_irq_owner[i] = 0;
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} else {
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2006-07-02 21:41:42 +08:00
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irq_desc[i].chip = &no_irq_chip;
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2005-10-20 14:56:38 +08:00
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}
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}
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}
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2006-10-08 02:44:33 +08:00
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static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id)
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2005-10-20 14:56:38 +08:00
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{
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return IRQ_NONE;
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}
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static struct irqaction bcm1480_dummy_action = {
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.handler = bcm1480_dummy_handler,
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.flags = 0,
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.mask = CPU_MASK_NONE,
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.name = "bcm1480-private",
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.next = NULL,
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.dev_id = 0
|
|
|
|
};
|
|
|
|
|
|
|
|
int bcm1480_steal_irq(int irq)
|
|
|
|
{
|
2006-07-02 21:41:42 +08:00
|
|
|
struct irq_desc *desc = irq_desc + irq;
|
2005-10-20 14:56:38 +08:00
|
|
|
unsigned long flags;
|
|
|
|
int retval = 0;
|
|
|
|
|
|
|
|
if (irq >= BCM1480_NR_IRQS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&desc->lock,flags);
|
|
|
|
/* Don't allow sharing at all for these */
|
|
|
|
if (desc->action != NULL)
|
|
|
|
retval = -EBUSY;
|
|
|
|
else {
|
|
|
|
desc->action = &bcm1480_dummy_action;
|
|
|
|
desc->depth = 0;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&desc->lock,flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* init_IRQ is called early in the boot sequence from init/main.c. It
|
|
|
|
* is responsible for setting up the interrupt mapper and installing the
|
|
|
|
* handler that will be responsible for dispatching interrupts to the
|
|
|
|
* "right" place.
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* For now, map all interrupts to IP[2]. We could save
|
|
|
|
* some cycles by parceling out system interrupts to different
|
|
|
|
* IP lines, but keep it simple for bringup. We'll also direct
|
|
|
|
* all interrupts to a single CPU; we should probably route
|
|
|
|
* PCI and LDT to one cpu and everything else to the other
|
|
|
|
* to balance the load a bit.
|
|
|
|
*
|
|
|
|
* On the second cpu, everything is set to IP5, which is
|
|
|
|
* ignored, EXCEPT the mailbox interrupt. That one is
|
|
|
|
* set to IP[2] so it is handled. This is needed so we
|
|
|
|
* can do cross-cpu function calls, as requred by SMP
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
|
|
|
|
#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
|
|
|
|
#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
|
|
|
|
#define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
|
|
|
|
#define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
|
|
|
|
|
|
|
|
void __init arch_init_irq(void)
|
|
|
|
{
|
|
|
|
|
|
|
|
unsigned int i, cpu;
|
|
|
|
u64 tmp;
|
|
|
|
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
|
|
|
|
STATUSF_IP1 | STATUSF_IP0;
|
|
|
|
|
|
|
|
/* Default everything to IP2 */
|
|
|
|
/* Start with _high registers which has no bit 0 interrupt source */
|
|
|
|
for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
|
|
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
|
|
__raw_writeq(IMR_IP2_VAL,
|
|
|
|
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
|
|
|
|
R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now do _low registers */
|
|
|
|
for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
|
|
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
|
|
__raw_writeq(IMR_IP2_VAL,
|
|
|
|
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
|
|
|
|
R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
init_bcm1480_irqs();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map the high 16 bits of mailbox_0 registers to IP[3], for
|
|
|
|
* inter-cpu messages
|
|
|
|
*/
|
|
|
|
/* Was I1 */
|
|
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
|
|
__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
|
|
|
|
(K_BCM1480_INT_MBOX_0_0 << 3)));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Clear the mailboxes. The firmware may leave them dirty */
|
|
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
|
|
__raw_writeq(0xffffffffffffffffULL,
|
|
|
|
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
|
|
|
|
__raw_writeq(0xffffffffffffffffULL,
|
|
|
|
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
|
|
|
|
tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
|
|
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
|
|
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
|
|
|
|
}
|
|
|
|
tmp = ~((u64) 0);
|
|
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
|
|
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
|
|
|
|
}
|
|
|
|
|
|
|
|
bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that the timer interrupts are also mapped, but this is
|
|
|
|
* done in bcm1480_time_init(). Also, the profiling driver
|
|
|
|
* does its own management of IP7.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_KGDB
|
|
|
|
imask |= STATUSF_IP6;
|
|
|
|
#endif
|
|
|
|
/* Enable necessary IPs, disable the rest */
|
|
|
|
change_c0_status(ST0_IM, imask);
|
|
|
|
|
|
|
|
#ifdef CONFIG_KGDB
|
|
|
|
if (kgdb_flag) {
|
|
|
|
kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
|
|
|
|
|
|
|
|
#ifdef CONFIG_SIBYTE_SB1250_DUART
|
|
|
|
sb1250_duart_present[kgdb_port] = 0;
|
|
|
|
#endif
|
|
|
|
/* Setup uart 1 settings, mapper */
|
|
|
|
/* QQQ FIXME */
|
|
|
|
__raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
|
|
|
|
|
|
|
|
bcm1480_steal_irq(kgdb_irq);
|
|
|
|
__raw_writeq(IMR_IP6_VAL,
|
|
|
|
IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
|
|
|
|
(kgdb_irq<<3));
|
|
|
|
bcm1480_unmask_irq(0, kgdb_irq);
|
|
|
|
|
|
|
|
#ifdef CONFIG_GDB_CONSOLE
|
|
|
|
register_gdb_console();
|
|
|
|
#endif
|
|
|
|
prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
|
|
|
|
set_debug_traps();
|
|
|
|
breakpoint();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_KGDB
|
|
|
|
|
|
|
|
#include <linux/delay.h>
|
|
|
|
|
|
|
|
#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
|
|
|
|
#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
|
|
|
|
|
2006-10-08 02:44:33 +08:00
|
|
|
static void bcm1480_kgdb_interrupt(void)
|
2005-10-20 14:56:38 +08:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Clear break-change status (allow some time for the remote
|
|
|
|
* host to stop the break, since we would see another
|
|
|
|
* interrupt on the end-of-break too)
|
|
|
|
*/
|
|
|
|
kstat.irqs[smp_processor_id()][kgdb_irq]++;
|
|
|
|
mdelay(500);
|
|
|
|
duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
|
|
|
|
M_DUART_RX_EN | M_DUART_TX_EN);
|
2006-10-08 02:44:33 +08:00
|
|
|
set_async_breakpoint(&get_irq_regs()->cp0_epc);
|
2005-10-20 14:56:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_KGDB */
|
2006-04-04 00:56:36 +08:00
|
|
|
|
2006-10-08 02:44:33 +08:00
|
|
|
extern void bcm1480_timer_interrupt(void);
|
|
|
|
extern void bcm1480_mailbox_interrupt(void);
|
2006-04-04 00:56:36 +08:00
|
|
|
|
2006-10-08 02:44:33 +08:00
|
|
|
asmlinkage void plat_irq_dispatch(void)
|
2006-04-04 00:56:36 +08:00
|
|
|
{
|
|
|
|
unsigned int pending;
|
|
|
|
|
|
|
|
#ifdef CONFIG_SIBYTE_BCM1480_PROF
|
|
|
|
/* Set compare to count to silence count/compare timer interrupts */
|
|
|
|
write_c0_compare(read_c0_count());
|
|
|
|
#endif
|
|
|
|
|
2006-10-03 21:42:02 +08:00
|
|
|
pending = read_c0_cause() & read_c0_status();
|
2006-04-04 00:56:36 +08:00
|
|
|
|
|
|
|
#ifdef CONFIG_SIBYTE_BCM1480_PROF
|
|
|
|
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
|
2006-10-08 02:44:33 +08:00
|
|
|
sbprof_cpu_intr();
|
2006-07-05 21:26:38 +08:00
|
|
|
else
|
2006-04-04 00:56:36 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
if (pending & CAUSEF_IP4)
|
2006-10-08 02:44:33 +08:00
|
|
|
bcm1480_timer_interrupt();
|
2006-04-04 00:56:36 +08:00
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
2006-07-05 21:26:38 +08:00
|
|
|
else if (pending & CAUSEF_IP3)
|
2006-10-08 02:44:33 +08:00
|
|
|
bcm1480_mailbox_interrupt();
|
2006-04-04 00:56:36 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_KGDB
|
2006-07-05 21:26:38 +08:00
|
|
|
else if (pending & CAUSEF_IP6)
|
2006-10-08 02:44:33 +08:00
|
|
|
bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
|
2006-04-04 00:56:36 +08:00
|
|
|
#endif
|
|
|
|
|
2006-07-05 21:26:38 +08:00
|
|
|
else if (pending & CAUSEF_IP2) {
|
2006-04-04 00:56:36 +08:00
|
|
|
unsigned long long mask_h, mask_l;
|
|
|
|
unsigned long base;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Default...we've hit an IP[2] interrupt, which means we've
|
|
|
|
* got to check the 1480 interrupt registers to figure out what
|
|
|
|
* to do. Need to detect which CPU we're on, now that
|
|
|
|
* smp_affinity is supported.
|
|
|
|
*/
|
|
|
|
base = A_BCM1480_IMR_MAPPER(smp_processor_id());
|
|
|
|
mask_h = __raw_readq(
|
|
|
|
IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
|
|
|
|
mask_l = __raw_readq(
|
|
|
|
IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
|
|
|
|
|
2006-07-05 21:32:51 +08:00
|
|
|
if (mask_h) {
|
2006-04-04 00:56:36 +08:00
|
|
|
if (mask_h ^ 1)
|
2006-10-08 02:44:33 +08:00
|
|
|
do_IRQ(fls64(mask_h) - 1);
|
2006-04-04 00:56:36 +08:00
|
|
|
else
|
2006-10-08 02:44:33 +08:00
|
|
|
do_IRQ(63 + fls64(mask_l));
|
2006-04-04 00:56:36 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|