2019-05-29 22:17:58 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-03-04 08:21:53 +08:00
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/*
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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*/
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2015-05-16 20:32:17 +08:00
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#ifndef __LPASS_LPAIF_REG_H__
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#define __LPASS_LPAIF_REG_H__
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2015-03-04 08:21:53 +08:00
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/* LPAIF I2S */
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2015-05-16 20:32:17 +08:00
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#define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
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(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
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2015-03-04 08:21:53 +08:00
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2015-05-16 20:32:17 +08:00
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#define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
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2015-03-04 08:21:53 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_LOOPBACK_DISABLE 0
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#define LPAIF_I2SCTL_LOOPBACK_ENABLE 1
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#define LPAIF_I2SCTL_SPKEN_DISABLE 0
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#define LPAIF_I2SCTL_SPKEN_ENABLE 1
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2015-03-04 08:21:53 +08:00
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ASoC: qcom: lpass-cpu: Make I2S SD lines configurable
The LPASS hardware allows configuring the MI2S SD lines to use
when playing/recording audio. However, at the moment the lpass-cpu
driver has SD0 hard-coded for mono/stereo (or additional fixed
SD lines for more channels).
For weird reasons there seems to be hardware that uses one of the
other SD lines for mono/stereo. For example, some Samsung devices
use an external Speaker amplifier connected to Quaternary MI2S.
For some reason, the SD line for audio playback was connected to
SD1 rather than SD0. (I have no idea why...)
At the moment, the lpass-cpu driver cannot be configured to work
for the Speaker on these devices.
The q6afe driver already allows configuring the MI2S SD lines
through the "qcom,sd-lines" device tree property, but this works
only when routing audio through the ADSP.
This commit adds a very similar configuration for the lpass-cpu driver.
It is now possible to add additional subnodes to the lpass device in
the device tree, to configure the SD lines for playback and/or capture.
E.g. for the Samsung devices mentioned above:
&lpass {
dai@3 {
reg = <MI2S_QUATERNARY>;
qcom,playback-sd-lines = <1>;
};
};
qcom,playback/capture-sd-lines takes a list of SD lines (0-3)
in the same format as the q6afe driver. (The difference here is that
q6afe has separate DAIs for playback/capture, while lpass-cpu has one
for both...)
For backwards compatibility with older device trees, the lpass-cpu driver
defaults to LPAIF_I2SCTL_MODE_8CH if the subnode for a DAI is missing.
This is equivalent to the previous behavior: Up to 8 channels can be
configured, and SD0/QUAT01 will be chosen when setting up a stream
with fewer channels.
This allows the speaker to work on Samsung MSM8916 devices
that use an external speaker amplifier.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200425184657.121991-2-stephan@gerhold.net
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-26 02:46:57 +08:00
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#define LPAIF_I2SCTL_MODE_NONE 0
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#define LPAIF_I2SCTL_MODE_SD0 1
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#define LPAIF_I2SCTL_MODE_SD1 2
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#define LPAIF_I2SCTL_MODE_SD2 3
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#define LPAIF_I2SCTL_MODE_SD3 4
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#define LPAIF_I2SCTL_MODE_QUAD01 5
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#define LPAIF_I2SCTL_MODE_QUAD23 6
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#define LPAIF_I2SCTL_MODE_6CH 7
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#define LPAIF_I2SCTL_MODE_8CH 8
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_MODE_10CH 9
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#define LPAIF_I2SCTL_MODE_12CH 10
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#define LPAIF_I2SCTL_MODE_14CH 11
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#define LPAIF_I2SCTL_MODE_16CH 12
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#define LPAIF_I2SCTL_MODE_SD4 13
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#define LPAIF_I2SCTL_MODE_SD5 14
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#define LPAIF_I2SCTL_MODE_SD6 15
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#define LPAIF_I2SCTL_MODE_SD7 16
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#define LPAIF_I2SCTL_MODE_QUAD45 17
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#define LPAIF_I2SCTL_MODE_QUAD47 18
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#define LPAIF_I2SCTL_MODE_8CH_2 19
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ASoC: qcom: lpass-cpu: Make I2S SD lines configurable
The LPASS hardware allows configuring the MI2S SD lines to use
when playing/recording audio. However, at the moment the lpass-cpu
driver has SD0 hard-coded for mono/stereo (or additional fixed
SD lines for more channels).
For weird reasons there seems to be hardware that uses one of the
other SD lines for mono/stereo. For example, some Samsung devices
use an external Speaker amplifier connected to Quaternary MI2S.
For some reason, the SD line for audio playback was connected to
SD1 rather than SD0. (I have no idea why...)
At the moment, the lpass-cpu driver cannot be configured to work
for the Speaker on these devices.
The q6afe driver already allows configuring the MI2S SD lines
through the "qcom,sd-lines" device tree property, but this works
only when routing audio through the ADSP.
This commit adds a very similar configuration for the lpass-cpu driver.
It is now possible to add additional subnodes to the lpass device in
the device tree, to configure the SD lines for playback and/or capture.
E.g. for the Samsung devices mentioned above:
&lpass {
dai@3 {
reg = <MI2S_QUATERNARY>;
qcom,playback-sd-lines = <1>;
};
};
qcom,playback/capture-sd-lines takes a list of SD lines (0-3)
in the same format as the q6afe driver. (The difference here is that
q6afe has separate DAIs for playback/capture, while lpass-cpu has one
for both...)
For backwards compatibility with older device trees, the lpass-cpu driver
defaults to LPAIF_I2SCTL_MODE_8CH if the subnode for a DAI is missing.
This is equivalent to the previous behavior: Up to 8 channels can be
configured, and SD0/QUAT01 will be chosen when setting up a stream
with fewer channels.
This allows the speaker to work on Samsung MSM8916 devices
that use an external speaker amplifier.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200425184657.121991-2-stephan@gerhold.net
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-04-26 02:46:57 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_SPKMODE(mode) mode
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2015-03-04 08:21:53 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_SPKMONO_STEREO 0
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#define LPAIF_I2SCTL_SPKMONO_MONO 1
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2015-03-04 08:21:53 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_MICEN_DISABLE 0
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#define LPAIF_I2SCTL_MICEN_ENABLE 1
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2016-02-11 20:18:06 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_MICMODE(mode) mode
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2016-02-11 20:18:06 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_MICMONO_STEREO 0
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#define LPAIF_I2SCTL_MICMONO_MONO 1
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2016-02-11 20:18:06 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_WSSRC_INTERNAL 0
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#define LPAIF_I2SCTL_WSSRC_EXTERNAL 1
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2015-03-04 08:21:53 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_I2SCTL_BITWIDTH_16 0
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#define LPAIF_I2SCTL_BITWIDTH_24 1
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#define LPAIF_I2SCTL_BITWIDTH_32 2
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2015-03-04 08:21:53 +08:00
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2020-11-24 00:17:53 +08:00
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#define LPAIF_I2SCTL_RESET_STATE 0x003C0004
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#define LPAIF_DMACTL_RESET_STATE 0x00200000
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2015-03-04 08:21:53 +08:00
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/* LPAIF IRQ */
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2015-05-16 20:32:17 +08:00
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#define LPAIF_IRQ_REG_ADDR(v, addr, port) \
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(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
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2015-03-04 08:21:53 +08:00
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2015-05-16 20:32:17 +08:00
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#define LPAIF_IRQ_PORT_HOST 0
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2015-03-04 08:21:53 +08:00
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2015-05-16 20:32:17 +08:00
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#define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
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#define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
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#define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
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2015-03-04 08:21:53 +08:00
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2022-02-24 23:33:43 +08:00
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/* LPAIF RXTX IRQ */
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#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
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(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
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#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
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#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
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#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
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/* LPAIF VA IRQ */
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#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
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(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
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#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
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#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
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#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
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2020-10-08 13:17:01 +08:00
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#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
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((v->hdmi_irq_reg_base) + (addr))
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#define LPASS_HDMITX_APP_IRQEN_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
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#define LPASS_HDMITX_APP_IRQSTAT_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
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#define LPASS_HDMITX_APP_IRQCLEAR_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
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2015-03-04 08:21:53 +08:00
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#define LPAIF_IRQ_BITSTRIDE 3
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2015-05-16 20:32:17 +08:00
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2015-03-04 08:21:53 +08:00
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#define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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#define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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#define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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2015-05-16 20:32:17 +08:00
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2015-03-04 08:21:53 +08:00
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#define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
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2020-10-08 13:17:01 +08:00
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#define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan))
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#define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) (1 << (24 + chan))
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#define LPAIF_IRQ_HDMI_METADONE BIT(23)
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2015-03-04 08:21:53 +08:00
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/* LPAIF DMA */
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2020-10-08 13:17:01 +08:00
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#define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
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(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
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#define LPAIF_HDMI_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
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#define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
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#define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
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#define LPAIF_HDMI_RDMABUFF_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
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#define LPAIF_HDMI_RDMACURR_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
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#define LPAIF_HDMI_RDMAPER_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
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#define LPAIF_HDMI_RDMAPERCNT_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
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2015-03-04 08:21:53 +08:00
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2015-05-16 20:32:17 +08:00
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#define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
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(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
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2015-03-04 08:21:53 +08:00
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2015-05-16 20:32:17 +08:00
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#define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT)
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2015-03-04 08:21:53 +08:00
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2015-05-16 20:32:17 +08:00
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#define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
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#define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
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#define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
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#define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
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#define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
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#define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
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2015-03-04 08:21:53 +08:00
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2016-02-11 20:18:14 +08:00
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#define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
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(v->wrdma_reg_base + (addr) + \
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v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
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#define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
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#define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
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#define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
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#define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
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#define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
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#define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
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2020-10-08 13:17:01 +08:00
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#define LPAIF_INTFDMA_REG(v, chan, reg, dai_id) \
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2021-01-25 18:44:42 +08:00
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((dai_id == LPASS_DP_RX) ? \
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2020-10-08 13:17:01 +08:00
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LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
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LPAIF_RDMA##reg##_REG(v, chan))
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#define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id) \
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((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
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(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
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LPAIF_WRDMA##reg##_REG(v, chan))
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2022-02-24 23:33:43 +08:00
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#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
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#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
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#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
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#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
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#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
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#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
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#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? \
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(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
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(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
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#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? \
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(v->rxtx_wrdma_reg_base + (addr) + \
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v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
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(v->va_wrdma_reg_base + (addr) + \
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v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
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#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
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LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
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#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
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LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
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#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
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((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
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__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
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__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
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#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
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((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
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LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
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LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
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#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
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LPAIF_DMACTL_REG(v, chan, dir, dai_id))
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2016-02-11 20:18:20 +08:00
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2020-08-14 18:53:01 +08:00
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#define LPAIF_DMACTL_BURSTEN_SINGLE 0
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#define LPAIF_DMACTL_BURSTEN_INCR4 1
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#define LPAIF_DMACTL_WPSCNT_ONE 0
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#define LPAIF_DMACTL_WPSCNT_TWO 1
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#define LPAIF_DMACTL_WPSCNT_THREE 2
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#define LPAIF_DMACTL_WPSCNT_FOUR 3
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#define LPAIF_DMACTL_WPSCNT_SIX 5
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#define LPAIF_DMACTL_WPSCNT_EIGHT 7
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#define LPAIF_DMACTL_WPSCNT_TEN 9
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#define LPAIF_DMACTL_WPSCNT_TWELVE 11
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#define LPAIF_DMACTL_WPSCNT_FOURTEEN 13
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#define LPAIF_DMACTL_WPSCNT_SIXTEEN 15
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#define LPAIF_DMACTL_AUDINTF(id) id
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#define LPAIF_DMACTL_FIFOWM_1 0
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#define LPAIF_DMACTL_FIFOWM_2 1
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#define LPAIF_DMACTL_FIFOWM_3 2
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#define LPAIF_DMACTL_FIFOWM_4 3
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#define LPAIF_DMACTL_FIFOWM_5 4
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#define LPAIF_DMACTL_FIFOWM_6 5
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#define LPAIF_DMACTL_FIFOWM_7 6
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#define LPAIF_DMACTL_FIFOWM_8 7
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#define LPAIF_DMACTL_FIFOWM_9 8
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#define LPAIF_DMACTL_FIFOWM_10 9
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#define LPAIF_DMACTL_FIFOWM_11 10
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#define LPAIF_DMACTL_FIFOWM_12 11
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#define LPAIF_DMACTL_FIFOWM_13 12
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#define LPAIF_DMACTL_FIFOWM_14 13
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#define LPAIF_DMACTL_FIFOWM_15 14
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#define LPAIF_DMACTL_FIFOWM_16 15
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#define LPAIF_DMACTL_FIFOWM_17 16
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#define LPAIF_DMACTL_FIFOWM_18 17
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#define LPAIF_DMACTL_FIFOWM_19 18
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#define LPAIF_DMACTL_FIFOWM_20 19
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#define LPAIF_DMACTL_FIFOWM_21 20
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#define LPAIF_DMACTL_FIFOWM_22 21
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#define LPAIF_DMACTL_FIFOWM_23 22
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#define LPAIF_DMACTL_FIFOWM_24 23
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#define LPAIF_DMACTL_FIFOWM_25 24
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#define LPAIF_DMACTL_FIFOWM_26 25
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#define LPAIF_DMACTL_FIFOWM_27 26
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#define LPAIF_DMACTL_FIFOWM_28 27
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#define LPAIF_DMACTL_FIFOWM_29 28
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#define LPAIF_DMACTL_FIFOWM_30 29
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#define LPAIF_DMACTL_FIFOWM_31 30
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#define LPAIF_DMACTL_FIFOWM_32 31
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#define LPAIF_DMACTL_ENABLE_OFF 0
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#define LPAIF_DMACTL_ENABLE_ON 1
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#define LPAIF_DMACTL_DYNCLK_OFF 0
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#define LPAIF_DMACTL_DYNCLK_ON 1
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2015-05-16 20:32:17 +08:00
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#endif /* __LPASS_LPAIF_REG_H__ */
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