2009-02-18 09:08:50 +08:00
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/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <linux/seq_file.h>
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2013-10-16 01:55:29 +08:00
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#include <linux/circ_buf.h>
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2013-10-16 19:30:34 +08:00
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#include <linux/ctype.h>
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2009-10-14 05:20:20 +08:00
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#include <linux/debugfs.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2011-08-31 06:16:33 +08:00
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#include <linux/export.h>
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2013-08-08 01:30:54 +08:00
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#include <linux/list_sort.h>
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2013-08-20 17:29:23 +08:00
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#include <asm/msr-index.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drmP.h>
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2010-09-02 00:47:52 +08:00
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#include "intel_drv.h"
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2010-11-01 19:35:28 +08:00
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#include "intel_ringbuffer.h"
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2012-10-03 01:01:07 +08:00
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#include <drm/i915_drm.h>
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2009-02-18 09:08:50 +08:00
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#include "i915_drv.h"
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2010-09-21 00:36:15 +08:00
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enum {
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2010-10-19 17:36:51 +08:00
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ACTIVE_LIST,
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2010-09-21 00:36:15 +08:00
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INACTIVE_LIST,
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2010-09-26 18:19:33 +08:00
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PINNED_LIST,
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2010-09-21 00:36:15 +08:00
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};
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2009-02-18 09:08:50 +08:00
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2013-10-16 01:55:39 +08:00
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/* As the drm_debugfs_init() routines are called before dev->dev_private is
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* allocated we need to hook into the minor for release. */
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static int
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drm_add_fake_info_node(struct drm_minor *minor,
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struct dentry *ent,
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const void *key)
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{
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struct drm_info_node *node;
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node = kmalloc(sizeof(*node), GFP_KERNEL);
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if (node == NULL) {
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debugfs_remove(ent);
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return -ENOMEM;
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}
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node->minor = minor;
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node->dent = ent;
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node->info_ent = (void *) key;
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mutex_lock(&minor->debugfs_lock);
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list_add(&node->list, &minor->debugfs_list);
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mutex_unlock(&minor->debugfs_lock);
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return 0;
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}
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2010-08-25 23:03:34 +08:00
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static int i915_capabilities(struct seq_file *m, void *data)
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{
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2014-05-13 22:30:28 +08:00
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struct drm_info_node *node = m->private;
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2010-08-25 23:03:34 +08:00
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struct drm_device *dev = node->minor->dev;
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const struct intel_device_info *info = INTEL_INFO(dev);
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seq_printf(m, "gen: %d\n", info->gen);
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2011-10-15 05:17:41 +08:00
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seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
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2013-04-23 23:37:17 +08:00
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#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
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#define SEP_SEMICOLON ;
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DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
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#undef PRINT_FLAG
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#undef SEP_SEMICOLON
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2010-08-25 23:03:34 +08:00
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return 0;
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}
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2009-02-18 09:08:50 +08:00
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2016-05-12 21:18:52 +08:00
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static char get_active_flag(struct drm_i915_gem_object *obj)
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2009-02-11 22:26:38 +08:00
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{
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2016-04-15 18:34:52 +08:00
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return obj->active ? '*' : ' ';
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2009-02-11 22:26:38 +08:00
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}
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2016-05-12 21:18:52 +08:00
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static char get_pin_flag(struct drm_i915_gem_object *obj)
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2016-04-15 18:34:52 +08:00
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{
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return obj->pin_display ? 'p' : ' ';
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}
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2016-05-12 21:18:52 +08:00
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static char get_tiling_flag(struct drm_i915_gem_object *obj)
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2009-02-11 22:26:38 +08:00
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{
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2011-08-17 03:34:10 +08:00
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switch (obj->tiling_mode) {
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default:
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2016-04-15 18:34:52 +08:00
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case I915_TILING_NONE: return ' ';
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case I915_TILING_X: return 'X';
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case I915_TILING_Y: return 'Y';
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2011-08-17 03:34:10 +08:00
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}
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2009-02-11 22:26:38 +08:00
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}
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2016-05-12 21:18:52 +08:00
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static char get_global_flag(struct drm_i915_gem_object *obj)
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2016-04-15 18:34:52 +08:00
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{
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return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
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}
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2016-05-12 21:18:52 +08:00
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static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
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2013-08-01 08:00:00 +08:00
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{
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2016-04-15 18:34:52 +08:00
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return obj->mapping ? 'M' : ' ';
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2013-08-01 08:00:00 +08:00
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}
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2015-07-01 18:51:10 +08:00
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static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
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{
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u64 size = 0;
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struct i915_vma *vma;
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2016-02-26 19:03:19 +08:00
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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2016-02-26 19:03:20 +08:00
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if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
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2015-07-01 18:51:10 +08:00
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size += vma->node.size;
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}
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return size;
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}
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2010-08-26 05:45:57 +08:00
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static void
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describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
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{
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2015-04-27 20:41:17 +08:00
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struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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2016-03-16 19:00:36 +08:00
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struct intel_engine_cs *engine;
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2013-08-01 08:00:00 +08:00
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struct i915_vma *vma;
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2013-12-07 06:10:55 +08:00
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int pin_count = 0;
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2016-03-24 02:19:53 +08:00
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enum intel_engine_id id;
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2013-12-07 06:10:55 +08:00
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2016-04-03 21:14:20 +08:00
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lockdep_assert_held(&obj->base.dev->struct_mutex);
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2016-04-15 18:34:52 +08:00
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seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
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2010-08-26 05:45:57 +08:00
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&obj->base,
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2016-04-15 18:34:52 +08:00
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get_active_flag(obj),
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2010-08-26 05:45:57 +08:00
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get_pin_flag(obj),
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get_tiling_flag(obj),
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2013-08-01 08:00:00 +08:00
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get_global_flag(obj),
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2016-04-15 18:34:52 +08:00
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get_pin_mapped_flag(obj),
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2011-12-21 00:54:15 +08:00
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obj->base.size / 1024,
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2010-08-26 05:45:57 +08:00
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obj->base.read_domains,
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2015-04-27 20:41:17 +08:00
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obj->base.write_domain);
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2016-03-24 02:19:53 +08:00
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for_each_engine_id(engine, dev_priv, id)
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2015-04-27 20:41:17 +08:00
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seq_printf(m, "%x ",
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2016-03-24 02:19:53 +08:00
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i915_gem_request_get_seqno(obj->last_read_req[id]));
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2015-04-27 20:41:17 +08:00
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seq_printf(m, "] %x %x%s%s%s",
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2014-11-25 02:49:26 +08:00
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i915_gem_request_get_seqno(obj->last_write_req),
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i915_gem_request_get_seqno(obj->last_fenced_req),
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2014-08-22 21:41:39 +08:00
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i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
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2010-08-26 05:45:57 +08:00
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obj->dirty ? " dirty" : "",
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obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
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if (obj->base.name)
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seq_printf(m, " (name: %d)", obj->base.name);
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2016-02-26 19:03:19 +08:00
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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2013-12-07 06:10:55 +08:00
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if (vma->pin_count > 0)
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pin_count++;
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2015-02-25 21:17:48 +08:00
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}
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seq_printf(m, " (pinned x %d)", pin_count);
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2013-08-09 19:25:09 +08:00
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if (obj->pin_display)
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seq_printf(m, " (display)");
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2010-08-26 05:45:57 +08:00
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if (obj->fence_reg != I915_FENCE_REG_NONE)
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seq_printf(m, " (fence: %d)", obj->fence_reg);
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2016-02-26 19:03:19 +08:00
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list_for_each_entry(vma, &obj->vma_list, obj_link) {
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2015-05-27 17:52:32 +08:00
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seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
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2016-02-26 19:03:20 +08:00
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vma->is_ggtt ? "g" : "pp",
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2015-05-27 17:52:32 +08:00
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vma->node.start, vma->node.size);
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2016-02-26 19:03:20 +08:00
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if (vma->is_ggtt)
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seq_printf(m, ", type: %u", vma->ggtt_view.type);
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seq_puts(m, ")");
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2013-08-01 08:00:00 +08:00
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}
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2012-11-15 19:32:21 +08:00
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if (obj->stolen)
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2015-01-23 16:05:06 +08:00
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seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
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2015-04-08 00:28:24 +08:00
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if (obj->pin_display || obj->fault_mappable) {
|
2010-11-24 20:23:44 +08:00
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char s[3], *t = s;
|
2015-04-08 00:28:24 +08:00
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|
|
if (obj->pin_display)
|
2010-11-24 20:23:44 +08:00
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*t++ = 'p';
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|
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if (obj->fault_mappable)
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|
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|
*t++ = 'f';
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*t = '\0';
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seq_printf(m, " (%s mappable)", s);
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}
|
2015-04-27 20:41:17 +08:00
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|
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if (obj->last_write_req != NULL)
|
2014-11-25 02:49:43 +08:00
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seq_printf(m, " (%s)",
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2016-03-16 19:00:39 +08:00
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|
|
i915_gem_request_get_engine(obj->last_write_req)->name);
|
2014-06-18 20:46:49 +08:00
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|
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if (obj->frontbuffer_bits)
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seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
|
2010-08-26 05:45:57 +08:00
|
|
|
}
|
|
|
|
|
2016-05-24 21:53:34 +08:00
|
|
|
static void describe_ctx(struct seq_file *m, struct i915_gem_context *ctx)
|
drm/i915: Do remaps for all contexts
On both Ivybridge and Haswell, row remapping information is saved and
restored with context. This means, we never actually properly supported
the l3 remapping because our sysfs interface is asynchronous (and not
tied to any context), and the known faulty HW would be reused by the
next context to run.
Not that due to the asynchronous nature of the sysfs entry, there is no
point modifying the registers for the existing context. Instead we set a
flag for all contexts to load the correct remapping information on the
next run. Interested clients can use debugfs to determine whether or not
the row has been remapped.
One could propose at this point that we just do the remapping in the
kernel. I guess since we have to maintain the sysfs interface anyway,
I'm not sure how useful it is, and I do like keeping the policy in
userspace; (it wasn't my original decision to make the
interface the way it is, so I'm not attached).
v2: Force a context switch when we have a remap on the next switch.
(Ville)
Don't let userspace use the interface with disabled contexts.
v3: Don't force a context switch, just let it nop
Improper context slice remap initialization, 1<<1 instead of 1<<i, but I
rewrote it to avoid a second round of confusion.
Error print moved to error path (All Ville)
Added a comment on why the slice remap initialization happens.
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-19 10:03:18 +08:00
|
|
|
{
|
2014-07-03 23:27:59 +08:00
|
|
|
seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
|
drm/i915: Do remaps for all contexts
On both Ivybridge and Haswell, row remapping information is saved and
restored with context. This means, we never actually properly supported
the l3 remapping because our sysfs interface is asynchronous (and not
tied to any context), and the known faulty HW would be reused by the
next context to run.
Not that due to the asynchronous nature of the sysfs entry, there is no
point modifying the registers for the existing context. Instead we set a
flag for all contexts to load the correct remapping information on the
next run. Interested clients can use debugfs to determine whether or not
the row has been remapped.
One could propose at this point that we just do the remapping in the
kernel. I guess since we have to maintain the sysfs interface anyway,
I'm not sure how useful it is, and I do like keeping the policy in
userspace; (it wasn't my original decision to make the
interface the way it is, so I'm not attached).
v2: Force a context switch when we have a remap on the next switch.
(Ville)
Don't let userspace use the interface with disabled contexts.
v3: Don't force a context switch, just let it nop
Improper context slice remap initialization, 1<<1 instead of 1<<i, but I
rewrote it to avoid a second round of confusion.
Error print moved to error path (All Ville)
Added a comment on why the slice remap initialization happens.
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-19 10:03:18 +08:00
|
|
|
seq_putc(m, ctx->remap_slice ? 'R' : 'r');
|
|
|
|
seq_putc(m, ' ');
|
|
|
|
}
|
|
|
|
|
2009-02-18 09:08:51 +08:00
|
|
|
static int i915_gem_object_list_info(struct seq_file *m, void *data)
|
2009-02-18 09:08:50 +08:00
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2009-02-18 09:08:51 +08:00
|
|
|
uintptr_t list = (uintptr_t) node->info_ent->data;
|
|
|
|
struct list_head *head;
|
2009-02-18 09:08:50 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2016-03-30 21:57:10 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2013-08-01 08:00:14 +08:00
|
|
|
struct i915_vma *vma;
|
2015-06-25 23:35:05 +08:00
|
|
|
u64 total_obj_size, total_gtt_size;
|
2010-09-26 18:44:19 +08:00
|
|
|
int count, ret;
|
2010-07-03 14:58:38 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2009-02-18 09:08:50 +08:00
|
|
|
|
2013-08-01 08:00:14 +08:00
|
|
|
/* FIXME: the user of this interface might want more than just GGTT */
|
2009-02-18 09:08:51 +08:00
|
|
|
switch (list) {
|
|
|
|
case ACTIVE_LIST:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "Active:\n");
|
2016-03-30 21:57:10 +08:00
|
|
|
head = &ggtt->base.active_list;
|
2009-02-18 09:08:51 +08:00
|
|
|
break;
|
|
|
|
case INACTIVE_LIST:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "Inactive:\n");
|
2016-03-30 21:57:10 +08:00
|
|
|
head = &ggtt->base.inactive_list;
|
2009-02-18 09:08:51 +08:00
|
|
|
break;
|
|
|
|
default:
|
2010-07-03 14:58:38 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return -EINVAL;
|
2009-02-18 09:08:50 +08:00
|
|
|
}
|
|
|
|
|
2010-09-26 18:44:19 +08:00
|
|
|
total_obj_size = total_gtt_size = count = 0;
|
2016-02-26 19:03:19 +08:00
|
|
|
list_for_each_entry(vma, head, vm_link) {
|
2013-08-01 08:00:14 +08:00
|
|
|
seq_printf(m, " ");
|
|
|
|
describe_obj(m, vma->obj);
|
|
|
|
seq_printf(m, "\n");
|
|
|
|
total_obj_size += vma->obj->base.size;
|
|
|
|
total_gtt_size += vma->node.size;
|
2010-09-26 18:44:19 +08:00
|
|
|
count++;
|
2009-02-18 09:08:50 +08:00
|
|
|
}
|
2010-07-03 14:58:38 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-03-21 02:54:25 +08:00
|
|
|
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
|
2010-09-26 18:44:19 +08:00
|
|
|
count, total_obj_size, total_gtt_size);
|
2009-02-18 09:08:50 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-08-08 01:30:54 +08:00
|
|
|
static int obj_rank_by_stolen(void *priv,
|
|
|
|
struct list_head *A, struct list_head *B)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *a =
|
2013-08-14 17:38:33 +08:00
|
|
|
container_of(A, struct drm_i915_gem_object, obj_exec_link);
|
2013-08-08 01:30:54 +08:00
|
|
|
struct drm_i915_gem_object *b =
|
2013-08-14 17:38:33 +08:00
|
|
|
container_of(B, struct drm_i915_gem_object, obj_exec_link);
|
2013-08-08 01:30:54 +08:00
|
|
|
|
2015-09-29 05:08:50 +08:00
|
|
|
if (a->stolen->start < b->stolen->start)
|
|
|
|
return -1;
|
|
|
|
if (a->stolen->start > b->stolen->start)
|
|
|
|
return 1;
|
|
|
|
return 0;
|
2013-08-08 01:30:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2013-08-08 01:30:54 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_object *obj;
|
2015-06-25 23:35:05 +08:00
|
|
|
u64 total_obj_size, total_gtt_size;
|
2013-08-08 01:30:54 +08:00
|
|
|
LIST_HEAD(stolen);
|
|
|
|
int count, ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
total_obj_size = total_gtt_size = count = 0;
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
|
|
|
if (obj->stolen == NULL)
|
|
|
|
continue;
|
|
|
|
|
2013-08-14 17:38:33 +08:00
|
|
|
list_add(&obj->obj_exec_link, &stolen);
|
2013-08-08 01:30:54 +08:00
|
|
|
|
|
|
|
total_obj_size += obj->base.size;
|
2015-07-01 18:51:10 +08:00
|
|
|
total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
|
2013-08-08 01:30:54 +08:00
|
|
|
count++;
|
|
|
|
}
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
|
|
|
|
if (obj->stolen == NULL)
|
|
|
|
continue;
|
|
|
|
|
2013-08-14 17:38:33 +08:00
|
|
|
list_add(&obj->obj_exec_link, &stolen);
|
2013-08-08 01:30:54 +08:00
|
|
|
|
|
|
|
total_obj_size += obj->base.size;
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
list_sort(NULL, &stolen, obj_rank_by_stolen);
|
|
|
|
seq_puts(m, "Stolen:\n");
|
|
|
|
while (!list_empty(&stolen)) {
|
2013-08-14 17:38:33 +08:00
|
|
|
obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
|
2013-08-08 01:30:54 +08:00
|
|
|
seq_puts(m, " ");
|
|
|
|
describe_obj(m, obj);
|
|
|
|
seq_putc(m, '\n');
|
2013-08-14 17:38:33 +08:00
|
|
|
list_del_init(&obj->obj_exec_link);
|
2013-08-08 01:30:54 +08:00
|
|
|
}
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
|
2013-08-08 01:30:54 +08:00
|
|
|
count, total_obj_size, total_gtt_size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-11-24 20:23:44 +08:00
|
|
|
#define count_objects(list, member) do { \
|
|
|
|
list_for_each_entry(obj, list, member) { \
|
2015-07-01 18:51:10 +08:00
|
|
|
size += i915_gem_obj_total_ggtt_size(obj); \
|
2010-11-24 20:23:44 +08:00
|
|
|
++count; \
|
|
|
|
if (obj->map_and_fenceable) { \
|
2013-07-06 05:41:04 +08:00
|
|
|
mappable_size += i915_gem_obj_ggtt_size(obj); \
|
2010-11-24 20:23:44 +08:00
|
|
|
++mappable_count; \
|
|
|
|
} \
|
|
|
|
} \
|
2011-08-17 03:34:10 +08:00
|
|
|
} while (0)
|
2010-11-24 20:23:44 +08:00
|
|
|
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
struct file_stats {
|
2014-03-19 21:45:45 +08:00
|
|
|
struct drm_i915_file_private *file_priv;
|
2015-06-25 23:35:05 +08:00
|
|
|
unsigned long count;
|
|
|
|
u64 total, unbound;
|
|
|
|
u64 global, shared;
|
|
|
|
u64 active, inactive;
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static int per_file_stats(int id, void *ptr, void *data)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj = ptr;
|
|
|
|
struct file_stats *stats = data;
|
2014-03-19 21:45:45 +08:00
|
|
|
struct i915_vma *vma;
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
|
|
|
|
stats->count++;
|
|
|
|
stats->total += obj->base.size;
|
|
|
|
|
2014-03-19 21:45:46 +08:00
|
|
|
if (obj->base.name || obj->base.dma_buf)
|
|
|
|
stats->shared += obj->base.size;
|
|
|
|
|
2014-03-19 21:45:45 +08:00
|
|
|
if (USES_FULL_PPGTT(obj->base.dev)) {
|
2016-02-26 19:03:19 +08:00
|
|
|
list_for_each_entry(vma, &obj->vma_list, obj_link) {
|
2014-03-19 21:45:45 +08:00
|
|
|
struct i915_hw_ppgtt *ppgtt;
|
|
|
|
|
|
|
|
if (!drm_mm_node_allocated(&vma->node))
|
|
|
|
continue;
|
|
|
|
|
2016-02-26 19:03:20 +08:00
|
|
|
if (vma->is_ggtt) {
|
2014-03-19 21:45:45 +08:00
|
|
|
stats->global += obj->base.size;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
|
2014-08-06 21:04:47 +08:00
|
|
|
if (ppgtt->file_priv != stats->file_priv)
|
2014-03-19 21:45:45 +08:00
|
|
|
continue;
|
|
|
|
|
2014-11-25 02:49:43 +08:00
|
|
|
if (obj->active) /* XXX per-vma statistic */
|
2014-03-19 21:45:45 +08:00
|
|
|
stats->active += obj->base.size;
|
|
|
|
else
|
|
|
|
stats->inactive += obj->base.size;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
} else {
|
2014-03-19 21:45:45 +08:00
|
|
|
if (i915_gem_obj_ggtt_bound(obj)) {
|
|
|
|
stats->global += obj->base.size;
|
2014-11-25 02:49:43 +08:00
|
|
|
if (obj->active)
|
2014-03-19 21:45:45 +08:00
|
|
|
stats->active += obj->base.size;
|
|
|
|
else
|
|
|
|
stats->inactive += obj->base.size;
|
|
|
|
return 0;
|
|
|
|
}
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
}
|
|
|
|
|
2014-03-19 21:45:45 +08:00
|
|
|
if (!list_empty(&obj->global_list))
|
|
|
|
stats->unbound += obj->base.size;
|
|
|
|
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-07 23:20:40 +08:00
|
|
|
#define print_file_stats(m, name, stats) do { \
|
|
|
|
if (stats.count) \
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
|
2015-04-07 23:20:40 +08:00
|
|
|
name, \
|
|
|
|
stats.count, \
|
|
|
|
stats.total, \
|
|
|
|
stats.active, \
|
|
|
|
stats.inactive, \
|
|
|
|
stats.global, \
|
|
|
|
stats.shared, \
|
|
|
|
stats.unbound); \
|
|
|
|
} while (0)
|
2014-12-12 04:13:08 +08:00
|
|
|
|
|
|
|
static void print_batch_pool_stats(struct seq_file *m,
|
|
|
|
struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct file_stats stats;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2016-03-24 19:20:38 +08:00
|
|
|
int j;
|
2014-12-12 04:13:08 +08:00
|
|
|
|
|
|
|
memset(&stats, 0, sizeof(stats));
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2016-03-16 19:00:36 +08:00
|
|
|
for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
|
2015-04-07 23:20:38 +08:00
|
|
|
list_for_each_entry(obj,
|
2016-03-16 19:00:36 +08:00
|
|
|
&engine->batch_pool.cache_list[j],
|
2015-04-07 23:20:38 +08:00
|
|
|
batch_pool_link)
|
|
|
|
per_file_stats(0, obj, &stats);
|
|
|
|
}
|
2015-04-07 23:20:36 +08:00
|
|
|
}
|
2014-12-12 04:13:08 +08:00
|
|
|
|
2015-04-07 23:20:40 +08:00
|
|
|
print_file_stats(m, "[k]batch pool", stats);
|
2014-12-12 04:13:08 +08:00
|
|
|
}
|
|
|
|
|
2013-08-01 08:00:14 +08:00
|
|
|
#define count_vmas(list, member) do { \
|
|
|
|
list_for_each_entry(vma, list, member) { \
|
2015-07-01 18:51:10 +08:00
|
|
|
size += i915_gem_obj_total_ggtt_size(vma->obj); \
|
2013-08-01 08:00:14 +08:00
|
|
|
++count; \
|
|
|
|
if (vma->obj->map_and_fenceable) { \
|
|
|
|
mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
|
|
|
|
++mappable_count; \
|
|
|
|
} \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
static int i915_gem_object_info(struct seq_file *m, void* data)
|
2010-09-30 18:46:12 +08:00
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-09-30 18:46:12 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2016-03-30 21:57:10 +08:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2012-08-20 17:33:30 +08:00
|
|
|
u32 count, mappable_count, purgeable_count;
|
2015-06-25 23:35:05 +08:00
|
|
|
u64 size, mappable_size, purgeable_size;
|
2016-04-15 18:34:53 +08:00
|
|
|
unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
|
|
|
|
u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
|
2010-11-24 20:23:44 +08:00
|
|
|
struct drm_i915_gem_object *obj;
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
struct drm_file *file;
|
2013-08-01 08:00:14 +08:00
|
|
|
struct i915_vma *vma;
|
2010-09-30 18:46:12 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-11-24 20:23:44 +08:00
|
|
|
seq_printf(m, "%u objects, %zu bytes\n",
|
|
|
|
dev_priv->mm.object_count,
|
|
|
|
dev_priv->mm.object_memory);
|
|
|
|
|
|
|
|
size = count = mappable_size = mappable_count = 0;
|
2013-06-01 02:28:48 +08:00
|
|
|
count_objects(&dev_priv->mm.bound_list, global_list);
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
|
2010-11-24 20:23:44 +08:00
|
|
|
count, mappable_count, size, mappable_size);
|
|
|
|
|
|
|
|
size = count = mappable_size = mappable_count = 0;
|
2016-03-30 21:57:10 +08:00
|
|
|
count_vmas(&ggtt->base.active_list, vm_link);
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
|
2010-11-24 20:23:44 +08:00
|
|
|
count, mappable_count, size, mappable_size);
|
|
|
|
|
|
|
|
size = count = mappable_size = mappable_count = 0;
|
2016-03-30 21:57:10 +08:00
|
|
|
count_vmas(&ggtt->base.inactive_list, vm_link);
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
|
2010-11-24 20:23:44 +08:00
|
|
|
count, mappable_count, size, mappable_size);
|
|
|
|
|
2012-08-20 17:33:30 +08:00
|
|
|
size = count = purgeable_size = purgeable_count = 0;
|
2013-06-01 02:28:48 +08:00
|
|
|
list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
|
drm/i915: Track unbound pages
When dealing with a working set larger than the GATT, or even the
mappable aperture when touching through the GTT, we end up with evicting
objects only to rebind them at a new offset again later. Moving an
object into and out of the GTT requires clflushing the pages, thus
causing a double-clflush penalty for rebinding.
To avoid having to clflush on rebinding, we can track the pages as they
are evicted from the GTT and only relinquish those pages on memory
pressure.
As usual, if it were not for the handling of out-of-memory condition and
having to manually shrink our own bo caches, it would be a net reduction
of code. Alas.
Note: The patch also contains a few changes to the last-hope
evict_everything logic in i916_gem_execbuffer.c - we no longer try to
only evict the purgeable stuff in a first try (since that's superflous
and only helps in OOM corner-cases, not fragmented-gtt trashing
situations).
Also, the extraction of the get_pages retry loop from bind_to_gtt (and
other callsites) to get_pages should imo have been a separate patch.
v2: Ditch the newly added put_pages (for unbound objects only) in
i915_gem_reset. A quick irc discussion hasn't revealed any important
reason for this, so if we need this, I'd like to have a git blame'able
explanation for it.
v3: Undo the s/drm_malloc_ab/kmalloc/ in get_pages that Chris noticed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Split out code movements and rant a bit in the commit message
with a few Notes. Done v2]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-20 17:40:46 +08:00
|
|
|
size += obj->base.size, ++count;
|
2012-08-20 17:33:30 +08:00
|
|
|
if (obj->madv == I915_MADV_DONTNEED)
|
|
|
|
purgeable_size += obj->base.size, ++purgeable_count;
|
2016-04-15 18:34:53 +08:00
|
|
|
if (obj->mapping) {
|
|
|
|
pin_mapped_count++;
|
|
|
|
pin_mapped_size += obj->base.size;
|
|
|
|
if (obj->pages_pin_count == 0) {
|
|
|
|
pin_mapped_purgeable_count++;
|
|
|
|
pin_mapped_purgeable_size += obj->base.size;
|
|
|
|
}
|
|
|
|
}
|
2012-08-20 17:33:30 +08:00
|
|
|
}
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
|
drm/i915: Track unbound pages
When dealing with a working set larger than the GATT, or even the
mappable aperture when touching through the GTT, we end up with evicting
objects only to rebind them at a new offset again later. Moving an
object into and out of the GTT requires clflushing the pages, thus
causing a double-clflush penalty for rebinding.
To avoid having to clflush on rebinding, we can track the pages as they
are evicted from the GTT and only relinquish those pages on memory
pressure.
As usual, if it were not for the handling of out-of-memory condition and
having to manually shrink our own bo caches, it would be a net reduction
of code. Alas.
Note: The patch also contains a few changes to the last-hope
evict_everything logic in i916_gem_execbuffer.c - we no longer try to
only evict the purgeable stuff in a first try (since that's superflous
and only helps in OOM corner-cases, not fragmented-gtt trashing
situations).
Also, the extraction of the get_pages retry loop from bind_to_gtt (and
other callsites) to get_pages should imo have been a separate patch.
v2: Ditch the newly added put_pages (for unbound objects only) in
i915_gem_reset. A quick irc discussion hasn't revealed any important
reason for this, so if we need this, I'd like to have a git blame'able
explanation for it.
v3: Undo the s/drm_malloc_ab/kmalloc/ in get_pages that Chris noticed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Split out code movements and rant a bit in the commit message
with a few Notes. Done v2]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-20 17:40:46 +08:00
|
|
|
|
2010-11-24 20:23:44 +08:00
|
|
|
size = count = mappable_size = mappable_count = 0;
|
2013-06-01 02:28:48 +08:00
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
2010-11-24 20:23:44 +08:00
|
|
|
if (obj->fault_mappable) {
|
2013-07-06 05:41:04 +08:00
|
|
|
size += i915_gem_obj_ggtt_size(obj);
|
2010-11-24 20:23:44 +08:00
|
|
|
++count;
|
|
|
|
}
|
2015-04-08 00:28:24 +08:00
|
|
|
if (obj->pin_display) {
|
2013-07-06 05:41:04 +08:00
|
|
|
mappable_size += i915_gem_obj_ggtt_size(obj);
|
2010-11-24 20:23:44 +08:00
|
|
|
++mappable_count;
|
|
|
|
}
|
2012-08-20 17:33:30 +08:00
|
|
|
if (obj->madv == I915_MADV_DONTNEED) {
|
|
|
|
purgeable_size += obj->base.size;
|
|
|
|
++purgeable_count;
|
|
|
|
}
|
2016-04-15 18:34:53 +08:00
|
|
|
if (obj->mapping) {
|
|
|
|
pin_mapped_count++;
|
|
|
|
pin_mapped_size += obj->base.size;
|
|
|
|
if (obj->pages_pin_count == 0) {
|
|
|
|
pin_mapped_purgeable_count++;
|
|
|
|
pin_mapped_purgeable_size += obj->base.size;
|
|
|
|
}
|
|
|
|
}
|
2010-11-24 20:23:44 +08:00
|
|
|
}
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%u purgeable objects, %llu bytes\n",
|
2012-08-20 17:33:30 +08:00
|
|
|
purgeable_count, purgeable_size);
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
|
2010-11-24 20:23:44 +08:00
|
|
|
mappable_count, mappable_size);
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%u fault mappable objects, %llu bytes\n",
|
2010-11-24 20:23:44 +08:00
|
|
|
count, size);
|
2016-04-15 18:34:53 +08:00
|
|
|
seq_printf(m,
|
|
|
|
"%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
|
|
|
|
pin_mapped_count, pin_mapped_purgeable_count,
|
|
|
|
pin_mapped_size, pin_mapped_purgeable_size);
|
2010-11-24 20:23:44 +08:00
|
|
|
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "%llu [%llu] gtt total\n",
|
2016-03-30 21:57:10 +08:00
|
|
|
ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
|
2010-09-30 18:46:12 +08:00
|
|
|
|
2014-12-12 04:13:08 +08:00
|
|
|
seq_putc(m, '\n');
|
|
|
|
print_batch_pool_stats(m, dev_priv);
|
2016-04-27 01:29:41 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
mutex_lock(&dev->filelist_mutex);
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
list_for_each_entry_reverse(file, &dev->filelist, lhead) {
|
|
|
|
struct file_stats stats;
|
2014-01-03 19:42:18 +08:00
|
|
|
struct task_struct *task;
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
|
|
|
|
memset(&stats, 0, sizeof(stats));
|
2014-03-19 21:45:45 +08:00
|
|
|
stats.file_priv = file->driver_priv;
|
2014-06-17 16:56:24 +08:00
|
|
|
spin_lock(&file->table_lock);
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
idr_for_each(&file->object_idr, per_file_stats, &stats);
|
2014-06-17 16:56:24 +08:00
|
|
|
spin_unlock(&file->table_lock);
|
2014-01-03 19:42:18 +08:00
|
|
|
/*
|
|
|
|
* Although we have a valid reference on file->pid, that does
|
|
|
|
* not guarantee that the task_struct who called get_pid() is
|
|
|
|
* still alive (e.g. get_pid(current) => fork() => exit()).
|
|
|
|
* Therefore, we need to protect this ->comm access using RCU.
|
|
|
|
*/
|
|
|
|
rcu_read_lock();
|
|
|
|
task = pid_task(file->pid, PIDTYPE_PID);
|
2014-12-12 04:13:08 +08:00
|
|
|
print_file_stats(m, task ? task->comm : "<unknown>", stats);
|
2014-01-03 19:42:18 +08:00
|
|
|
rcu_read_unlock();
|
drm/i915: Track clients and print their object usage in debugfs
By stashing a pointer of who opened the device and keeping a list of
open fd, we can then walk each client and inspect how many objects they
have open. For example,
i915_gem_objects:
1102 objects, 613646336 bytes
663 [662] objects, 468783104 [468750336] bytes in gtt
37 [37] active objects, 46874624 [46874624] bytes
626 [625] inactive objects, 421908480 [421875712] bytes
282 unbound objects, 6512640 bytes
85 purgeable objects, 6787072 bytes
28 pinned mappable objects, 3686400 bytes
40 fault mappable objects, 27783168 bytes
2145386496 [536870912] gtt total
Xorg: 43 objects, 32243712 bytes (10223616 active, 16683008 inactive, 4096 unbound)
gnome-shell: 30 objects, 28381184 bytes (0 active, 28336128 inactive, 0 unbound)
xonotic-linux64: 1032 objects, 569933824 bytes (46874624 active, 383545344 inactive, 6508544 unbound)
v2: Use existing drm->filelist as pointed out by Ben.
v3: Not even stashing the task_struct is required as Ben pointed out
drm_file->pid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-05 06:49:08 +08:00
|
|
|
}
|
2016-04-27 01:29:41 +08:00
|
|
|
mutex_unlock(&dev->filelist_mutex);
|
2010-09-30 18:46:12 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-25 05:59:49 +08:00
|
|
|
static int i915_gem_gtt_info(struct seq_file *m, void *data)
|
2011-01-10 08:00:24 +08:00
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2011-01-10 08:00:24 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2012-04-24 22:47:30 +08:00
|
|
|
uintptr_t list = (uintptr_t) node->info_ent->data;
|
2011-01-10 08:00:24 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_object *obj;
|
2015-06-25 23:35:05 +08:00
|
|
|
u64 total_obj_size, total_gtt_size;
|
2011-01-10 08:00:24 +08:00
|
|
|
int count, ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
total_obj_size = total_gtt_size = count = 0;
|
2013-06-01 02:28:48 +08:00
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
2013-12-07 06:10:55 +08:00
|
|
|
if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
|
2012-04-24 22:47:30 +08:00
|
|
|
continue;
|
|
|
|
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, " ");
|
2011-01-10 08:00:24 +08:00
|
|
|
describe_obj(m, obj);
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_putc(m, '\n');
|
2011-01-10 08:00:24 +08:00
|
|
|
total_obj_size += obj->base.size;
|
2015-07-01 18:51:10 +08:00
|
|
|
total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
|
2011-01-10 08:00:24 +08:00
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2015-06-25 23:35:05 +08:00
|
|
|
seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
|
2011-01-10 08:00:24 +08:00
|
|
|
count, total_obj_size, total_gtt_size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-17 21:07:52 +08:00
|
|
|
static void i915_dump_pageflip(struct seq_file *m,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_crtc *crtc,
|
|
|
|
struct intel_flip_work *work)
|
|
|
|
{
|
|
|
|
const char pipe = pipe_name(crtc->pipe);
|
|
|
|
u32 pending;
|
2016-05-17 21:07:54 +08:00
|
|
|
int i;
|
2016-05-17 21:07:52 +08:00
|
|
|
|
|
|
|
pending = atomic_read(&work->pending);
|
|
|
|
if (pending) {
|
|
|
|
seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
|
2016-05-17 21:07:54 +08:00
|
|
|
pipe, plane_name(crtc->plane));
|
2016-05-17 21:07:52 +08:00
|
|
|
} else {
|
|
|
|
seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
|
2016-05-17 21:07:54 +08:00
|
|
|
pipe, plane_name(crtc->plane));
|
2016-05-17 21:07:52 +08:00
|
|
|
}
|
|
|
|
|
2016-05-17 21:07:54 +08:00
|
|
|
for (i = 0; i < work->num_planes; i++) {
|
|
|
|
struct intel_plane_state *old_plane_state = work->old_plane_state[i];
|
|
|
|
struct drm_plane *plane = old_plane_state->base.plane;
|
|
|
|
struct drm_i915_gem_request *req = old_plane_state->wait_req;
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
|
|
|
|
seq_printf(m, "[PLANE:%i] part of flip.\n", plane->base.id);
|
|
|
|
|
|
|
|
if (!req) {
|
|
|
|
seq_printf(m, "Plane not associated with any engine\n");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
engine = i915_gem_request_get_engine(req);
|
|
|
|
|
|
|
|
seq_printf(m, "Plane blocked on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
|
2016-05-17 21:07:52 +08:00
|
|
|
engine->name,
|
2016-05-17 21:07:54 +08:00
|
|
|
i915_gem_request_get_seqno(req),
|
2016-05-17 21:07:52 +08:00
|
|
|
dev_priv->next_seqno,
|
|
|
|
engine->get_seqno(engine),
|
2016-05-17 21:07:54 +08:00
|
|
|
i915_gem_request_completed(req, true));
|
|
|
|
}
|
|
|
|
|
2016-05-17 21:07:55 +08:00
|
|
|
seq_printf(m, "Flip queued on frame %d, now %d\n",
|
|
|
|
pending ? work->flip_queued_vblank : -1,
|
2016-05-17 21:07:52 +08:00
|
|
|
intel_crtc_get_vblank_counter(crtc));
|
|
|
|
}
|
|
|
|
|
2010-09-02 00:47:52 +08:00
|
|
|
static int i915_gem_pageflip_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-09-02 00:47:52 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 14:13:24 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-09-02 00:47:52 +08:00
|
|
|
struct intel_crtc *crtc;
|
2014-06-18 04:34:37 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-09-02 00:47:52 +08:00
|
|
|
|
2014-05-14 06:32:22 +08:00
|
|
|
for_each_intel_crtc(dev, crtc) {
|
2011-02-08 04:26:52 +08:00
|
|
|
const char pipe = pipe_name(crtc->pipe);
|
|
|
|
const char plane = plane_name(crtc->plane);
|
2016-05-17 21:07:49 +08:00
|
|
|
struct intel_flip_work *work;
|
2010-09-02 00:47:52 +08:00
|
|
|
|
2014-09-15 20:55:22 +08:00
|
|
|
spin_lock_irq(&dev->event_lock);
|
2016-05-17 21:07:52 +08:00
|
|
|
if (list_empty(&crtc->flip_work)) {
|
2011-02-08 04:26:52 +08:00
|
|
|
seq_printf(m, "No flip due on pipe %c (plane %c)\n",
|
2010-09-02 00:47:52 +08:00
|
|
|
pipe, plane);
|
|
|
|
} else {
|
2016-05-17 21:07:52 +08:00
|
|
|
list_for_each_entry(work, &crtc->flip_work, head) {
|
|
|
|
i915_dump_pageflip(m, dev_priv, crtc, work);
|
|
|
|
seq_puts(m, "\n");
|
2010-09-02 00:47:52 +08:00
|
|
|
}
|
|
|
|
}
|
2014-09-15 20:55:22 +08:00
|
|
|
spin_unlock_irq(&dev->event_lock);
|
2010-09-02 00:47:52 +08:00
|
|
|
}
|
|
|
|
|
2014-06-18 04:34:37 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2010-09-02 00:47:52 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-12-12 04:13:08 +08:00
|
|
|
static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_object *obj;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2015-04-07 23:20:38 +08:00
|
|
|
int total = 0;
|
2016-03-24 19:20:38 +08:00
|
|
|
int ret, j;
|
2014-12-12 04:13:08 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2016-03-16 19:00:36 +08:00
|
|
|
for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
|
2015-04-07 23:20:38 +08:00
|
|
|
int count;
|
|
|
|
|
|
|
|
count = 0;
|
|
|
|
list_for_each_entry(obj,
|
2016-03-16 19:00:36 +08:00
|
|
|
&engine->batch_pool.cache_list[j],
|
2015-04-07 23:20:38 +08:00
|
|
|
batch_pool_link)
|
|
|
|
count++;
|
|
|
|
seq_printf(m, "%s cache[%d]: %d objects\n",
|
2016-03-16 19:00:36 +08:00
|
|
|
engine->name, j, count);
|
2015-04-07 23:20:38 +08:00
|
|
|
|
|
|
|
list_for_each_entry(obj,
|
2016-03-16 19:00:36 +08:00
|
|
|
&engine->batch_pool.cache_list[j],
|
2015-04-07 23:20:38 +08:00
|
|
|
batch_pool_link) {
|
|
|
|
seq_puts(m, " ");
|
|
|
|
describe_obj(m, obj);
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
|
|
|
|
total += count;
|
2015-04-07 23:20:36 +08:00
|
|
|
}
|
2014-12-12 04:13:08 +08:00
|
|
|
}
|
|
|
|
|
2015-04-07 23:20:38 +08:00
|
|
|
seq_printf(m, "total: %d\n", total);
|
2014-12-12 04:13:08 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-02-18 09:08:50 +08:00
|
|
|
static int i915_gem_request_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2009-02-18 09:08:50 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2015-05-21 20:21:25 +08:00
|
|
|
struct drm_i915_gem_request *req;
|
2016-03-24 19:20:38 +08:00
|
|
|
int ret, any;
|
2010-07-03 14:58:38 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2009-02-18 09:08:50 +08:00
|
|
|
|
2015-04-01 17:36:56 +08:00
|
|
|
any = 0;
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2015-04-01 17:36:56 +08:00
|
|
|
int count;
|
|
|
|
|
|
|
|
count = 0;
|
2016-03-16 19:00:36 +08:00
|
|
|
list_for_each_entry(req, &engine->request_list, list)
|
2015-04-01 17:36:56 +08:00
|
|
|
count++;
|
|
|
|
if (count == 0)
|
2012-09-02 03:51:22 +08:00
|
|
|
continue;
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s requests: %d\n", engine->name, count);
|
|
|
|
list_for_each_entry(req, &engine->request_list, list) {
|
2015-04-01 17:36:56 +08:00
|
|
|
struct task_struct *task;
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
task = NULL;
|
2015-05-21 20:21:25 +08:00
|
|
|
if (req->pid)
|
|
|
|
task = pid_task(req->pid, PIDTYPE_PID);
|
2015-04-01 17:36:56 +08:00
|
|
|
seq_printf(m, " %x @ %d: %s [%d]\n",
|
2015-05-21 20:21:25 +08:00
|
|
|
req->seqno,
|
|
|
|
(int) (jiffies - req->emitted_jiffies),
|
2015-04-01 17:36:56 +08:00
|
|
|
task ? task->comm : "<unknown>",
|
|
|
|
task ? task->pid : -1);
|
|
|
|
rcu_read_unlock();
|
2010-10-27 22:11:53 +08:00
|
|
|
}
|
2015-04-01 17:36:56 +08:00
|
|
|
|
|
|
|
any++;
|
2009-02-18 09:08:50 +08:00
|
|
|
}
|
2010-07-03 14:58:38 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2015-04-01 17:36:56 +08:00
|
|
|
if (any == 0)
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "No requests\n");
|
2010-10-27 22:11:53 +08:00
|
|
|
|
2009-02-18 09:08:50 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-10-27 22:27:33 +08:00
|
|
|
static void i915_ring_seqno_info(struct seq_file *m,
|
2016-03-16 19:00:37 +08:00
|
|
|
struct intel_engine_cs *engine)
|
2010-10-27 22:27:33 +08:00
|
|
|
{
|
2016-04-09 17:57:55 +08:00
|
|
|
seq_printf(m, "Current sequence (%s): %x\n",
|
|
|
|
engine->name, engine->get_seqno(engine));
|
|
|
|
seq_printf(m, "Current user interrupts (%s): %x\n",
|
|
|
|
engine->name, READ_ONCE(engine->user_interrupts));
|
2010-10-27 22:27:33 +08:00
|
|
|
}
|
|
|
|
|
2009-02-18 09:08:50 +08:00
|
|
|
static int i915_gem_seqno_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2009-02-18 09:08:50 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2016-03-24 19:20:38 +08:00
|
|
|
int ret;
|
2010-07-03 14:58:38 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2009-02-18 09:08:50 +08:00
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv)
|
2016-03-16 19:00:36 +08:00
|
|
|
i915_ring_seqno_info(m, engine);
|
2010-07-03 14:58:38 +08:00
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2010-07-03 14:58:38 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2009-02-18 09:08:50 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int i915_interrupt_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2009-02-18 09:08:50 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2011-02-08 04:26:52 +08:00
|
|
|
int ret, i, pipe;
|
2010-07-03 14:58:38 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2009-02-18 09:08:50 +08:00
|
|
|
|
2014-04-09 18:28:09 +08:00
|
|
|
if (IS_CHERRYVIEW(dev)) {
|
|
|
|
seq_printf(m, "Master Interrupt Control:\t%08x\n",
|
|
|
|
I915_READ(GEN8_MASTER_IRQ));
|
|
|
|
|
|
|
|
seq_printf(m, "Display IER:\t%08x\n",
|
|
|
|
I915_READ(VLV_IER));
|
|
|
|
seq_printf(m, "Display IIR:\t%08x\n",
|
|
|
|
I915_READ(VLV_IIR));
|
|
|
|
seq_printf(m, "Display IIR_RW:\t%08x\n",
|
|
|
|
I915_READ(VLV_IIR_RW));
|
|
|
|
seq_printf(m, "Display IMR:\t%08x\n",
|
|
|
|
I915_READ(VLV_IMR));
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2014-04-09 18:28:09 +08:00
|
|
|
seq_printf(m, "Pipe %c stat:\t%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(PIPESTAT(pipe)));
|
|
|
|
|
|
|
|
seq_printf(m, "Port hotplug:\t%08x\n",
|
|
|
|
I915_READ(PORT_HOTPLUG_EN));
|
|
|
|
seq_printf(m, "DPFLIPSTAT:\t%08x\n",
|
|
|
|
I915_READ(VLV_DPFLIPSTAT));
|
|
|
|
seq_printf(m, "DPINVGTT:\t%08x\n",
|
|
|
|
I915_READ(DPINVGTT));
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
|
|
|
|
i, I915_READ(GEN8_GT_IMR(i)));
|
|
|
|
seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
|
|
|
|
i, I915_READ(GEN8_GT_IIR(i)));
|
|
|
|
seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
|
|
|
|
i, I915_READ(GEN8_GT_IER(i)));
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(m, "PCU interrupt mask:\t%08x\n",
|
|
|
|
I915_READ(GEN8_PCU_IMR));
|
|
|
|
seq_printf(m, "PCU interrupt identity:\t%08x\n",
|
|
|
|
I915_READ(GEN8_PCU_IIR));
|
|
|
|
seq_printf(m, "PCU interrupt enable:\t%08x\n",
|
|
|
|
I915_READ(GEN8_PCU_IER));
|
|
|
|
} else if (INTEL_INFO(dev)->gen >= 8) {
|
2013-11-03 12:07:10 +08:00
|
|
|
seq_printf(m, "Master Interrupt Control:\t%08x\n",
|
|
|
|
I915_READ(GEN8_MASTER_IRQ));
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
|
|
|
|
i, I915_READ(GEN8_GT_IMR(i)));
|
|
|
|
seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
|
|
|
|
i, I915_READ(GEN8_GT_IIR(i)));
|
|
|
|
seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
|
|
|
|
i, I915_READ(GEN8_GT_IER(i)));
|
|
|
|
}
|
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2016-02-13 00:55:17 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
|
|
|
|
|
power_domain = POWER_DOMAIN_PIPE(pipe);
|
|
|
|
if (!intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
power_domain)) {
|
2014-08-09 04:45:32 +08:00
|
|
|
seq_printf(m, "Pipe %c power disabled\n",
|
|
|
|
pipe_name(pipe));
|
|
|
|
continue;
|
|
|
|
}
|
2013-11-03 12:07:10 +08:00
|
|
|
seq_printf(m, "Pipe %c IMR:\t%08x\n",
|
2014-03-04 01:31:46 +08:00
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(GEN8_DE_PIPE_IMR(pipe)));
|
2013-11-03 12:07:10 +08:00
|
|
|
seq_printf(m, "Pipe %c IIR:\t%08x\n",
|
2014-03-04 01:31:46 +08:00
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(GEN8_DE_PIPE_IIR(pipe)));
|
2013-11-03 12:07:10 +08:00
|
|
|
seq_printf(m, "Pipe %c IER:\t%08x\n",
|
2014-03-04 01:31:46 +08:00
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(GEN8_DE_PIPE_IER(pipe)));
|
2016-02-13 00:55:17 +08:00
|
|
|
|
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
2013-11-03 12:07:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
|
|
|
|
I915_READ(GEN8_DE_PORT_IMR));
|
|
|
|
seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
|
|
|
|
I915_READ(GEN8_DE_PORT_IIR));
|
|
|
|
seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
|
|
|
|
I915_READ(GEN8_DE_PORT_IER));
|
|
|
|
|
|
|
|
seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
|
|
|
|
I915_READ(GEN8_DE_MISC_IMR));
|
|
|
|
seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
|
|
|
|
I915_READ(GEN8_DE_MISC_IIR));
|
|
|
|
seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
|
|
|
|
I915_READ(GEN8_DE_MISC_IER));
|
|
|
|
|
|
|
|
seq_printf(m, "PCU interrupt mask:\t%08x\n",
|
|
|
|
I915_READ(GEN8_PCU_IMR));
|
|
|
|
seq_printf(m, "PCU interrupt identity:\t%08x\n",
|
|
|
|
I915_READ(GEN8_PCU_IIR));
|
|
|
|
seq_printf(m, "PCU interrupt enable:\t%08x\n",
|
|
|
|
I915_READ(GEN8_PCU_IER));
|
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
2012-03-29 04:39:38 +08:00
|
|
|
seq_printf(m, "Display IER:\t%08x\n",
|
|
|
|
I915_READ(VLV_IER));
|
|
|
|
seq_printf(m, "Display IIR:\t%08x\n",
|
|
|
|
I915_READ(VLV_IIR));
|
|
|
|
seq_printf(m, "Display IIR_RW:\t%08x\n",
|
|
|
|
I915_READ(VLV_IIR_RW));
|
|
|
|
seq_printf(m, "Display IMR:\t%08x\n",
|
|
|
|
I915_READ(VLV_IMR));
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2012-03-29 04:39:38 +08:00
|
|
|
seq_printf(m, "Pipe %c stat:\t%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(PIPESTAT(pipe)));
|
|
|
|
|
|
|
|
seq_printf(m, "Master IER:\t%08x\n",
|
|
|
|
I915_READ(VLV_MASTER_IER));
|
|
|
|
|
|
|
|
seq_printf(m, "Render IER:\t%08x\n",
|
|
|
|
I915_READ(GTIER));
|
|
|
|
seq_printf(m, "Render IIR:\t%08x\n",
|
|
|
|
I915_READ(GTIIR));
|
|
|
|
seq_printf(m, "Render IMR:\t%08x\n",
|
|
|
|
I915_READ(GTIMR));
|
|
|
|
|
|
|
|
seq_printf(m, "PM IER:\t\t%08x\n",
|
|
|
|
I915_READ(GEN6_PMIER));
|
|
|
|
seq_printf(m, "PM IIR:\t\t%08x\n",
|
|
|
|
I915_READ(GEN6_PMIIR));
|
|
|
|
seq_printf(m, "PM IMR:\t\t%08x\n",
|
|
|
|
I915_READ(GEN6_PMIMR));
|
|
|
|
|
|
|
|
seq_printf(m, "Port hotplug:\t%08x\n",
|
|
|
|
I915_READ(PORT_HOTPLUG_EN));
|
|
|
|
seq_printf(m, "DPFLIPSTAT:\t%08x\n",
|
|
|
|
I915_READ(VLV_DPFLIPSTAT));
|
|
|
|
seq_printf(m, "DPINVGTT:\t%08x\n",
|
|
|
|
I915_READ(DPINVGTT));
|
|
|
|
|
|
|
|
} else if (!HAS_PCH_SPLIT(dev)) {
|
2009-08-10 21:37:24 +08:00
|
|
|
seq_printf(m, "Interrupt enable: %08x\n",
|
|
|
|
I915_READ(IER));
|
|
|
|
seq_printf(m, "Interrupt identity: %08x\n",
|
|
|
|
I915_READ(IIR));
|
|
|
|
seq_printf(m, "Interrupt mask: %08x\n",
|
|
|
|
I915_READ(IMR));
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe)
|
2011-02-08 04:26:52 +08:00
|
|
|
seq_printf(m, "Pipe %c stat: %08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(PIPESTAT(pipe)));
|
2009-08-10 21:37:24 +08:00
|
|
|
} else {
|
|
|
|
seq_printf(m, "North Display Interrupt enable: %08x\n",
|
|
|
|
I915_READ(DEIER));
|
|
|
|
seq_printf(m, "North Display Interrupt identity: %08x\n",
|
|
|
|
I915_READ(DEIIR));
|
|
|
|
seq_printf(m, "North Display Interrupt mask: %08x\n",
|
|
|
|
I915_READ(DEIMR));
|
|
|
|
seq_printf(m, "South Display Interrupt enable: %08x\n",
|
|
|
|
I915_READ(SDEIER));
|
|
|
|
seq_printf(m, "South Display Interrupt identity: %08x\n",
|
|
|
|
I915_READ(SDEIIR));
|
|
|
|
seq_printf(m, "South Display Interrupt mask: %08x\n",
|
|
|
|
I915_READ(SDEIMR));
|
|
|
|
seq_printf(m, "Graphics Interrupt enable: %08x\n",
|
|
|
|
I915_READ(GTIER));
|
|
|
|
seq_printf(m, "Graphics Interrupt identity: %08x\n",
|
|
|
|
I915_READ(GTIIR));
|
|
|
|
seq_printf(m, "Graphics Interrupt mask: %08x\n",
|
|
|
|
I915_READ(GTIMR));
|
|
|
|
}
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2013-11-03 12:07:10 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2012-09-02 03:51:22 +08:00
|
|
|
seq_printf(m,
|
|
|
|
"Graphics Interrupt mask (%s): %08x\n",
|
2016-03-16 19:00:36 +08:00
|
|
|
engine->name, I915_READ_IMR(engine));
|
2011-01-05 06:22:17 +08:00
|
|
|
}
|
2016-03-16 19:00:36 +08:00
|
|
|
i915_ring_seqno_info(m, engine);
|
2011-01-05 06:22:17 +08:00
|
|
|
}
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2010-07-03 14:58:38 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2009-02-18 09:08:50 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-02-11 22:26:38 +08:00
|
|
|
static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2009-02-11 22:26:38 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-07-03 14:58:38 +08:00
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2009-02-11 22:26:38 +08:00
|
|
|
|
|
|
|
seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
|
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++) {
|
2010-11-09 03:18:58 +08:00
|
|
|
struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
|
2009-02-11 22:26:38 +08:00
|
|
|
|
drm/i915: Track unbound pages
When dealing with a working set larger than the GATT, or even the
mappable aperture when touching through the GTT, we end up with evicting
objects only to rebind them at a new offset again later. Moving an
object into and out of the GTT requires clflushing the pages, thus
causing a double-clflush penalty for rebinding.
To avoid having to clflush on rebinding, we can track the pages as they
are evicted from the GTT and only relinquish those pages on memory
pressure.
As usual, if it were not for the handling of out-of-memory condition and
having to manually shrink our own bo caches, it would be a net reduction
of code. Alas.
Note: The patch also contains a few changes to the last-hope
evict_everything logic in i916_gem_execbuffer.c - we no longer try to
only evict the purgeable stuff in a first try (since that's superflous
and only helps in OOM corner-cases, not fragmented-gtt trashing
situations).
Also, the extraction of the get_pages retry loop from bind_to_gtt (and
other callsites) to get_pages should imo have been a separate patch.
v2: Ditch the newly added put_pages (for unbound objects only) in
i915_gem_reset. A quick irc discussion hasn't revealed any important
reason for this, so if we need this, I'd like to have a git blame'able
explanation for it.
v3: Undo the s/drm_malloc_ab/kmalloc/ in get_pages that Chris noticed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Split out code movements and rant a bit in the commit message
with a few Notes. Done v2]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-20 17:40:46 +08:00
|
|
|
seq_printf(m, "Fence %d, pin count = %d, object = ",
|
|
|
|
i, dev_priv->fence_regs[i].pin_count);
|
2010-10-27 22:11:53 +08:00
|
|
|
if (obj == NULL)
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "unused");
|
2010-10-27 22:11:53 +08:00
|
|
|
else
|
2010-11-09 03:18:58 +08:00
|
|
|
describe_obj(m, obj);
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_putc(m, '\n');
|
2009-02-11 22:26:38 +08:00
|
|
|
}
|
|
|
|
|
2010-11-09 03:18:58 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2009-02-11 22:26:38 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-02-18 09:08:50 +08:00
|
|
|
static int i915_hws_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2009-02-18 09:08:50 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2012-11-30 05:18:51 +08:00
|
|
|
const u32 *hws;
|
2010-10-30 04:00:54 +08:00
|
|
|
int i;
|
|
|
|
|
2016-03-16 19:00:38 +08:00
|
|
|
engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
|
2016-03-16 19:00:36 +08:00
|
|
|
hws = engine->status_page.page_addr;
|
2009-02-18 09:08:50 +08:00
|
|
|
if (hws == NULL)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
|
|
|
|
seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
|
|
i * 4,
|
|
|
|
hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-04-27 21:17:40 +08:00
|
|
|
static ssize_t
|
|
|
|
i915_error_state_write(struct file *filp,
|
|
|
|
const char __user *ubuf,
|
|
|
|
size_t cnt,
|
|
|
|
loff_t *ppos)
|
|
|
|
{
|
2013-05-23 18:55:35 +08:00
|
|
|
struct i915_error_state_file_priv *error_priv = filp->private_data;
|
2012-04-27 21:17:40 +08:00
|
|
|
struct drm_device *dev = error_priv->dev;
|
2012-08-09 21:07:02 +08:00
|
|
|
int ret;
|
2012-04-27 21:17:40 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Resetting error state\n");
|
|
|
|
|
2012-08-09 21:07:02 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-04-27 21:17:40 +08:00
|
|
|
i915_destroy_error_state(dev);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return cnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_error_state_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
struct i915_error_state_file_priv *error_priv;
|
|
|
|
|
|
|
|
error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
|
|
|
|
if (!error_priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
error_priv->dev = dev;
|
|
|
|
|
2013-06-06 20:18:40 +08:00
|
|
|
i915_error_state_get(dev, error_priv);
|
2012-04-27 21:17:40 +08:00
|
|
|
|
2013-05-23 18:55:35 +08:00
|
|
|
file->private_data = error_priv;
|
|
|
|
|
|
|
|
return 0;
|
2012-04-27 21:17:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_error_state_release(struct inode *inode, struct file *file)
|
|
|
|
{
|
2013-05-23 18:55:35 +08:00
|
|
|
struct i915_error_state_file_priv *error_priv = file->private_data;
|
2012-04-27 21:17:40 +08:00
|
|
|
|
2013-06-06 20:18:40 +08:00
|
|
|
i915_error_state_put(error_priv);
|
2012-04-27 21:17:40 +08:00
|
|
|
kfree(error_priv);
|
|
|
|
|
2013-05-23 18:55:35 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-06 20:18:41 +08:00
|
|
|
static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
|
|
|
|
size_t count, loff_t *pos)
|
|
|
|
{
|
|
|
|
struct i915_error_state_file_priv *error_priv = file->private_data;
|
|
|
|
struct drm_i915_error_state_buf error_str;
|
|
|
|
loff_t tmp_pos = 0;
|
|
|
|
ssize_t ret_count = 0;
|
|
|
|
int ret;
|
|
|
|
|
2014-08-22 21:41:39 +08:00
|
|
|
ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
|
2013-06-06 20:18:41 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-05-23 18:55:35 +08:00
|
|
|
|
2013-06-06 20:18:39 +08:00
|
|
|
ret = i915_error_state_to_str(&error_str, error_priv);
|
2013-05-23 18:55:35 +08:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
|
|
|
|
error_str.buf,
|
|
|
|
error_str.bytes);
|
|
|
|
|
|
|
|
if (ret_count < 0)
|
|
|
|
ret = ret_count;
|
|
|
|
else
|
|
|
|
*pos = error_str.start + ret_count;
|
|
|
|
out:
|
2013-06-06 20:18:41 +08:00
|
|
|
i915_error_state_buf_release(&error_str);
|
2013-05-23 18:55:35 +08:00
|
|
|
return ret ?: ret_count;
|
2012-04-27 21:17:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_error_state_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_error_state_open,
|
2013-05-23 18:55:35 +08:00
|
|
|
.read = i915_error_state_read,
|
2012-04-27 21:17:40 +08:00
|
|
|
.write = i915_error_state_write,
|
|
|
|
.llseek = default_llseek,
|
|
|
|
.release = i915_error_state_release,
|
|
|
|
};
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_next_seqno_get(void *data, u64 *val)
|
2012-12-04 21:12:00 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-12-04 21:12:00 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
*val = dev_priv->next_seqno;
|
2012-12-04 21:12:00 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2012-12-04 21:12:00 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_next_seqno_set(void *data, u64 val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
2012-12-04 21:12:00 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-12-19 17:13:09 +08:00
|
|
|
ret = i915_gem_set_seqno(dev, val);
|
2012-12-04 21:12:00 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return ret;
|
2012-12-04 21:12:00 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
|
|
|
|
i915_next_seqno_get, i915_next_seqno_set,
|
2013-04-12 17:10:05 +08:00
|
|
|
"0x%llx\n");
|
2012-12-04 21:12:00 +08:00
|
|
|
|
2014-03-31 14:00:02 +08:00
|
|
|
static int i915_frequency_info(struct seq_file *m, void *unused)
|
2010-01-30 03:27:07 +08:00
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-01-30 03:27:07 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-11-28 04:21:54 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2013-09-17 05:56:43 +08:00
|
|
|
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2010-12-18 06:19:02 +08:00
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
u16 rgvswctl = I915_READ16(MEMSWCTL);
|
|
|
|
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
|
|
|
|
|
|
|
|
seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
|
|
|
|
seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
|
|
|
|
seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
|
|
|
|
MEMSTAT_VID_SHIFT);
|
|
|
|
seq_printf(m, "Current P-state: %d\n",
|
|
|
|
(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
|
2015-12-10 04:29:35 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
|
|
|
|
u32 freq_sts;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
|
|
|
|
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
|
|
|
|
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
|
|
|
|
|
|
|
|
seq_printf(m, "actual GPU freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
|
|
|
|
|
|
|
|
seq_printf(m, "current GPU freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
|
|
|
|
|
|
|
|
seq_printf(m, "max GPU freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
|
|
|
|
|
|
|
|
seq_printf(m, "min GPU freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
|
|
|
|
|
|
|
|
seq_printf(m, "idle GPU freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
|
|
|
|
|
|
|
|
seq_printf(m,
|
|
|
|
"efficient (RPe) frequency: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
} else if (INTEL_INFO(dev)->gen >= 6) {
|
2015-06-26 05:54:07 +08:00
|
|
|
u32 rp_state_limits;
|
|
|
|
u32 gt_perf_status;
|
|
|
|
u32 rp_state_cap;
|
2014-03-27 17:06:14 +08:00
|
|
|
u32 rpmodectl, rpinclimit, rpdeclimit;
|
2013-08-27 06:51:01 +08:00
|
|
|
u32 rpstat, cagf, reqf;
|
2011-01-19 07:49:25 +08:00
|
|
|
u32 rpupei, rpcurup, rpprevup;
|
|
|
|
u32 rpdownei, rpcurdown, rpprevdown;
|
2014-08-02 05:14:48 +08:00
|
|
|
u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
|
2010-12-18 06:19:02 +08:00
|
|
|
int max_freq;
|
|
|
|
|
2015-06-26 05:54:07 +08:00
|
|
|
rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
|
|
|
|
if (IS_BROXTON(dev)) {
|
|
|
|
rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
|
|
|
|
gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
|
|
|
|
} else {
|
|
|
|
rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
|
|
|
|
gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
|
|
|
|
}
|
|
|
|
|
2010-12-18 06:19:02 +08:00
|
|
|
/* RPSTAT1 is in the GT power well */
|
2011-04-26 03:11:50 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
2013-11-28 04:21:54 +08:00
|
|
|
goto out;
|
2011-04-26 03:11:50 +08:00
|
|
|
|
2015-01-16 17:34:40 +08:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2013-08-27 06:51:01 +08:00
|
|
|
reqf = I915_READ(GEN6_RPNSWREQ);
|
2015-03-06 13:37:21 +08:00
|
|
|
if (IS_GEN9(dev))
|
|
|
|
reqf >>= 23;
|
|
|
|
else {
|
|
|
|
reqf &= ~GEN6_TURBO_DISABLE;
|
|
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
|
|
reqf >>= 24;
|
|
|
|
else
|
|
|
|
reqf >>= 25;
|
|
|
|
}
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
reqf = intel_gpu_freq(dev_priv, reqf);
|
2013-08-27 06:51:01 +08:00
|
|
|
|
2014-03-27 17:06:14 +08:00
|
|
|
rpmodectl = I915_READ(GEN6_RP_CONTROL);
|
|
|
|
rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
|
|
|
|
rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
|
|
|
|
|
2011-01-19 07:49:25 +08:00
|
|
|
rpstat = I915_READ(GEN6_RPSTAT1);
|
2016-04-23 02:35:46 +08:00
|
|
|
rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
|
|
|
|
rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
|
|
|
|
rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
|
|
|
|
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
|
|
|
|
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
|
|
|
|
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
|
2015-03-06 13:37:21 +08:00
|
|
|
if (IS_GEN9(dev))
|
|
|
|
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
|
|
|
|
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
2013-01-30 04:00:15 +08:00
|
|
|
cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
|
|
|
|
else
|
|
|
|
cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
cagf = intel_gpu_freq(dev_priv, cagf);
|
2011-01-19 07:49:25 +08:00
|
|
|
|
2015-01-16 17:34:40 +08:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2011-04-26 03:11:50 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2014-08-02 05:14:48 +08:00
|
|
|
if (IS_GEN6(dev) || IS_GEN7(dev)) {
|
|
|
|
pm_ier = I915_READ(GEN6_PMIER);
|
|
|
|
pm_imr = I915_READ(GEN6_PMIMR);
|
|
|
|
pm_isr = I915_READ(GEN6_PMISR);
|
|
|
|
pm_iir = I915_READ(GEN6_PMIIR);
|
|
|
|
pm_mask = I915_READ(GEN6_PMINTRMSK);
|
|
|
|
} else {
|
|
|
|
pm_ier = I915_READ(GEN8_GT_IER(2));
|
|
|
|
pm_imr = I915_READ(GEN8_GT_IMR(2));
|
|
|
|
pm_isr = I915_READ(GEN8_GT_ISR(2));
|
|
|
|
pm_iir = I915_READ(GEN8_GT_IIR(2));
|
|
|
|
pm_mask = I915_READ(GEN6_PMINTRMSK);
|
|
|
|
}
|
2014-03-27 17:06:14 +08:00
|
|
|
seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
|
2014-08-02 05:14:48 +08:00
|
|
|
pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
|
2010-12-18 06:19:02 +08:00
|
|
|
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
|
|
|
|
seq_printf(m, "Render p-state ratio: %d\n",
|
2015-03-06 13:37:21 +08:00
|
|
|
(gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
|
2010-12-18 06:19:02 +08:00
|
|
|
seq_printf(m, "Render p-state VID: %d\n",
|
|
|
|
gt_perf_status & 0xff);
|
|
|
|
seq_printf(m, "Render p-state limit: %d\n",
|
|
|
|
rp_state_limits & 0xff);
|
2014-03-27 17:06:14 +08:00
|
|
|
seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
|
|
|
|
seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
|
|
|
|
seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
|
|
|
|
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
|
2013-08-27 06:51:01 +08:00
|
|
|
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
|
2013-01-30 04:00:15 +08:00
|
|
|
seq_printf(m, "CAGF: %dMHz\n", cagf);
|
2016-04-23 02:35:46 +08:00
|
|
|
seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
|
|
|
|
rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
|
|
|
|
seq_printf(m, "RP CUR UP: %d (%dus)\n",
|
|
|
|
rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
|
|
|
|
seq_printf(m, "RP PREV UP: %d (%dus)\n",
|
|
|
|
rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
|
2015-04-27 20:41:19 +08:00
|
|
|
seq_printf(m, "Up threshold: %d%%\n",
|
|
|
|
dev_priv->rps.up_threshold);
|
|
|
|
|
2016-04-23 02:35:46 +08:00
|
|
|
seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
|
|
|
|
rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
|
|
|
|
seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
|
|
|
|
rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
|
|
|
|
seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
|
|
|
|
rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
|
2015-04-27 20:41:19 +08:00
|
|
|
seq_printf(m, "Down threshold: %d%%\n",
|
|
|
|
dev_priv->rps.down_threshold);
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2015-06-26 05:54:07 +08:00
|
|
|
max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
|
|
|
|
rp_state_cap >> 16) & 0xff;
|
2015-10-28 19:16:45 +08:00
|
|
|
max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
|
|
|
|
GEN9_FREQ_SCALER : 1);
|
2010-12-18 06:19:02 +08:00
|
|
|
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
intel_gpu_freq(dev_priv, max_freq));
|
2010-12-18 06:19:02 +08:00
|
|
|
|
|
|
|
max_freq = (rp_state_cap & 0xff00) >> 8;
|
2015-10-28 19:16:45 +08:00
|
|
|
max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
|
|
|
|
GEN9_FREQ_SCALER : 1);
|
2010-12-18 06:19:02 +08:00
|
|
|
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
intel_gpu_freq(dev_priv, max_freq));
|
2010-12-18 06:19:02 +08:00
|
|
|
|
2015-06-26 05:54:07 +08:00
|
|
|
max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
|
|
|
|
rp_state_cap >> 0) & 0xff;
|
2015-10-28 19:16:45 +08:00
|
|
|
max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
|
|
|
|
GEN9_FREQ_SCALER : 1);
|
2010-12-18 06:19:02 +08:00
|
|
|
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
intel_gpu_freq(dev_priv, max_freq));
|
2013-04-06 05:29:22 +08:00
|
|
|
seq_printf(m, "Max overclocked frequency: %dMHz\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
|
2015-03-18 17:48:21 +08:00
|
|
|
|
2015-04-27 20:41:19 +08:00
|
|
|
seq_printf(m, "Current freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
|
|
|
|
seq_printf(m, "Actual freq: %d MHz\n", cagf);
|
2015-03-18 17:48:21 +08:00
|
|
|
seq_printf(m, "Idle freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
|
2015-04-27 20:41:19 +08:00
|
|
|
seq_printf(m, "Min freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
|
|
|
|
seq_printf(m, "Max freq: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
|
|
|
|
seq_printf(m,
|
|
|
|
"efficient (RPe) frequency: %d MHz\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
|
2010-12-18 06:19:02 +08:00
|
|
|
} else {
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "no P-state info available\n");
|
2010-12-18 06:19:02 +08:00
|
|
|
}
|
2010-01-30 03:27:07 +08:00
|
|
|
|
2015-09-25 19:00:32 +08:00
|
|
|
seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
|
|
|
|
seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
|
|
|
|
seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
out:
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
return ret;
|
2010-01-30 03:27:07 +08:00
|
|
|
}
|
|
|
|
|
2015-01-27 00:03:04 +08:00
|
|
|
static int i915_hangcheck_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
2015-02-06 00:41:48 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2016-03-16 19:00:39 +08:00
|
|
|
u64 acthd[I915_NUM_ENGINES];
|
|
|
|
u32 seqno[I915_NUM_ENGINES];
|
2015-12-01 23:56:12 +08:00
|
|
|
u32 instdone[I915_NUM_INSTDONE_REG];
|
2016-03-24 02:19:53 +08:00
|
|
|
enum intel_engine_id id;
|
|
|
|
int j;
|
2015-01-27 00:03:04 +08:00
|
|
|
|
|
|
|
if (!i915.enable_hangcheck) {
|
|
|
|
seq_printf(m, "Hangcheck disabled\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-02-06 00:41:48 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2016-03-24 02:19:53 +08:00
|
|
|
for_each_engine_id(engine, dev_priv, id) {
|
|
|
|
acthd[id] = intel_ring_get_active_head(engine);
|
2016-04-09 17:57:54 +08:00
|
|
|
seqno[id] = engine->get_seqno(engine);
|
2015-02-06 00:41:48 +08:00
|
|
|
}
|
|
|
|
|
2016-05-06 22:40:21 +08:00
|
|
|
i915_get_extra_instdone(dev_priv, instdone);
|
2015-12-01 23:56:12 +08:00
|
|
|
|
2015-02-06 00:41:48 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2015-01-27 00:03:04 +08:00
|
|
|
if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
|
|
|
|
seq_printf(m, "Hangcheck active, fires in %dms\n",
|
|
|
|
jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
|
|
|
|
jiffies));
|
|
|
|
} else
|
|
|
|
seq_printf(m, "Hangcheck inactive\n");
|
|
|
|
|
2016-03-24 02:19:53 +08:00
|
|
|
for_each_engine_id(engine, dev_priv, id) {
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s:\n", engine->name);
|
2016-04-07 14:29:10 +08:00
|
|
|
seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
|
|
|
|
engine->hangcheck.seqno,
|
|
|
|
seqno[id],
|
|
|
|
engine->last_submitted_seqno);
|
2016-04-09 17:57:55 +08:00
|
|
|
seq_printf(m, "\tuser interrupts = %x [current %x]\n",
|
|
|
|
engine->hangcheck.user_interrupts,
|
|
|
|
READ_ONCE(engine->user_interrupts));
|
2015-01-27 00:03:04 +08:00
|
|
|
seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
|
2016-03-16 19:00:36 +08:00
|
|
|
(long long)engine->hangcheck.acthd,
|
2016-03-24 02:19:53 +08:00
|
|
|
(long long)acthd[id]);
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
|
|
|
|
seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
|
2015-12-01 23:56:12 +08:00
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
if (engine->id == RCS) {
|
2015-12-01 23:56:12 +08:00
|
|
|
seq_puts(m, "\tinstdone read =");
|
|
|
|
|
|
|
|
for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
|
|
|
|
seq_printf(m, " 0x%08x", instdone[j]);
|
|
|
|
|
|
|
|
seq_puts(m, "\n\tinstdone accu =");
|
|
|
|
|
|
|
|
for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
|
|
|
|
seq_printf(m, " 0x%08x",
|
2016-03-16 19:00:36 +08:00
|
|
|
engine->hangcheck.instdone[j]);
|
2015-12-01 23:56:12 +08:00
|
|
|
|
|
|
|
seq_puts(m, "\n");
|
|
|
|
}
|
2015-01-27 00:03:04 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-12-13 11:34:16 +08:00
|
|
|
static int ironlake_drpc_info(struct seq_file *m)
|
2010-01-30 03:27:07 +08:00
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-01-30 03:27:07 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-10-06 02:44:54 +08:00
|
|
|
u32 rgvmodectl, rstdbyctl;
|
|
|
|
u16 crstandvid;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2011-10-06 02:44:54 +08:00
|
|
|
|
|
|
|
rgvmodectl = I915_READ(MEMMODECTL);
|
|
|
|
rstdbyctl = I915_READ(RSTDBYCTL);
|
|
|
|
crstandvid = I915_READ16(CRSTANDVID);
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2011-10-06 02:44:54 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-01-30 03:27:07 +08:00
|
|
|
|
2015-09-03 16:16:09 +08:00
|
|
|
seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
|
2010-01-30 03:27:07 +08:00
|
|
|
seq_printf(m, "Boost freq: %d\n",
|
|
|
|
(rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
|
|
|
|
MEMMODE_BOOST_FREQ_SHIFT);
|
|
|
|
seq_printf(m, "HW control enabled: %s\n",
|
2015-09-03 16:16:09 +08:00
|
|
|
yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
|
2010-01-30 03:27:07 +08:00
|
|
|
seq_printf(m, "SW control enabled: %s\n",
|
2015-09-03 16:16:09 +08:00
|
|
|
yesno(rgvmodectl & MEMMODE_SWMODE_EN));
|
2010-01-30 03:27:07 +08:00
|
|
|
seq_printf(m, "Gated voltage change: %s\n",
|
2015-09-03 16:16:09 +08:00
|
|
|
yesno(rgvmodectl & MEMMODE_RCLK_GATE));
|
2010-01-30 03:27:07 +08:00
|
|
|
seq_printf(m, "Starting frequency: P%d\n",
|
|
|
|
(rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
|
2010-05-21 05:28:11 +08:00
|
|
|
seq_printf(m, "Max P-state: P%d\n",
|
2010-01-30 03:27:07 +08:00
|
|
|
(rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
|
2010-05-21 05:28:11 +08:00
|
|
|
seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
|
|
|
|
seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
|
|
|
|
seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
|
|
|
|
seq_printf(m, "Render standby enabled: %s\n",
|
2015-09-03 16:16:09 +08:00
|
|
|
yesno(!(rstdbyctl & RCX_SW_EXIT)));
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "Current RS state: ");
|
2011-01-06 04:01:24 +08:00
|
|
|
switch (rstdbyctl & RSX_STATUS_MASK) {
|
|
|
|
case RSX_STATUS_ON:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "on\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
case RSX_STATUS_RC1:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC1\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
case RSX_STATUS_RC1E:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC1E\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
case RSX_STATUS_RS1:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RS1\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
case RSX_STATUS_RS2:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RS2 (RC6)\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
case RSX_STATUS_RS3:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC3 (RC6+)\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
default:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "unknown\n");
|
2011-01-06 04:01:24 +08:00
|
|
|
break;
|
|
|
|
}
|
2010-01-30 03:27:07 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-16 17:34:42 +08:00
|
|
|
static int i915_forcewake_domains(struct seq_file *m, void *data)
|
2014-01-10 17:48:26 +08:00
|
|
|
{
|
2015-01-16 17:34:37 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_uncore_forcewake_domain *fw_domain;
|
|
|
|
|
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
2016-04-08 00:04:33 +08:00
|
|
|
for_each_fw_domain(fw_domain, dev_priv) {
|
2015-01-16 17:34:37 +08:00
|
|
|
seq_printf(m, "%s.wake_count = %u\n",
|
2016-04-08 00:04:33 +08:00
|
|
|
intel_uncore_forcewake_domain_to_str(fw_domain->id),
|
2015-01-16 17:34:37 +08:00
|
|
|
fw_domain->wake_count);
|
|
|
|
}
|
|
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
2014-01-10 17:48:26 +08:00
|
|
|
|
2015-01-16 17:34:37 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vlv_drpc_info(struct seq_file *m)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2014-01-10 17:48:26 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-11-20 02:07:42 +08:00
|
|
|
u32 rpmodectl1, rcctl1, pw_status;
|
2014-01-10 17:48:26 +08:00
|
|
|
|
2014-04-15 01:24:27 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2014-11-20 02:07:42 +08:00
|
|
|
pw_status = I915_READ(VLV_GTLC_PW_STATUS);
|
2014-01-10 17:48:26 +08:00
|
|
|
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
|
|
|
|
rcctl1 = I915_READ(GEN6_RC_CONTROL);
|
|
|
|
|
2014-04-15 01:24:27 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2014-01-10 17:48:26 +08:00
|
|
|
seq_printf(m, "Video Turbo Mode: %s\n",
|
|
|
|
yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
|
|
|
|
seq_printf(m, "Turbo enabled: %s\n",
|
|
|
|
yesno(rpmodectl1 & GEN6_RP_ENABLE));
|
|
|
|
seq_printf(m, "HW control enabled: %s\n",
|
|
|
|
yesno(rpmodectl1 & GEN6_RP_ENABLE));
|
|
|
|
seq_printf(m, "SW control enabled: %s\n",
|
|
|
|
yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
|
|
|
|
GEN6_RP_MEDIA_SW_MODE));
|
|
|
|
seq_printf(m, "RC6 Enabled: %s\n",
|
|
|
|
yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
|
|
|
|
GEN6_RC_CTL_EI_MODE(1))));
|
|
|
|
seq_printf(m, "Render Power Well: %s\n",
|
2014-11-20 02:07:42 +08:00
|
|
|
(pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
|
2014-01-10 17:48:26 +08:00
|
|
|
seq_printf(m, "Media Power Well: %s\n",
|
2014-11-20 02:07:42 +08:00
|
|
|
(pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
|
2014-01-10 17:48:26 +08:00
|
|
|
|
2014-04-15 01:24:24 +08:00
|
|
|
seq_printf(m, "Render RC6 residency since boot: %u\n",
|
|
|
|
I915_READ(VLV_GT_RENDER_RC6));
|
|
|
|
seq_printf(m, "Media RC6 residency since boot: %u\n",
|
|
|
|
I915_READ(VLV_GT_MEDIA_RC6));
|
|
|
|
|
2015-01-16 17:34:42 +08:00
|
|
|
return i915_forcewake_domains(m, NULL);
|
2014-01-10 17:48:26 +08:00
|
|
|
}
|
|
|
|
|
2011-12-13 11:34:16 +08:00
|
|
|
static int gen6_drpc_info(struct seq_file *m)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2011-12-13 11:34:16 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-09-27 01:34:02 +08:00
|
|
|
u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
|
2012-01-25 20:52:43 +08:00
|
|
|
unsigned forcewake_count;
|
2013-06-25 05:59:49 +08:00
|
|
|
int count = 0, ret;
|
2011-12-13 11:34:16 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2011-12-13 11:34:16 +08:00
|
|
|
|
2013-07-20 03:36:52 +08:00
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
2015-01-16 17:34:37 +08:00
|
|
|
forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
|
2013-07-20 03:36:52 +08:00
|
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
2012-01-25 20:52:43 +08:00
|
|
|
|
|
|
|
if (forcewake_count) {
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC information inaccurate because somebody "
|
|
|
|
"holds a forcewake reference \n");
|
2011-12-13 11:34:16 +08:00
|
|
|
} else {
|
|
|
|
/* NB: we cannot use forcewake, else we read the wrong values */
|
|
|
|
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
|
|
|
|
udelay(10);
|
|
|
|
seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
|
|
|
|
}
|
|
|
|
|
2015-10-22 20:34:56 +08:00
|
|
|
gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
|
2013-07-20 03:36:56 +08:00
|
|
|
trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
|
2011-12-13 11:34:16 +08:00
|
|
|
|
|
|
|
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
|
|
|
|
rcctl1 = I915_READ(GEN6_RC_CONTROL);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2012-11-06 22:36:36 +08:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2011-12-13 11:34:16 +08:00
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2011-12-13 11:34:16 +08:00
|
|
|
seq_printf(m, "Video Turbo Mode: %s\n",
|
|
|
|
yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
|
|
|
|
seq_printf(m, "HW control enabled: %s\n",
|
|
|
|
yesno(rpmodectl1 & GEN6_RP_ENABLE));
|
|
|
|
seq_printf(m, "SW control enabled: %s\n",
|
|
|
|
yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
|
|
|
|
GEN6_RP_MEDIA_SW_MODE));
|
2012-01-24 08:14:05 +08:00
|
|
|
seq_printf(m, "RC1e Enabled: %s\n",
|
2011-12-13 11:34:16 +08:00
|
|
|
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
|
|
|
|
seq_printf(m, "RC6 Enabled: %s\n",
|
|
|
|
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
|
|
|
|
seq_printf(m, "Deep RC6 Enabled: %s\n",
|
|
|
|
yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
|
|
|
|
seq_printf(m, "Deepest RC6 Enabled: %s\n",
|
|
|
|
yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "Current RC state: ");
|
2011-12-13 11:34:16 +08:00
|
|
|
switch (gt_core_status & GEN6_RCn_MASK) {
|
|
|
|
case GEN6_RC0:
|
|
|
|
if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "Core Power Down\n");
|
2011-12-13 11:34:16 +08:00
|
|
|
else
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "on\n");
|
2011-12-13 11:34:16 +08:00
|
|
|
break;
|
|
|
|
case GEN6_RC3:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC3\n");
|
2011-12-13 11:34:16 +08:00
|
|
|
break;
|
|
|
|
case GEN6_RC6:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC6\n");
|
2011-12-13 11:34:16 +08:00
|
|
|
break;
|
|
|
|
case GEN6_RC7:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "RC7\n");
|
2011-12-13 11:34:16 +08:00
|
|
|
break;
|
|
|
|
default:
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "Unknown\n");
|
2011-12-13 11:34:16 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(m, "Core Power Down: %s\n",
|
|
|
|
yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
|
2012-03-28 09:59:38 +08:00
|
|
|
|
|
|
|
/* Not exactly sure what this is */
|
|
|
|
seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
|
|
|
|
I915_READ(GEN6_GT_GFX_RC6_LOCKED));
|
|
|
|
seq_printf(m, "RC6 residency since boot: %u\n",
|
|
|
|
I915_READ(GEN6_GT_GFX_RC6));
|
|
|
|
seq_printf(m, "RC6+ residency since boot: %u\n",
|
|
|
|
I915_READ(GEN6_GT_GFX_RC6p));
|
|
|
|
seq_printf(m, "RC6++ residency since boot: %u\n",
|
|
|
|
I915_READ(GEN6_GT_GFX_RC6pp));
|
|
|
|
|
2012-09-27 01:34:02 +08:00
|
|
|
seq_printf(m, "RC6 voltage: %dmV\n",
|
|
|
|
GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
|
|
|
|
seq_printf(m, "RC6+ voltage: %dmV\n",
|
|
|
|
GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
|
|
|
|
seq_printf(m, "RC6++ voltage: %dmV\n",
|
|
|
|
GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
|
2011-12-13 11:34:16 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_drpc_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2011-12-13 11:34:16 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
|
2015-12-10 04:29:35 +08:00
|
|
|
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
2014-01-10 17:48:26 +08:00
|
|
|
return vlv_drpc_info(m);
|
2014-08-27 01:42:51 +08:00
|
|
|
else if (INTEL_INFO(dev)->gen >= 6)
|
2011-12-13 11:34:16 +08:00
|
|
|
return gen6_drpc_info(m);
|
|
|
|
else
|
|
|
|
return ironlake_drpc_info(m);
|
|
|
|
}
|
|
|
|
|
2015-06-18 16:30:22 +08:00
|
|
|
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
|
|
|
|
dev_priv->fb_tracking.busy_bits);
|
|
|
|
|
|
|
|
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
|
|
|
|
dev_priv->fb_tracking.flip_bits);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-06 04:42:41 +08:00
|
|
|
static int i915_fbc_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-02-06 04:42:41 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-02-06 04:42:41 +08:00
|
|
|
|
2014-01-10 15:50:12 +08:00
|
|
|
if (!HAS_FBC(dev)) {
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "FBC unsupported on this chipset\n");
|
2010-02-06 04:42:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2015-07-03 06:25:10 +08:00
|
|
|
mutex_lock(&dev_priv->fbc.lock);
|
2014-02-22 00:52:23 +08:00
|
|
|
|
2015-10-15 04:45:36 +08:00
|
|
|
if (intel_fbc_is_active(dev_priv))
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "FBC enabled\n");
|
2015-06-13 01:36:20 +08:00
|
|
|
else
|
|
|
|
seq_printf(m, "FBC disabled: %s\n",
|
2015-10-28 00:50:03 +08:00
|
|
|
dev_priv->fbc.no_fbc_reason);
|
2014-02-22 00:52:23 +08:00
|
|
|
|
2015-06-13 01:36:18 +08:00
|
|
|
if (INTEL_INFO(dev_priv)->gen >= 7)
|
|
|
|
seq_printf(m, "Compressing: %s\n",
|
|
|
|
yesno(I915_READ(FBC_STATUS2) &
|
|
|
|
FBC_COMPRESSION_MASK));
|
|
|
|
|
2015-07-03 06:25:10 +08:00
|
|
|
mutex_unlock(&dev_priv->fbc.lock);
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2010-02-06 04:42:41 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-01 17:04:45 +08:00
|
|
|
static int i915_fbc_fc_get(void *data, u64 *val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
*val = dev_priv->fbc.false_color;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_fbc_fc_set(void *data, u64 val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2015-07-03 06:25:10 +08:00
|
|
|
mutex_lock(&dev_priv->fbc.lock);
|
2014-08-01 17:04:45 +08:00
|
|
|
|
|
|
|
reg = I915_READ(ILK_DPFC_CONTROL);
|
|
|
|
dev_priv->fbc.false_color = val;
|
|
|
|
|
|
|
|
I915_WRITE(ILK_DPFC_CONTROL, val ?
|
|
|
|
(reg | FBC_CTL_FALSE_COLOR) :
|
|
|
|
(reg & ~FBC_CTL_FALSE_COLOR));
|
|
|
|
|
2015-07-03 06:25:10 +08:00
|
|
|
mutex_unlock(&dev_priv->fbc.lock);
|
2014-08-01 17:04:45 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
|
|
|
|
i915_fbc_fc_get, i915_fbc_fc_set,
|
|
|
|
"%llu\n");
|
|
|
|
|
2013-06-01 03:33:24 +08:00
|
|
|
static int i915_ips_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2013-06-01 03:33:24 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-06-25 01:29:34 +08:00
|
|
|
if (!HAS_IPS(dev)) {
|
2013-06-01 03:33:24 +08:00
|
|
|
seq_puts(m, "not supported\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2014-06-30 19:45:01 +08:00
|
|
|
seq_printf(m, "Enabled by kernel parameter: %s\n",
|
|
|
|
yesno(i915.enable_ips));
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
seq_puts(m, "Currently: unknown\n");
|
|
|
|
} else {
|
|
|
|
if (I915_READ(IPS_CTL) & IPS_ENABLE)
|
|
|
|
seq_puts(m, "Currently: enabled\n");
|
|
|
|
else
|
|
|
|
seq_puts(m, "Currently: disabled\n");
|
|
|
|
}
|
2013-06-01 03:33:24 +08:00
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2013-06-01 03:33:24 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-06 04:47:35 +08:00
|
|
|
static int i915_sr_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-02-06 04:47:35 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-02-06 04:47:35 +08:00
|
|
|
bool sr_enabled = false;
|
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2010-12-15 15:42:31 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
2010-08-20 01:04:08 +08:00
|
|
|
sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
|
2015-06-02 19:17:47 +08:00
|
|
|
else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
|
|
|
|
IS_I945G(dev) || IS_I945GM(dev))
|
2010-02-06 04:47:35 +08:00
|
|
|
sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
|
|
|
|
else if (IS_I915GM(dev))
|
|
|
|
sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
|
|
|
|
else if (IS_PINEVIEW(dev))
|
|
|
|
sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
|
2015-12-10 04:29:35 +08:00
|
|
|
else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
2015-06-02 19:17:47 +08:00
|
|
|
sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
|
2010-02-06 04:47:35 +08:00
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2010-08-20 01:04:08 +08:00
|
|
|
seq_printf(m, "self-refresh: %s\n",
|
|
|
|
sr_enabled ? "enabled" : "disabled");
|
2010-02-06 04:47:35 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-21 05:28:11 +08:00
|
|
|
static int i915_emon_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-05-21 05:28:11 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-05-21 05:28:11 +08:00
|
|
|
unsigned long temp, chipset, gfx;
|
2010-07-03 14:58:38 +08:00
|
|
|
int ret;
|
|
|
|
|
2012-05-01 02:35:02 +08:00
|
|
|
if (!IS_GEN5(dev))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2010-07-03 14:58:38 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-05-21 05:28:11 +08:00
|
|
|
|
|
|
|
temp = i915_mch_val(dev_priv);
|
|
|
|
chipset = i915_chipset_val(dev_priv);
|
|
|
|
gfx = i915_gfx_val(dev_priv);
|
2010-07-03 14:58:38 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-05-21 05:28:11 +08:00
|
|
|
|
|
|
|
seq_printf(m, "GMCH temp: %ld\n", temp);
|
|
|
|
seq_printf(m, "Chipset power: %ld\n", chipset);
|
|
|
|
seq_printf(m, "GFX power: %ld\n", gfx);
|
|
|
|
seq_printf(m, "Total power: %ld\n", chipset + gfx);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-29 04:04:16 +08:00
|
|
|
static int i915_ring_freq_table(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2011-06-29 04:04:16 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-12-19 21:54:52 +08:00
|
|
|
int ret = 0;
|
2011-06-29 04:04:16 +08:00
|
|
|
int gpu_freq, ia_freq;
|
2015-06-29 17:20:22 +08:00
|
|
|
unsigned int max_gpu_freq, min_gpu_freq;
|
2011-06-29 04:04:16 +08:00
|
|
|
|
2015-06-29 17:20:23 +08:00
|
|
|
if (!HAS_CORE_RING_FREQ(dev)) {
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "unsupported on this chipset\n");
|
2011-06-29 04:04:16 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-12-19 21:54:52 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2013-09-17 05:56:43 +08:00
|
|
|
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
|
2011-06-29 04:04:16 +08:00
|
|
|
if (ret)
|
2013-12-19 21:54:52 +08:00
|
|
|
goto out;
|
2011-06-29 04:04:16 +08:00
|
|
|
|
2015-10-28 19:16:45 +08:00
|
|
|
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
|
2015-06-29 17:20:22 +08:00
|
|
|
/* Convert GT frequency to 50 HZ units */
|
|
|
|
min_gpu_freq =
|
|
|
|
dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
|
|
|
|
max_gpu_freq =
|
|
|
|
dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
|
|
|
|
} else {
|
|
|
|
min_gpu_freq = dev_priv->rps.min_freq_softlimit;
|
|
|
|
max_gpu_freq = dev_priv->rps.max_freq_softlimit;
|
|
|
|
}
|
|
|
|
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
|
2011-06-29 04:04:16 +08:00
|
|
|
|
2015-06-29 17:20:22 +08:00
|
|
|
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
|
2012-09-27 01:34:00 +08:00
|
|
|
ia_freq = gpu_freq;
|
|
|
|
sandybridge_pcode_read(dev_priv,
|
|
|
|
GEN6_PCODE_READ_MIN_FREQ_TABLE,
|
|
|
|
&ia_freq);
|
2013-04-13 02:10:13 +08:00
|
|
|
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
|
2015-06-29 17:20:22 +08:00
|
|
|
intel_gpu_freq(dev_priv, (gpu_freq *
|
2015-10-28 19:16:45 +08:00
|
|
|
(IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
|
|
|
|
GEN9_FREQ_SCALER : 1))),
|
2013-04-13 02:10:13 +08:00
|
|
|
((ia_freq >> 0) & 0xff) * 100,
|
|
|
|
((ia_freq >> 8) & 0xff) * 100);
|
2011-06-29 04:04:16 +08:00
|
|
|
}
|
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2011-06-29 04:04:16 +08:00
|
|
|
|
2013-12-19 21:54:52 +08:00
|
|
|
out:
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
return ret;
|
2011-06-29 04:04:16 +08:00
|
|
|
}
|
|
|
|
|
2010-08-19 23:09:23 +08:00
|
|
|
static int i915_opregion(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-08-19 23:09:23 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-08-19 23:09:23 +08:00
|
|
|
struct intel_opregion *opregion = &dev_priv->opregion;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
2012-04-22 04:49:10 +08:00
|
|
|
goto out;
|
2010-08-19 23:09:23 +08:00
|
|
|
|
2015-12-14 18:50:53 +08:00
|
|
|
if (opregion->header)
|
|
|
|
seq_write(m, opregion->header, OPREGION_SIZE);
|
2010-08-19 23:09:23 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2012-04-22 04:49:10 +08:00
|
|
|
out:
|
2010-08-19 23:09:23 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-15 19:17:12 +08:00
|
|
|
static int i915_vbt(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_opregion *opregion = &dev_priv->opregion;
|
|
|
|
|
|
|
|
if (opregion->vbt)
|
|
|
|
seq_write(m, opregion->vbt, opregion->vbt_size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-26 05:45:57 +08:00
|
|
|
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2010-08-26 05:45:57 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2015-11-27 16:13:11 +08:00
|
|
|
struct intel_framebuffer *fbdev_fb = NULL;
|
2015-07-11 01:02:51 +08:00
|
|
|
struct drm_framebuffer *drm_fb;
|
2016-04-03 21:14:20 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-08-26 05:45:57 +08:00
|
|
|
|
2015-08-10 19:34:08 +08:00
|
|
|
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
2015-11-27 16:13:11 +08:00
|
|
|
if (to_i915(dev)->fbdev) {
|
|
|
|
fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
|
|
|
|
|
|
|
|
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
|
|
|
|
fbdev_fb->base.width,
|
|
|
|
fbdev_fb->base.height,
|
|
|
|
fbdev_fb->base.depth,
|
|
|
|
fbdev_fb->base.bits_per_pixel,
|
|
|
|
fbdev_fb->base.modifier[0],
|
2016-04-15 13:10:35 +08:00
|
|
|
drm_framebuffer_read_refcount(&fbdev_fb->base));
|
2015-11-27 16:13:11 +08:00
|
|
|
describe_obj(m, fbdev_fb->obj);
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
2013-10-09 15:18:51 +08:00
|
|
|
#endif
|
2010-08-26 05:45:57 +08:00
|
|
|
|
drm: revamp locking around fb creation/destruction
Well, at least step 1. The goal here is that framebuffer objects can
survive outside of the mode_config lock, with just a reference held
as protection. The first step to get there is to introduce a special
fb_lock which protects fb lookup, creation and destruction, to make
them appear atomic.
This new fb_lock can nest within the mode_config lock. But the idea is
(once the reference counting part is completed) that we only quickly
take that fb_lock to lookup a framebuffer and grab a reference,
without any other locks involved.
vmwgfx is the only driver which does framebuffer lookups itself, also
wrap those calls to drm_mode_object_find with the new lock.
Also protect the fb_list walking in i915 and omapdrm with the new lock.
As a slight complication there's also the list of user-created fbs
attached to the file private. The problem now is that at fclose() time
we need to walk that list, eventually do a modeset call to remove the
fb from active usage (and are required to be able to take the
mode_config lock), but in the end we need to grab the new fb_lock to
remove the fb from the list. The easiest solution is to add another
mutex to protect this per-file list.
Currently that new fbs_lock nests within the modeset locks and so
appears redudant. But later patches will switch around this sequence
so that taking the modeset locks in the fb destruction path is
optional in the fastpath. Ultimately the goal is that addfb and rmfb
do not require the mode_config lock, since otherwise they have the
potential to introduce stalls in the pageflip sequence of a compositor
(if the compositor e.g. switches to a fullscreen client or if it
enables a plane). But that requires a few more steps and hoops to jump
through.
Note that framebuffer creation/destruction is now double-protected -
once by the fb_lock and in parts by the idr_lock. The later would be
unnecessariy if framebuffers would have their own idr allocator. But
that's material for another patch (series).
v2: Properly initialize the fb->filp_head list in _init, otherwise the
newly added WARN to check whether the fb isn't on a fpriv list any
more will fail for driver-private objects.
v3: Fixup two error-case unlock bugs spotted by Richard Wilbur.
Reviewed-by: Rob Clark <rob@ti.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-11 04:19:18 +08:00
|
|
|
mutex_lock(&dev->mode_config.fb_lock);
|
2015-07-11 01:02:51 +08:00
|
|
|
drm_for_each_fb(drm_fb, dev) {
|
2015-11-27 16:13:11 +08:00
|
|
|
struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
|
|
|
|
if (fb == fbdev_fb)
|
2010-08-26 05:45:57 +08:00
|
|
|
continue;
|
|
|
|
|
2015-02-11 01:16:07 +08:00
|
|
|
seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
|
2010-08-26 05:45:57 +08:00
|
|
|
fb->base.width,
|
|
|
|
fb->base.height,
|
|
|
|
fb->base.depth,
|
2012-12-11 23:21:38 +08:00
|
|
|
fb->base.bits_per_pixel,
|
2015-02-11 01:16:07 +08:00
|
|
|
fb->base.modifier[0],
|
2016-04-15 13:10:35 +08:00
|
|
|
drm_framebuffer_read_refcount(&fb->base));
|
2010-11-09 03:18:58 +08:00
|
|
|
describe_obj(m, fb->obj);
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_putc(m, '\n');
|
2010-08-26 05:45:57 +08:00
|
|
|
}
|
drm: revamp locking around fb creation/destruction
Well, at least step 1. The goal here is that framebuffer objects can
survive outside of the mode_config lock, with just a reference held
as protection. The first step to get there is to introduce a special
fb_lock which protects fb lookup, creation and destruction, to make
them appear atomic.
This new fb_lock can nest within the mode_config lock. But the idea is
(once the reference counting part is completed) that we only quickly
take that fb_lock to lookup a framebuffer and grab a reference,
without any other locks involved.
vmwgfx is the only driver which does framebuffer lookups itself, also
wrap those calls to drm_mode_object_find with the new lock.
Also protect the fb_list walking in i915 and omapdrm with the new lock.
As a slight complication there's also the list of user-created fbs
attached to the file private. The problem now is that at fclose() time
we need to walk that list, eventually do a modeset call to remove the
fb from active usage (and are required to be able to take the
mode_config lock), but in the end we need to grab the new fb_lock to
remove the fb from the list. The easiest solution is to add another
mutex to protect this per-file list.
Currently that new fbs_lock nests within the modeset locks and so
appears redudant. But later patches will switch around this sequence
so that taking the modeset locks in the fb destruction path is
optional in the fastpath. Ultimately the goal is that addfb and rmfb
do not require the mode_config lock, since otherwise they have the
potential to introduce stalls in the pageflip sequence of a compositor
(if the compositor e.g. switches to a fullscreen client or if it
enables a plane). But that requires a few more steps and hoops to jump
through.
Note that framebuffer creation/destruction is now double-protected -
once by the fb_lock and in parts by the idr_lock. The later would be
unnecessariy if framebuffers would have their own idr allocator. But
that's material for another patch (series).
v2: Properly initialize the fb->filp_head list in _init, otherwise the
newly added WARN to check whether the fb isn't on a fpriv list any
more will fail for driver-private objects.
v3: Fixup two error-case unlock bugs spotted by Richard Wilbur.
Reviewed-by: Rob Clark <rob@ti.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-11 04:19:18 +08:00
|
|
|
mutex_unlock(&dev->mode_config.fb_lock);
|
2016-04-03 21:14:20 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2010-08-26 05:45:57 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-25 00:04:46 +08:00
|
|
|
static void describe_ctx_ringbuf(struct seq_file *m,
|
|
|
|
struct intel_ringbuffer *ringbuf)
|
|
|
|
{
|
|
|
|
seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
|
|
|
|
ringbuf->space, ringbuf->head, ringbuf->tail,
|
|
|
|
ringbuf->last_retired_head);
|
|
|
|
}
|
|
|
|
|
2011-03-20 09:14:29 +08:00
|
|
|
static int i915_context_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2011-03-20 09:14:29 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2016-05-24 21:53:34 +08:00
|
|
|
struct i915_gem_context *ctx;
|
2016-03-24 02:19:53 +08:00
|
|
|
enum intel_engine_id id;
|
|
|
|
int ret;
|
2011-03-20 09:14:29 +08:00
|
|
|
|
2014-05-30 05:23:08 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
2011-03-20 09:14:29 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-09-18 12:12:45 +08:00
|
|
|
list_for_each_entry(ctx, &dev_priv->context_list, link) {
|
2014-07-25 00:04:46 +08:00
|
|
|
if (!i915.enable_execlists &&
|
|
|
|
ctx->legacy_hw_ctx.rcs_state == NULL)
|
2014-04-30 15:30:00 +08:00
|
|
|
continue;
|
|
|
|
|
2016-04-28 16:56:51 +08:00
|
|
|
seq_printf(m, "HW context %u ", ctx->hw_id);
|
drm/i915: Do remaps for all contexts
On both Ivybridge and Haswell, row remapping information is saved and
restored with context. This means, we never actually properly supported
the l3 remapping because our sysfs interface is asynchronous (and not
tied to any context), and the known faulty HW would be reused by the
next context to run.
Not that due to the asynchronous nature of the sysfs entry, there is no
point modifying the registers for the existing context. Instead we set a
flag for all contexts to load the correct remapping information on the
next run. Interested clients can use debugfs to determine whether or not
the row has been remapped.
One could propose at this point that we just do the remapping in the
kernel. I guess since we have to maintain the sysfs interface anyway,
I'm not sure how useful it is, and I do like keeping the policy in
userspace; (it wasn't my original decision to make the
interface the way it is, so I'm not attached).
v2: Force a context switch when we have a remap on the next switch.
(Ville)
Don't let userspace use the interface with disabled contexts.
v3: Don't force a context switch, just let it nop
Improper context slice remap initialization, 1<<1 instead of 1<<i, but I
rewrote it to avoid a second round of confusion.
Error print moved to error path (All Ville)
Added a comment on why the slice remap initialization happens.
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-19 10:03:18 +08:00
|
|
|
describe_ctx(m, ctx);
|
2016-01-20 03:02:55 +08:00
|
|
|
if (ctx == dev_priv->kernel_context)
|
|
|
|
seq_printf(m, "(kernel context) ");
|
2014-07-25 00:04:46 +08:00
|
|
|
|
|
|
|
if (i915.enable_execlists) {
|
|
|
|
seq_putc(m, '\n');
|
2016-03-24 02:19:53 +08:00
|
|
|
for_each_engine_id(engine, dev_priv, id) {
|
2014-07-25 00:04:46 +08:00
|
|
|
struct drm_i915_gem_object *ctx_obj =
|
2016-03-24 02:19:53 +08:00
|
|
|
ctx->engine[id].state;
|
2014-07-25 00:04:46 +08:00
|
|
|
struct intel_ringbuffer *ringbuf =
|
2016-03-24 02:19:53 +08:00
|
|
|
ctx->engine[id].ringbuf;
|
2014-07-25 00:04:46 +08:00
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s: ", engine->name);
|
2014-07-25 00:04:46 +08:00
|
|
|
if (ctx_obj)
|
|
|
|
describe_obj(m, ctx_obj);
|
|
|
|
if (ringbuf)
|
|
|
|
describe_ctx_ringbuf(m, ringbuf);
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
|
|
|
|
}
|
2013-09-18 12:12:45 +08:00
|
|
|
|
|
|
|
seq_putc(m, '\n');
|
2013-02-15 07:05:12 +08:00
|
|
|
}
|
|
|
|
|
2014-05-30 05:23:08 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2011-03-20 09:14:29 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-12-02 21:21:18 +08:00
|
|
|
static void i915_dump_lrc_obj(struct seq_file *m,
|
2016-05-24 21:53:34 +08:00
|
|
|
struct i915_gem_context *ctx,
|
2016-03-16 19:00:37 +08:00
|
|
|
struct intel_engine_cs *engine)
|
2014-12-02 21:21:18 +08:00
|
|
|
{
|
|
|
|
struct page *page;
|
|
|
|
uint32_t *reg_state;
|
|
|
|
int j;
|
2016-03-16 19:00:37 +08:00
|
|
|
struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
|
2014-12-02 21:21:18 +08:00
|
|
|
unsigned long ggtt_offset = 0;
|
|
|
|
|
2016-04-28 16:56:52 +08:00
|
|
|
seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
|
|
|
|
|
2014-12-02 21:21:18 +08:00
|
|
|
if (ctx_obj == NULL) {
|
2016-04-28 16:56:52 +08:00
|
|
|
seq_puts(m, "\tNot allocated\n");
|
2014-12-02 21:21:18 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!i915_gem_obj_ggtt_bound(ctx_obj))
|
|
|
|
seq_puts(m, "\tNot bound in GGTT\n");
|
|
|
|
else
|
|
|
|
ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
|
|
|
|
|
|
|
|
if (i915_gem_object_get_pages(ctx_obj)) {
|
|
|
|
seq_puts(m, "\tFailed to get pages for context object\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
|
2014-12-02 21:21:18 +08:00
|
|
|
if (!WARN_ON(page == NULL)) {
|
|
|
|
reg_state = kmap_atomic(page);
|
|
|
|
|
|
|
|
for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
|
|
|
|
seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
|
|
ggtt_offset + 4096 + (j * 4),
|
|
|
|
reg_state[j], reg_state[j + 1],
|
|
|
|
reg_state[j + 2], reg_state[j + 3]);
|
|
|
|
}
|
|
|
|
kunmap_atomic(reg_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
|
2014-08-07 20:24:26 +08:00
|
|
|
static int i915_dump_lrc(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2016-05-24 21:53:34 +08:00
|
|
|
struct i915_gem_context *ctx;
|
2016-03-24 19:20:38 +08:00
|
|
|
int ret;
|
2014-08-07 20:24:26 +08:00
|
|
|
|
|
|
|
if (!i915.enable_execlists) {
|
|
|
|
seq_printf(m, "Logical Ring Contexts are disabled\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-01-20 03:02:55 +08:00
|
|
|
list_for_each_entry(ctx, &dev_priv->context_list, link)
|
2016-04-28 16:56:53 +08:00
|
|
|
for_each_engine(engine, dev_priv)
|
|
|
|
i915_dump_lrc_obj(m, ctx, engine);
|
2014-08-07 20:24:26 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-07 20:23:20 +08:00
|
|
|
static int i915_execlists(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2014-08-07 20:23:20 +08:00
|
|
|
u32 status_pointer;
|
|
|
|
u8 read_pointer;
|
|
|
|
u8 write_pointer;
|
|
|
|
u32 status;
|
|
|
|
u32 ctx_id;
|
|
|
|
struct list_head *cursor;
|
2016-03-24 19:20:38 +08:00
|
|
|
int i, ret;
|
2014-08-07 20:23:20 +08:00
|
|
|
|
|
|
|
if (!i915.enable_execlists) {
|
|
|
|
seq_puts(m, "Logical Ring Contexts are disabled\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-10-16 23:13:38 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2015-01-15 21:10:39 +08:00
|
|
|
struct drm_i915_gem_request *head_req = NULL;
|
2014-08-07 20:23:20 +08:00
|
|
|
int count = 0;
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s\n", engine->name);
|
2014-08-07 20:23:20 +08:00
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
|
|
|
|
ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
|
2014-08-07 20:23:20 +08:00
|
|
|
seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
|
|
|
|
status, ctx_id);
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
|
2014-08-07 20:23:20 +08:00
|
|
|
seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
read_pointer = engine->next_context_status_buffer;
|
2016-01-06 02:30:05 +08:00
|
|
|
write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
|
2014-08-07 20:23:20 +08:00
|
|
|
if (read_pointer > write_pointer)
|
2016-01-06 02:30:05 +08:00
|
|
|
write_pointer += GEN8_CSB_ENTRIES;
|
2014-08-07 20:23:20 +08:00
|
|
|
seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
|
|
|
|
read_pointer, write_pointer);
|
|
|
|
|
2016-01-06 02:30:05 +08:00
|
|
|
for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
|
2016-03-16 19:00:36 +08:00
|
|
|
status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
|
|
|
|
ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
|
2014-08-07 20:23:20 +08:00
|
|
|
|
|
|
|
seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
|
|
|
|
i, status, ctx_id);
|
|
|
|
}
|
|
|
|
|
drm/i915: Move execlists irq handler to a bottom half
Doing a lot of work in the interrupt handler introduces huge
latencies to the system as a whole.
Most dramatic effect can be seen by running an all engine
stress test like igt/gem_exec_nop/all where, when the kernel
config is lean enough, the whole system can be brought into
multi-second periods of complete non-interactivty. That can
look for example like this:
NMI watchdog: BUG: soft lockup - CPU#0 stuck for 23s! [kworker/u8:3:143]
Modules linked in: [redacted for brevity]
CPU: 0 PID: 143 Comm: kworker/u8:3 Tainted: G U L 4.5.0-160321+ #183
Hardware name: Intel Corporation Broadwell Client platform/WhiteTip Mountain 1
Workqueue: i915 gen6_pm_rps_work [i915]
task: ffff8800aae88000 ti: ffff8800aae90000 task.ti: ffff8800aae90000
RIP: 0010:[<ffffffff8104a3c2>] [<ffffffff8104a3c2>] __do_softirq+0x72/0x1d0
RSP: 0000:ffff88014f403f38 EFLAGS: 00000206
RAX: ffff8800aae94000 RBX: 0000000000000000 RCX: 00000000000006e0
RDX: 0000000000000020 RSI: 0000000004208060 RDI: 0000000000215d80
RBP: ffff88014f403f80 R08: 0000000b1b42c180 R09: 0000000000000022
R10: 0000000000000004 R11: 00000000ffffffff R12: 000000000000a030
R13: 0000000000000082 R14: ffff8800aa4d0080 R15: 0000000000000082
FS: 0000000000000000(0000) GS:ffff88014f400000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00007fa53b90c000 CR3: 0000000001a0a000 CR4: 00000000001406f0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Stack:
042080601b33869f ffff8800aae94000 00000000fffc2678 ffff88010000000a
0000000000000000 000000000000a030 0000000000005302 ffff8800aa4d0080
0000000000000206 ffff88014f403f90 ffffffff8104a716 ffff88014f403fa8
Call Trace:
<IRQ>
[<ffffffff8104a716>] irq_exit+0x86/0x90
[<ffffffff81031e7d>] smp_apic_timer_interrupt+0x3d/0x50
[<ffffffff814f3eac>] apic_timer_interrupt+0x7c/0x90
<EOI>
[<ffffffffa01c5b40>] ? gen8_write64+0x1a0/0x1a0 [i915]
[<ffffffff814f2b39>] ? _raw_spin_unlock_irqrestore+0x9/0x20
[<ffffffffa01c5c44>] gen8_write32+0x104/0x1a0 [i915]
[<ffffffff8132c6a2>] ? n_tty_receive_buf_common+0x372/0xae0
[<ffffffffa017cc9e>] gen6_set_rps_thresholds+0x1be/0x330 [i915]
[<ffffffffa017eaf0>] gen6_set_rps+0x70/0x200 [i915]
[<ffffffffa0185375>] intel_set_rps+0x25/0x30 [i915]
[<ffffffffa01768fd>] gen6_pm_rps_work+0x10d/0x2e0 [i915]
[<ffffffff81063852>] ? finish_task_switch+0x72/0x1c0
[<ffffffff8105ab29>] process_one_work+0x139/0x350
[<ffffffff8105b186>] worker_thread+0x126/0x490
[<ffffffff8105b060>] ? rescuer_thread+0x320/0x320
[<ffffffff8105fa64>] kthread+0xc4/0xe0
[<ffffffff8105f9a0>] ? kthread_create_on_node+0x170/0x170
[<ffffffff814f351f>] ret_from_fork+0x3f/0x70
[<ffffffff8105f9a0>] ? kthread_create_on_node+0x170/0x170
I could not explain, or find a code path, which would explain
a +20 second lockup, but from some instrumentation it was
apparent the interrupts off proportion of time was between
10-25% under heavy load which is quite bad.
When a interrupt "cliff" is reached, which was >~320k irq/s on
my machine, the whole system goes into a terrible state of the
above described multi-second lockups.
By moving the GT interrupt handling to a tasklet in a most
simple way, the problem above disappears completely.
Testing the effect on sytem-wide latencies using
igt/gem_syslatency shows the following before this patch:
gem_syslatency: cycles=1532739, latency mean=416531.829us max=2499237us
gem_syslatency: cycles=1839434, latency mean=1458099.157us max=4998944us
gem_syslatency: cycles=1432570, latency mean=2688.451us max=1201185us
gem_syslatency: cycles=1533543, latency mean=416520.499us max=2498886us
This shows that the unrelated process is experiencing huge
delays in its wake-up latency. After the patch the results
look like this:
gem_syslatency: cycles=808907, latency mean=53.133us max=1640us
gem_syslatency: cycles=862154, latency mean=62.778us max=2117us
gem_syslatency: cycles=856039, latency mean=58.079us max=2123us
gem_syslatency: cycles=841683, latency mean=56.914us max=1667us
Showing a huge improvement in the unrelated process wake-up
latency. It also shows an approximate halving in the number
of total empty batches submitted during the test. This may
not be worrying since the test puts the driver under
a very unrealistic load with ncpu threads doing empty batch
submission to all GPU engines each.
Another benefit compared to the hard-irq handling is that now
work on all engines can be dispatched in parallel since we can
have up to number of CPUs active tasklets. (While previously
a single hard-irq would serially dispatch on one engine after
another.)
More interesting scenario with regards to throughput is
"gem_latency -n 100" which shows 25% better throughput and
CPU usage, and 14% better dispatch latencies.
I did not find any gains or regressions with Synmark2 or
GLbench under light testing. More benchmarking is certainly
required.
v2:
* execlists_lock should be taken as spin_lock_bh when
queuing work from userspace now. (Chris Wilson)
* uncore.lock must be taken with spin_lock_irq when
submitting requests since that now runs from either
softirq or process context.
v3:
* Expanded commit message with more testing data;
* converted missed locking sites to _bh;
* added execlist_lock comment. (Chris Wilson)
v4:
* Mention dispatch parallelism in commit. (Chris Wilson)
* Do not hold uncore.lock over MMIO reads since the block
is already serialised per-engine via the tasklet itself.
(Chris Wilson)
* intel_lrc_irq_handler should be static. (Chris Wilson)
* Cancel/sync the tasklet on GPU reset. (Chris Wilson)
* Document and WARN that tasklet cannot be active/pending
on engine cleanup. (Chris Wilson/Imre Deak)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Testcase: igt/gem_exec_nop/all
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94350
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1459768316-6670-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-04-04 19:11:56 +08:00
|
|
|
spin_lock_bh(&engine->execlist_lock);
|
2016-03-16 19:00:36 +08:00
|
|
|
list_for_each(cursor, &engine->execlist_queue)
|
2014-08-07 20:23:20 +08:00
|
|
|
count++;
|
2016-03-16 19:00:36 +08:00
|
|
|
head_req = list_first_entry_or_null(&engine->execlist_queue,
|
|
|
|
struct drm_i915_gem_request,
|
|
|
|
execlist_link);
|
drm/i915: Move execlists irq handler to a bottom half
Doing a lot of work in the interrupt handler introduces huge
latencies to the system as a whole.
Most dramatic effect can be seen by running an all engine
stress test like igt/gem_exec_nop/all where, when the kernel
config is lean enough, the whole system can be brought into
multi-second periods of complete non-interactivty. That can
look for example like this:
NMI watchdog: BUG: soft lockup - CPU#0 stuck for 23s! [kworker/u8:3:143]
Modules linked in: [redacted for brevity]
CPU: 0 PID: 143 Comm: kworker/u8:3 Tainted: G U L 4.5.0-160321+ #183
Hardware name: Intel Corporation Broadwell Client platform/WhiteTip Mountain 1
Workqueue: i915 gen6_pm_rps_work [i915]
task: ffff8800aae88000 ti: ffff8800aae90000 task.ti: ffff8800aae90000
RIP: 0010:[<ffffffff8104a3c2>] [<ffffffff8104a3c2>] __do_softirq+0x72/0x1d0
RSP: 0000:ffff88014f403f38 EFLAGS: 00000206
RAX: ffff8800aae94000 RBX: 0000000000000000 RCX: 00000000000006e0
RDX: 0000000000000020 RSI: 0000000004208060 RDI: 0000000000215d80
RBP: ffff88014f403f80 R08: 0000000b1b42c180 R09: 0000000000000022
R10: 0000000000000004 R11: 00000000ffffffff R12: 000000000000a030
R13: 0000000000000082 R14: ffff8800aa4d0080 R15: 0000000000000082
FS: 0000000000000000(0000) GS:ffff88014f400000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00007fa53b90c000 CR3: 0000000001a0a000 CR4: 00000000001406f0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
Stack:
042080601b33869f ffff8800aae94000 00000000fffc2678 ffff88010000000a
0000000000000000 000000000000a030 0000000000005302 ffff8800aa4d0080
0000000000000206 ffff88014f403f90 ffffffff8104a716 ffff88014f403fa8
Call Trace:
<IRQ>
[<ffffffff8104a716>] irq_exit+0x86/0x90
[<ffffffff81031e7d>] smp_apic_timer_interrupt+0x3d/0x50
[<ffffffff814f3eac>] apic_timer_interrupt+0x7c/0x90
<EOI>
[<ffffffffa01c5b40>] ? gen8_write64+0x1a0/0x1a0 [i915]
[<ffffffff814f2b39>] ? _raw_spin_unlock_irqrestore+0x9/0x20
[<ffffffffa01c5c44>] gen8_write32+0x104/0x1a0 [i915]
[<ffffffff8132c6a2>] ? n_tty_receive_buf_common+0x372/0xae0
[<ffffffffa017cc9e>] gen6_set_rps_thresholds+0x1be/0x330 [i915]
[<ffffffffa017eaf0>] gen6_set_rps+0x70/0x200 [i915]
[<ffffffffa0185375>] intel_set_rps+0x25/0x30 [i915]
[<ffffffffa01768fd>] gen6_pm_rps_work+0x10d/0x2e0 [i915]
[<ffffffff81063852>] ? finish_task_switch+0x72/0x1c0
[<ffffffff8105ab29>] process_one_work+0x139/0x350
[<ffffffff8105b186>] worker_thread+0x126/0x490
[<ffffffff8105b060>] ? rescuer_thread+0x320/0x320
[<ffffffff8105fa64>] kthread+0xc4/0xe0
[<ffffffff8105f9a0>] ? kthread_create_on_node+0x170/0x170
[<ffffffff814f351f>] ret_from_fork+0x3f/0x70
[<ffffffff8105f9a0>] ? kthread_create_on_node+0x170/0x170
I could not explain, or find a code path, which would explain
a +20 second lockup, but from some instrumentation it was
apparent the interrupts off proportion of time was between
10-25% under heavy load which is quite bad.
When a interrupt "cliff" is reached, which was >~320k irq/s on
my machine, the whole system goes into a terrible state of the
above described multi-second lockups.
By moving the GT interrupt handling to a tasklet in a most
simple way, the problem above disappears completely.
Testing the effect on sytem-wide latencies using
igt/gem_syslatency shows the following before this patch:
gem_syslatency: cycles=1532739, latency mean=416531.829us max=2499237us
gem_syslatency: cycles=1839434, latency mean=1458099.157us max=4998944us
gem_syslatency: cycles=1432570, latency mean=2688.451us max=1201185us
gem_syslatency: cycles=1533543, latency mean=416520.499us max=2498886us
This shows that the unrelated process is experiencing huge
delays in its wake-up latency. After the patch the results
look like this:
gem_syslatency: cycles=808907, latency mean=53.133us max=1640us
gem_syslatency: cycles=862154, latency mean=62.778us max=2117us
gem_syslatency: cycles=856039, latency mean=58.079us max=2123us
gem_syslatency: cycles=841683, latency mean=56.914us max=1667us
Showing a huge improvement in the unrelated process wake-up
latency. It also shows an approximate halving in the number
of total empty batches submitted during the test. This may
not be worrying since the test puts the driver under
a very unrealistic load with ncpu threads doing empty batch
submission to all GPU engines each.
Another benefit compared to the hard-irq handling is that now
work on all engines can be dispatched in parallel since we can
have up to number of CPUs active tasklets. (While previously
a single hard-irq would serially dispatch on one engine after
another.)
More interesting scenario with regards to throughput is
"gem_latency -n 100" which shows 25% better throughput and
CPU usage, and 14% better dispatch latencies.
I did not find any gains or regressions with Synmark2 or
GLbench under light testing. More benchmarking is certainly
required.
v2:
* execlists_lock should be taken as spin_lock_bh when
queuing work from userspace now. (Chris Wilson)
* uncore.lock must be taken with spin_lock_irq when
submitting requests since that now runs from either
softirq or process context.
v3:
* Expanded commit message with more testing data;
* converted missed locking sites to _bh;
* added execlist_lock comment. (Chris Wilson)
v4:
* Mention dispatch parallelism in commit. (Chris Wilson)
* Do not hold uncore.lock over MMIO reads since the block
is already serialised per-engine via the tasklet itself.
(Chris Wilson)
* intel_lrc_irq_handler should be static. (Chris Wilson)
* Cancel/sync the tasklet on GPU reset. (Chris Wilson)
* Document and WARN that tasklet cannot be active/pending
on engine cleanup. (Chris Wilson/Imre Deak)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Testcase: igt/gem_exec_nop/all
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94350
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1459768316-6670-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-04-04 19:11:56 +08:00
|
|
|
spin_unlock_bh(&engine->execlist_lock);
|
2014-08-07 20:23:20 +08:00
|
|
|
|
|
|
|
seq_printf(m, "\t%d requests in queue\n", count);
|
|
|
|
if (head_req) {
|
2016-04-28 16:56:52 +08:00
|
|
|
seq_printf(m, "\tHead request context: %u\n",
|
|
|
|
head_req->ctx->hw_id);
|
2014-08-07 20:23:20 +08:00
|
|
|
seq_printf(m, "\tHead request tail: %u\n",
|
2015-01-15 21:10:39 +08:00
|
|
|
head_req->tail);
|
2014-08-07 20:23:20 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
|
2014-10-16 23:13:38 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2014-08-07 20:23:20 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-12-14 20:57:16 +08:00
|
|
|
static const char *swizzle_string(unsigned swizzle)
|
|
|
|
{
|
2013-06-25 05:59:49 +08:00
|
|
|
switch (swizzle) {
|
2011-12-14 20:57:16 +08:00
|
|
|
case I915_BIT_6_SWIZZLE_NONE:
|
|
|
|
return "none";
|
|
|
|
case I915_BIT_6_SWIZZLE_9:
|
|
|
|
return "bit9";
|
|
|
|
case I915_BIT_6_SWIZZLE_9_10:
|
|
|
|
return "bit9/bit10";
|
|
|
|
case I915_BIT_6_SWIZZLE_9_11:
|
|
|
|
return "bit9/bit11";
|
|
|
|
case I915_BIT_6_SWIZZLE_9_10_11:
|
|
|
|
return "bit9/bit10/bit11";
|
|
|
|
case I915_BIT_6_SWIZZLE_9_17:
|
|
|
|
return "bit9/bit17";
|
|
|
|
case I915_BIT_6_SWIZZLE_9_10_17:
|
|
|
|
return "bit9/bit10/bit17";
|
|
|
|
case I915_BIT_6_SWIZZLE_UNKNOWN:
|
2012-12-29 01:00:09 +08:00
|
|
|
return "unknown";
|
2011-12-14 20:57:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return "bug";
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_swizzle_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2011-12-14 20:57:16 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-08-09 21:07:02 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2011-12-14 20:57:16 +08:00
|
|
|
|
|
|
|
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
|
|
|
|
swizzle_string(dev_priv->mm.bit_6_swizzle_x));
|
|
|
|
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
|
|
|
|
swizzle_string(dev_priv->mm.bit_6_swizzle_y));
|
|
|
|
|
|
|
|
if (IS_GEN3(dev) || IS_GEN4(dev)) {
|
|
|
|
seq_printf(m, "DDC = 0x%08x\n",
|
|
|
|
I915_READ(DCC));
|
2014-11-20 16:26:30 +08:00
|
|
|
seq_printf(m, "DDC2 = 0x%08x\n",
|
|
|
|
I915_READ(DCC2));
|
2011-12-14 20:57:16 +08:00
|
|
|
seq_printf(m, "C0DRB3 = 0x%04x\n",
|
|
|
|
I915_READ16(C0DRB3));
|
|
|
|
seq_printf(m, "C1DRB3 = 0x%04x\n",
|
|
|
|
I915_READ16(C1DRB3));
|
2013-11-03 12:07:14 +08:00
|
|
|
} else if (INTEL_INFO(dev)->gen >= 6) {
|
2012-01-31 23:47:56 +08:00
|
|
|
seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
|
|
|
|
I915_READ(MAD_DIMM_C0));
|
|
|
|
seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
|
|
|
|
I915_READ(MAD_DIMM_C1));
|
|
|
|
seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
|
|
|
|
I915_READ(MAD_DIMM_C2));
|
|
|
|
seq_printf(m, "TILECTL = 0x%08x\n",
|
|
|
|
I915_READ(TILECTL));
|
2014-01-23 22:23:14 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 8)
|
2013-11-03 12:07:14 +08:00
|
|
|
seq_printf(m, "GAMTARBMODE = 0x%08x\n",
|
|
|
|
I915_READ(GAMTARBMODE));
|
|
|
|
else
|
|
|
|
seq_printf(m, "ARB_MODE = 0x%08x\n",
|
|
|
|
I915_READ(ARB_MODE));
|
2012-01-31 23:47:56 +08:00
|
|
|
seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
|
|
|
|
I915_READ(DISP_ARB_CTL));
|
2011-12-14 20:57:16 +08:00
|
|
|
}
|
2014-11-20 16:26:30 +08:00
|
|
|
|
|
|
|
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
|
|
|
seq_puts(m, "L-shaped memory detected\n");
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2011-12-14 20:57:16 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-12-07 06:11:30 +08:00
|
|
|
static int per_file_ctx(int id, void *ptr, void *data)
|
|
|
|
{
|
2016-05-24 21:53:34 +08:00
|
|
|
struct i915_gem_context *ctx = ptr;
|
2013-12-07 06:11:30 +08:00
|
|
|
struct seq_file *m = data;
|
2014-08-06 21:04:53 +08:00
|
|
|
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
|
|
|
|
|
|
|
|
if (!ppgtt) {
|
|
|
|
seq_printf(m, " no ppgtt for context %d\n",
|
|
|
|
ctx->user_handle);
|
|
|
|
return 0;
|
|
|
|
}
|
2013-12-07 06:11:30 +08:00
|
|
|
|
2014-05-22 21:13:38 +08:00
|
|
|
if (i915_gem_context_is_default(ctx))
|
|
|
|
seq_puts(m, " default context:\n");
|
|
|
|
else
|
drm/i915: Emphasize that ctx->id is merely a user handle
This is an Execlists preparatory patch, since they make context ID become an
overloaded term:
- In the software, it was used to distinguish which context userspace was
trying to use.
- In the BSpec, the term is used to describe the 20-bits long field the
hardware uses to it to discriminate the contexts that are submitted to
the ELSP and inform the driver about their current status (via Context
Switch Interrupts and Context Status Buffers).
Initially, I tried to make the different meanings converge, but it proved
impossible:
- The software ctx->id is per-filp, while the hardware one needs to be
globally unique.
- Also, we multiplex several backing states objects per intel_context,
and all of them need unique HW IDs.
- I tried adding a per-filp ID and then composing the HW context ID as:
ctx->id + file_priv->id + ring->id, but the fact that the hardware only
uses 20-bits means we have to artificially limit the number of filps or
contexts the userspace can create.
The ctx->user_handle renaming bits are done with this Cocci patch (plus
manual frobbing of the struct declaration):
@@
struct intel_context c;
@@
- (c).id
+ c.user_handle
@@
struct intel_context *c;
@@
- (c)->id
+ c->user_handle
Also, while we are at it, s/DEFAULT_CONTEXT_ID/DEFAULT_CONTEXT_HANDLE and
change the type to unsigned 32 bits.
v2: s/handle/user_handle and change the type to uint32_t as suggested by
Chris Wilson.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-03 23:28:00 +08:00
|
|
|
seq_printf(m, " context %d:\n", ctx->user_handle);
|
2013-12-07 06:11:30 +08:00
|
|
|
ppgtt->debug_dump(ppgtt, m);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-03 12:07:30 +08:00
|
|
|
static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
|
2012-02-10 00:15:49 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2013-11-03 12:07:30 +08:00
|
|
|
struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
|
2016-03-24 19:20:38 +08:00
|
|
|
int i;
|
2012-02-10 00:15:49 +08:00
|
|
|
|
2013-11-03 12:07:30 +08:00
|
|
|
if (!ppgtt)
|
|
|
|
return;
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s\n", engine->name);
|
2013-11-03 12:07:30 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
2016-03-16 19:00:36 +08:00
|
|
|
u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
|
2013-11-03 12:07:30 +08:00
|
|
|
pdp <<= 32;
|
2016-03-16 19:00:36 +08:00
|
|
|
pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
|
2014-03-31 23:17:16 +08:00
|
|
|
seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
|
2013-11-03 12:07:30 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2012-02-10 00:15:49 +08:00
|
|
|
|
2016-05-10 17:57:06 +08:00
|
|
|
if (IS_GEN6(dev_priv))
|
2012-02-10 00:15:49 +08:00
|
|
|
seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s\n", engine->name);
|
2016-05-10 17:57:06 +08:00
|
|
|
if (IS_GEN7(dev_priv))
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "GFX_MODE: 0x%08x\n",
|
|
|
|
I915_READ(RING_MODE_GEN7(engine)));
|
|
|
|
seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
|
|
|
|
I915_READ(RING_PP_DIR_BASE(engine)));
|
|
|
|
seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
|
|
|
|
I915_READ(RING_PP_DIR_BASE_READ(engine)));
|
|
|
|
seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
|
|
|
|
I915_READ(RING_PP_DIR_DCLV(engine)));
|
2012-02-10 00:15:49 +08:00
|
|
|
}
|
|
|
|
if (dev_priv->mm.aliasing_ppgtt) {
|
|
|
|
struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
|
|
|
|
|
2013-06-25 05:59:48 +08:00
|
|
|
seq_puts(m, "aliasing PPGTT:\n");
|
2015-06-25 23:35:07 +08:00
|
|
|
seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
|
2013-12-07 06:11:30 +08:00
|
|
|
|
2013-12-07 06:11:29 +08:00
|
|
|
ppgtt->debug_dump(ppgtt, m);
|
2014-08-06 21:04:53 +08:00
|
|
|
}
|
2013-12-07 06:11:30 +08:00
|
|
|
|
2012-02-10 00:15:49 +08:00
|
|
|
seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
|
2013-11-03 12:07:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_ppgtt_info(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2013-11-03 12:07:30 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2013-11-28 04:21:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2015-07-30 00:23:57 +08:00
|
|
|
struct drm_file *file;
|
2013-11-03 12:07:30 +08:00
|
|
|
|
|
|
|
int ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2013-11-03 12:07:30 +08:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8)
|
|
|
|
gen8_ppgtt_info(m, dev);
|
|
|
|
else if (INTEL_INFO(dev)->gen >= 6)
|
|
|
|
gen6_ppgtt_info(m, dev);
|
|
|
|
|
2016-04-27 01:29:41 +08:00
|
|
|
mutex_lock(&dev->filelist_mutex);
|
2015-07-30 00:23:57 +08:00
|
|
|
list_for_each_entry_reverse(file, &dev->filelist, lhead) {
|
|
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
2015-09-25 18:58:11 +08:00
|
|
|
struct task_struct *task;
|
2015-07-30 00:23:57 +08:00
|
|
|
|
2015-09-25 18:58:11 +08:00
|
|
|
task = get_pid_task(file->pid, PIDTYPE_PID);
|
2015-10-02 23:14:22 +08:00
|
|
|
if (!task) {
|
|
|
|
ret = -ESRCH;
|
|
|
|
goto out_put;
|
|
|
|
}
|
2015-09-25 18:58:11 +08:00
|
|
|
seq_printf(m, "\nproc: %s\n", task->comm);
|
|
|
|
put_task_struct(task);
|
2015-07-30 00:23:57 +08:00
|
|
|
idr_for_each(&file_priv->context_idr, per_file_ctx,
|
|
|
|
(void *)(unsigned long)m);
|
|
|
|
}
|
2016-04-27 01:29:41 +08:00
|
|
|
mutex_unlock(&dev->filelist_mutex);
|
2015-07-30 00:23:57 +08:00
|
|
|
|
2015-10-02 23:14:22 +08:00
|
|
|
out_put:
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2012-02-10 00:15:49 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2015-10-02 23:14:22 +08:00
|
|
|
return ret;
|
2012-02-10 00:15:49 +08:00
|
|
|
}
|
|
|
|
|
2015-04-27 20:41:23 +08:00
|
|
|
static int count_irq_waiters(struct drm_i915_private *i915)
|
|
|
|
{
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2015-04-27 20:41:23 +08:00
|
|
|
int count = 0;
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, i915)
|
2016-03-16 19:00:36 +08:00
|
|
|
count += engine->irq_refcount;
|
2015-04-27 20:41:23 +08:00
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2015-04-07 23:20:32 +08:00
|
|
|
static int i915_rps_boost_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_file *file;
|
|
|
|
|
2015-04-27 20:41:23 +08:00
|
|
|
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
|
|
|
|
seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
|
|
|
|
seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
|
|
|
|
seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
|
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
|
2016-04-27 01:29:41 +08:00
|
|
|
|
|
|
|
mutex_lock(&dev->filelist_mutex);
|
2015-05-22 04:01:47 +08:00
|
|
|
spin_lock(&dev_priv->rps.client_lock);
|
2015-04-07 23:20:32 +08:00
|
|
|
list_for_each_entry_reverse(file, &dev->filelist, lhead) {
|
|
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
|
|
struct task_struct *task;
|
|
|
|
|
|
|
|
rcu_read_lock();
|
|
|
|
task = pid_task(file->pid, PIDTYPE_PID);
|
|
|
|
seq_printf(m, "%s [%d]: %d boosts%s\n",
|
|
|
|
task ? task->comm : "<unknown>",
|
|
|
|
task ? task->pid : -1,
|
2015-04-27 20:41:22 +08:00
|
|
|
file_priv->rps.boosts,
|
|
|
|
list_empty(&file_priv->rps.link) ? "" : ", active");
|
2015-04-07 23:20:32 +08:00
|
|
|
rcu_read_unlock();
|
|
|
|
}
|
2015-04-27 20:41:22 +08:00
|
|
|
seq_printf(m, "Semaphore boosts: %d%s\n",
|
|
|
|
dev_priv->rps.semaphores.boosts,
|
|
|
|
list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
|
|
|
|
seq_printf(m, "MMIO flip boosts: %d%s\n",
|
|
|
|
dev_priv->rps.mmioflips.boosts,
|
|
|
|
list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
|
2015-04-07 23:20:32 +08:00
|
|
|
seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
|
2015-05-22 04:01:47 +08:00
|
|
|
spin_unlock(&dev_priv->rps.client_lock);
|
2016-04-27 01:29:41 +08:00
|
|
|
mutex_unlock(&dev->filelist_mutex);
|
2015-04-07 23:20:32 +08:00
|
|
|
|
2015-05-22 04:01:47 +08:00
|
|
|
return 0;
|
2015-04-07 23:20:32 +08:00
|
|
|
}
|
|
|
|
|
2013-07-05 02:02:07 +08:00
|
|
|
static int i915_llc(struct seq_file *m, void *data)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2013-07-05 02:02:07 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-04-13 22:26:43 +08:00
|
|
|
const bool edram = INTEL_GEN(dev_priv) > 8;
|
2013-07-05 02:02:07 +08:00
|
|
|
|
|
|
|
seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
|
2016-04-13 22:26:43 +08:00
|
|
|
seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
|
|
|
|
intel_uncore_edram_size(dev_priv)/1024/1024);
|
2013-07-05 02:02:07 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:37 +08:00
|
|
|
static int i915_guc_load_status_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
|
|
|
|
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
|
|
|
u32 tmp, i;
|
|
|
|
|
2016-04-07 16:08:05 +08:00
|
|
|
if (!HAS_GUC_UCODE(dev_priv))
|
2015-08-12 22:43:37 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
seq_printf(m, "GuC firmware status:\n");
|
|
|
|
seq_printf(m, "\tpath: %s\n",
|
|
|
|
guc_fw->guc_fw_path);
|
|
|
|
seq_printf(m, "\tfetch: %s\n",
|
|
|
|
intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
|
|
|
|
seq_printf(m, "\tload: %s\n",
|
|
|
|
intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
|
|
|
|
seq_printf(m, "\tversion wanted: %d.%d\n",
|
|
|
|
guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
|
|
|
|
seq_printf(m, "\tversion found: %d.%d\n",
|
|
|
|
guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
|
2015-10-20 07:10:54 +08:00
|
|
|
seq_printf(m, "\theader: offset is %d; size = %d\n",
|
|
|
|
guc_fw->header_offset, guc_fw->header_size);
|
|
|
|
seq_printf(m, "\tuCode: offset is %d; size = %d\n",
|
|
|
|
guc_fw->ucode_offset, guc_fw->ucode_size);
|
|
|
|
seq_printf(m, "\tRSA: offset is %d; size = %d\n",
|
|
|
|
guc_fw->rsa_offset, guc_fw->rsa_size);
|
2015-08-12 22:43:37 +08:00
|
|
|
|
|
|
|
tmp = I915_READ(GUC_STATUS);
|
|
|
|
|
|
|
|
seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
|
|
|
|
seq_printf(m, "\tBootrom status = 0x%x\n",
|
|
|
|
(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
|
|
|
|
seq_printf(m, "\tuKernel status = 0x%x\n",
|
|
|
|
(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
|
|
|
|
seq_printf(m, "\tMIA Core status = 0x%x\n",
|
|
|
|
(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
|
|
|
|
seq_puts(m, "\nScratch registers:\n");
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:44 +08:00
|
|
|
static void i915_guc_client_info(struct seq_file *m,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_guc_client *client)
|
|
|
|
{
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2015-08-12 22:43:44 +08:00
|
|
|
uint64_t tot = 0;
|
|
|
|
|
|
|
|
seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
|
|
|
|
client->priority, client->ctx_index, client->proc_desc_offset);
|
|
|
|
seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
|
|
|
|
client->doorbell_id, client->doorbell_offset, client->cookie);
|
|
|
|
seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
|
|
|
|
client->wq_size, client->wq_offset, client->wq_tail);
|
|
|
|
|
2016-05-13 22:36:33 +08:00
|
|
|
seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
|
2015-08-12 22:43:44 +08:00
|
|
|
seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
|
|
|
|
seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
|
|
|
|
seq_printf(m, "\tLast submission result: %d\n", client->retcode);
|
|
|
|
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2015-08-12 22:43:44 +08:00
|
|
|
seq_printf(m, "\tSubmissions: %llu %s\n",
|
2016-03-16 19:00:36 +08:00
|
|
|
client->submissions[engine->guc_id],
|
|
|
|
engine->name);
|
|
|
|
tot += client->submissions[engine->guc_id];
|
2015-08-12 22:43:44 +08:00
|
|
|
}
|
|
|
|
seq_printf(m, "\tTotal: %llu\n", tot);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_guc_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_guc guc;
|
2015-08-22 01:45:27 +08:00
|
|
|
struct i915_guc_client client = {};
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2015-08-12 22:43:44 +08:00
|
|
|
u64 total = 0;
|
|
|
|
|
2016-04-07 16:08:05 +08:00
|
|
|
if (!HAS_GUC_SCHED(dev_priv))
|
2015-08-12 22:43:44 +08:00
|
|
|
return 0;
|
|
|
|
|
2015-12-03 08:56:29 +08:00
|
|
|
if (mutex_lock_interruptible(&dev->struct_mutex))
|
|
|
|
return 0;
|
|
|
|
|
2015-08-12 22:43:44 +08:00
|
|
|
/* Take a local copy of the GuC data, so we can dump it at leisure */
|
|
|
|
guc = dev_priv->guc;
|
2015-12-03 08:56:29 +08:00
|
|
|
if (guc.execbuf_client)
|
2015-08-12 22:43:44 +08:00
|
|
|
client = *guc.execbuf_client;
|
2015-12-03 08:56:29 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
2015-08-12 22:43:44 +08:00
|
|
|
|
|
|
|
seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
|
|
|
|
seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
|
|
|
|
seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
|
|
|
|
seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
|
|
|
|
seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
|
|
|
|
|
|
|
|
seq_printf(m, "\nGuC submissions:\n");
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
2016-01-24 03:58:14 +08:00
|
|
|
seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
|
2016-03-16 19:00:36 +08:00
|
|
|
engine->name, guc.submissions[engine->guc_id],
|
|
|
|
guc.last_seqno[engine->guc_id]);
|
|
|
|
total += guc.submissions[engine->guc_id];
|
2015-08-12 22:43:44 +08:00
|
|
|
}
|
|
|
|
seq_printf(m, "\t%s: %llu\n", "Total", total);
|
|
|
|
|
|
|
|
seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
|
|
|
|
i915_guc_client_info(m, dev_priv, &client);
|
|
|
|
|
|
|
|
/* Add more as required ... */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-08-12 22:43:40 +08:00
|
|
|
static int i915_guc_log_dump(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
|
|
|
|
u32 *log;
|
|
|
|
int i = 0, pg;
|
|
|
|
|
|
|
|
if (!log_obj)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
|
|
|
|
log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
|
|
|
|
|
|
|
|
for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
|
|
|
|
seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
|
|
*(log + i), *(log + i + 1),
|
|
|
|
*(log + i + 2), *(log + i + 3));
|
|
|
|
|
|
|
|
kunmap_atomic(log);
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-07-12 05:44:59 +08:00
|
|
|
static int i915_edp_psr_status(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-04 03:15:06 +08:00
|
|
|
u32 psrperf = 0;
|
2014-11-15 00:52:40 +08:00
|
|
|
u32 stat[3];
|
|
|
|
enum pipe pipe;
|
2013-10-04 03:15:06 +08:00
|
|
|
bool enabled = false;
|
2013-07-12 05:44:59 +08:00
|
|
|
|
2015-03-09 22:17:58 +08:00
|
|
|
if (!HAS_PSR(dev)) {
|
|
|
|
seq_puts(m, "PSR not supported\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2014-07-12 01:30:17 +08:00
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
2013-10-04 03:15:06 +08:00
|
|
|
seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
|
|
|
|
seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
|
2014-07-12 01:30:11 +08:00
|
|
|
seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
|
2014-06-13 01:16:45 +08:00
|
|
|
seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
|
2014-07-12 01:30:17 +08:00
|
|
|
seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
|
|
|
|
dev_priv->psr.busy_frontbuffer_bits);
|
|
|
|
seq_printf(m, "Re-enable work scheduled: %s\n",
|
|
|
|
yesno(work_busy(&dev_priv->psr.work.work)));
|
2013-07-12 05:44:59 +08:00
|
|
|
|
2015-03-09 22:17:58 +08:00
|
|
|
if (HAS_DDI(dev))
|
2015-11-12 02:34:15 +08:00
|
|
|
enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
|
2015-03-09 22:17:58 +08:00
|
|
|
else {
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
|
|
stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
|
|
|
|
VLV_EDP_PSR_CURR_STATE_MASK;
|
|
|
|
if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
|
|
|
|
(stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
|
|
|
|
enabled = true;
|
2014-11-15 00:52:40 +08:00
|
|
|
}
|
|
|
|
}
|
2016-02-02 04:02:07 +08:00
|
|
|
|
|
|
|
seq_printf(m, "Main link in standby mode: %s\n",
|
|
|
|
yesno(dev_priv->psr.link_standby));
|
|
|
|
|
2014-11-15 00:52:40 +08:00
|
|
|
seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
|
|
|
|
|
|
|
|
if (!HAS_DDI(dev))
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
|
|
if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
|
|
|
|
(stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
|
|
|
|
seq_printf(m, " pipe %c", pipe_name(pipe));
|
|
|
|
}
|
|
|
|
seq_puts(m, "\n");
|
2013-07-12 05:44:59 +08:00
|
|
|
|
2015-11-24 06:16:40 +08:00
|
|
|
/*
|
|
|
|
* VLV/CHV PSR has no kind of performance counter
|
|
|
|
* SKL+ Perf counter is reset to 0 everytime DC state is entered
|
|
|
|
*/
|
|
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
|
2015-11-12 02:34:15 +08:00
|
|
|
psrperf = I915_READ(EDP_PSR_PERF_CNT) &
|
2013-10-04 03:15:06 +08:00
|
|
|
EDP_PSR_PERF_CNT_MASK;
|
2014-11-15 00:52:40 +08:00
|
|
|
|
|
|
|
seq_printf(m, "Performance_Counter: %u\n", psrperf);
|
|
|
|
}
|
2014-07-12 01:30:17 +08:00
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
2013-07-12 05:44:59 +08:00
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2013-07-12 05:44:59 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-01-24 23:36:17 +08:00
|
|
|
static int i915_sink_crc(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct intel_encoder *encoder;
|
|
|
|
struct intel_connector *connector;
|
|
|
|
struct intel_dp *intel_dp = NULL;
|
|
|
|
int ret;
|
|
|
|
u8 crc[6];
|
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
2015-03-14 07:13:59 +08:00
|
|
|
for_each_intel_connector(dev, connector) {
|
2014-01-24 23:36:17 +08:00
|
|
|
|
|
|
|
if (connector->base.dpms != DRM_MODE_DPMS_ON)
|
|
|
|
continue;
|
|
|
|
|
2014-02-14 03:51:33 +08:00
|
|
|
if (!connector->base.encoder)
|
|
|
|
continue;
|
|
|
|
|
2014-01-24 23:36:17 +08:00
|
|
|
encoder = to_intel_encoder(connector->base.encoder);
|
|
|
|
if (encoder->type != INTEL_OUTPUT_EDP)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
|
|
|
|
ret = intel_dp_sink_crc(intel_dp, crc);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
|
|
|
|
crc[0], crc[1], crc[2],
|
|
|
|
crc[3], crc[4], crc[5]);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
ret = -ENODEV;
|
|
|
|
out:
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-08-20 17:29:23 +08:00
|
|
|
static int i915_energy_uJ(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u64 power;
|
|
|
|
u32 units;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2013-08-20 17:29:23 +08:00
|
|
|
rdmsrl(MSR_RAPL_POWER_UNIT, power);
|
|
|
|
power = (power & 0x1f00) >> 8;
|
|
|
|
units = 1000000 / (1 << power); /* convert to uJ */
|
|
|
|
power = I915_READ(MCH_SECP_NRG_STTS);
|
|
|
|
power *= units;
|
|
|
|
|
2014-02-22 00:52:23 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2013-08-20 17:29:23 +08:00
|
|
|
seq_printf(m, "%llu", (long long unsigned)power);
|
2013-08-20 00:18:10 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-06-05 01:23:57 +08:00
|
|
|
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
|
2013-08-20 00:18:10 +08:00
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2013-08-20 00:18:10 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2016-04-03 21:14:21 +08:00
|
|
|
if (!HAS_RUNTIME_PM(dev_priv))
|
|
|
|
seq_puts(m, "Runtime power management not supported\n");
|
2013-08-20 00:18:10 +08:00
|
|
|
|
2014-02-22 00:52:24 +08:00
|
|
|
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
|
2013-08-20 00:18:10 +08:00
|
|
|
seq_printf(m, "IRQs disabled: %s\n",
|
2014-06-21 00:29:20 +08:00
|
|
|
yesno(!intel_irqs_enabled(dev_priv)));
|
2015-06-15 19:52:28 +08:00
|
|
|
#ifdef CONFIG_PM
|
2015-06-05 01:23:58 +08:00
|
|
|
seq_printf(m, "Usage count: %d\n",
|
|
|
|
atomic_read(&dev->dev->power.usage_count));
|
2015-06-15 19:52:28 +08:00
|
|
|
#else
|
|
|
|
seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
|
|
|
|
#endif
|
2016-04-03 21:14:21 +08:00
|
|
|
seq_printf(m, "PCI device power state: %s [%d]\n",
|
|
|
|
pci_power_name(dev_priv->dev->pdev->current_state),
|
|
|
|
dev_priv->dev->pdev->current_state);
|
2013-08-20 00:18:10 +08:00
|
|
|
|
2013-08-20 17:29:23 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-25 23:15:35 +08:00
|
|
|
static int i915_power_domain_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2013-11-25 23:15:35 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
|
|
|
|
seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
|
|
|
|
for (i = 0; i < power_domains->power_well_count; i++) {
|
|
|
|
struct i915_power_well *power_well;
|
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
|
|
|
|
|
power_well = &power_domains->power_wells[i];
|
|
|
|
seq_printf(m, "%-25s %d\n", power_well->name,
|
|
|
|
power_well->count);
|
|
|
|
|
|
|
|
for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
|
|
|
|
power_domain++) {
|
|
|
|
if (!(BIT(power_domain) & power_well->domains))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
seq_printf(m, " %-23s %d\n",
|
2015-11-20 23:55:33 +08:00
|
|
|
intel_display_power_domain_str(power_domain),
|
2013-11-25 23:15:35 +08:00
|
|
|
power_domains->domain_use_count[power_domain]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-27 20:47:01 +08:00
|
|
|
static int i915_dmc_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_csr *csr;
|
|
|
|
|
|
|
|
if (!HAS_CSR(dev)) {
|
|
|
|
seq_puts(m, "not supported\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
csr = &dev_priv->csr;
|
|
|
|
|
2015-10-30 23:54:47 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2015-10-27 20:47:01 +08:00
|
|
|
seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
|
|
|
|
seq_printf(m, "path: %s\n", csr->fw_path);
|
|
|
|
|
|
|
|
if (!csr->dmc_payload)
|
2015-10-30 23:54:47 +08:00
|
|
|
goto out;
|
2015-10-27 20:47:01 +08:00
|
|
|
|
|
|
|
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
|
|
|
|
CSR_VERSION_MINOR(csr->version));
|
|
|
|
|
2015-10-30 23:53:32 +08:00
|
|
|
if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
|
|
|
|
seq_printf(m, "DC3 -> DC5 count: %d\n",
|
|
|
|
I915_READ(SKL_CSR_DC3_DC5_COUNT));
|
|
|
|
seq_printf(m, "DC5 -> DC6 count: %d\n",
|
|
|
|
I915_READ(SKL_CSR_DC5_DC6_COUNT));
|
2015-10-27 20:47:03 +08:00
|
|
|
} else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
|
|
|
|
seq_printf(m, "DC3 -> DC5 count: %d\n",
|
|
|
|
I915_READ(BXT_CSR_DC3_DC5_COUNT));
|
2015-10-30 23:53:32 +08:00
|
|
|
}
|
|
|
|
|
2015-10-30 23:54:47 +08:00
|
|
|
out:
|
|
|
|
seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
|
|
|
|
seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
|
|
|
|
seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
|
|
|
|
|
2015-10-30 23:53:32 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2015-10-27 20:47:01 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-08 04:48:15 +08:00
|
|
|
static void intel_seq_print_mode(struct seq_file *m, int tabs,
|
|
|
|
struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < tabs; i++)
|
|
|
|
seq_putc(m, '\t');
|
|
|
|
|
|
|
|
seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
|
|
|
|
mode->base.id, mode->name,
|
|
|
|
mode->vrefresh, mode->clock,
|
|
|
|
mode->hdisplay, mode->hsync_start,
|
|
|
|
mode->hsync_end, mode->htotal,
|
|
|
|
mode->vdisplay, mode->vsync_start,
|
|
|
|
mode->vsync_end, mode->vtotal,
|
|
|
|
mode->type, mode->flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_encoder_info(struct seq_file *m,
|
|
|
|
struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_encoder *intel_encoder)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2014-02-08 04:48:15 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
|
|
|
|
encoder = &intel_encoder->base;
|
|
|
|
seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
|
2014-06-03 19:56:21 +08:00
|
|
|
encoder->base.id, encoder->name);
|
2014-02-08 04:48:15 +08:00
|
|
|
for_each_connector_on_encoder(dev, encoder, intel_connector) {
|
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
|
|
|
|
connector->base.id,
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->name,
|
2014-02-08 04:48:15 +08:00
|
|
|
drm_get_connector_status_name(connector->status));
|
|
|
|
if (connector->status == connector_status_connected) {
|
|
|
|
struct drm_display_mode *mode = &crtc->mode;
|
|
|
|
seq_printf(m, ", mode:\n");
|
|
|
|
intel_seq_print_mode(m, 2, mode);
|
|
|
|
} else {
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2014-02-08 04:48:15 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
|
struct intel_encoder *intel_encoder;
|
2015-09-10 22:07:57 +08:00
|
|
|
struct drm_plane_state *plane_state = crtc->primary->state;
|
|
|
|
struct drm_framebuffer *fb = plane_state->fb;
|
2014-02-08 04:48:15 +08:00
|
|
|
|
2015-09-10 22:07:57 +08:00
|
|
|
if (fb)
|
2014-06-17 01:12:55 +08:00
|
|
|
seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
|
2015-09-10 22:07:57 +08:00
|
|
|
fb->base.id, plane_state->src_x >> 16,
|
|
|
|
plane_state->src_y >> 16, fb->width, fb->height);
|
2014-06-17 01:12:55 +08:00
|
|
|
else
|
|
|
|
seq_puts(m, "\tprimary plane disabled\n");
|
2014-02-08 04:48:15 +08:00
|
|
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder)
|
|
|
|
intel_encoder_info(m, intel_crtc, intel_encoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
|
|
|
|
{
|
|
|
|
struct drm_display_mode *mode = panel->fixed_mode;
|
|
|
|
|
|
|
|
seq_printf(m, "\tfixed mode:\n");
|
|
|
|
intel_seq_print_mode(m, 2, mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_dp_info(struct seq_file *m,
|
|
|
|
struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
struct intel_encoder *intel_encoder = intel_connector->encoder;
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
|
|
|
|
|
|
|
seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
|
2015-09-03 16:16:09 +08:00
|
|
|
seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
|
2014-02-08 04:48:15 +08:00
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_EDP)
|
|
|
|
intel_panel_info(m, &intel_connector->panel);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_hdmi_info(struct seq_file *m,
|
|
|
|
struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
struct intel_encoder *intel_encoder = intel_connector->encoder;
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
|
|
|
|
|
2015-09-03 16:16:09 +08:00
|
|
|
seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
|
2014-02-08 04:48:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_lvds_info(struct seq_file *m,
|
|
|
|
struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
intel_panel_info(m, &intel_connector->panel);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_connector_info(struct seq_file *m,
|
|
|
|
struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
struct intel_encoder *intel_encoder = intel_connector->encoder;
|
2014-02-21 04:39:57 +08:00
|
|
|
struct drm_display_mode *mode;
|
2014-02-08 04:48:15 +08:00
|
|
|
|
|
|
|
seq_printf(m, "connector %d: type %s, status: %s\n",
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->base.id, connector->name,
|
2014-02-08 04:48:15 +08:00
|
|
|
drm_get_connector_status_name(connector->status));
|
|
|
|
if (connector->status == connector_status_connected) {
|
|
|
|
seq_printf(m, "\tname: %s\n", connector->display_info.name);
|
|
|
|
seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
|
|
|
|
connector->display_info.width_mm,
|
|
|
|
connector->display_info.height_mm);
|
|
|
|
seq_printf(m, "\tsubpixel order: %s\n",
|
|
|
|
drm_get_subpixel_order_name(connector->display_info.subpixel_order));
|
|
|
|
seq_printf(m, "\tCEA rev: %d\n",
|
|
|
|
connector->display_info.cea_rev);
|
|
|
|
}
|
2014-05-02 11:44:18 +08:00
|
|
|
if (intel_encoder) {
|
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
|
|
|
|
intel_encoder->type == INTEL_OUTPUT_EDP)
|
|
|
|
intel_dp_info(m, intel_connector);
|
|
|
|
else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
|
|
|
|
intel_hdmi_info(m, intel_connector);
|
|
|
|
else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
|
|
|
|
intel_lvds_info(m, intel_connector);
|
|
|
|
}
|
2014-02-08 04:48:15 +08:00
|
|
|
|
2014-02-21 04:39:57 +08:00
|
|
|
seq_printf(m, "\tmodes:\n");
|
|
|
|
list_for_each_entry(mode, &connector->modes, head)
|
|
|
|
intel_seq_print_mode(m, 2, mode);
|
2014-02-08 04:48:15 +08:00
|
|
|
}
|
|
|
|
|
2014-03-12 17:13:13 +08:00
|
|
|
static bool cursor_active(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 state;
|
|
|
|
|
|
|
|
if (IS_845G(dev) || IS_I865G(dev))
|
2015-09-23 00:47:51 +08:00
|
|
|
state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
|
2014-03-12 17:13:13 +08:00
|
|
|
else
|
2014-04-09 18:28:53 +08:00
|
|
|
state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
|
2014-03-12 17:13:13 +08:00
|
|
|
|
|
|
|
return state;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pos;
|
|
|
|
|
2014-04-09 18:28:53 +08:00
|
|
|
pos = I915_READ(CURPOS(pipe));
|
2014-03-12 17:13:13 +08:00
|
|
|
|
|
|
|
*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
|
|
|
|
if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
|
|
|
|
*x = -*x;
|
|
|
|
|
|
|
|
*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
|
|
|
|
if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
|
|
|
|
*y = -*y;
|
|
|
|
|
|
|
|
return cursor_active(dev, pipe);
|
|
|
|
}
|
|
|
|
|
2015-10-27 23:58:32 +08:00
|
|
|
static const char *plane_type(enum drm_plane_type type)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case DRM_PLANE_TYPE_OVERLAY:
|
|
|
|
return "OVL";
|
|
|
|
case DRM_PLANE_TYPE_PRIMARY:
|
|
|
|
return "PRI";
|
|
|
|
case DRM_PLANE_TYPE_CURSOR:
|
|
|
|
return "CUR";
|
|
|
|
/*
|
|
|
|
* Deliberately omitting default: to generate compiler warnings
|
|
|
|
* when a new drm_plane_type gets added.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
return "unknown";
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *plane_rotation(unsigned int rotation)
|
|
|
|
{
|
|
|
|
static char buf[48];
|
|
|
|
/*
|
|
|
|
* According to doc only one DRM_ROTATE_ is allowed but this
|
|
|
|
* will print them all to visualize if the values are misused
|
|
|
|
*/
|
|
|
|
snprintf(buf, sizeof(buf),
|
|
|
|
"%s%s%s%s%s%s(0x%08x)",
|
|
|
|
(rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
|
|
|
|
(rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
|
|
|
|
(rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
|
|
|
|
(rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
|
|
|
|
(rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
|
|
|
|
(rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
|
|
|
|
rotation);
|
|
|
|
|
|
|
|
return buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct intel_plane *intel_plane;
|
|
|
|
|
|
|
|
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
|
|
|
|
struct drm_plane_state *state;
|
|
|
|
struct drm_plane *plane = &intel_plane->base;
|
|
|
|
|
|
|
|
if (!plane->state) {
|
|
|
|
seq_puts(m, "plane->state is NULL!\n");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
state = plane->state;
|
|
|
|
|
|
|
|
seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
|
|
|
|
plane->base.id,
|
|
|
|
plane_type(intel_plane->base.type),
|
|
|
|
state->crtc_x, state->crtc_y,
|
|
|
|
state->crtc_w, state->crtc_h,
|
|
|
|
(state->src_x >> 16),
|
|
|
|
((state->src_x & 0xffff) * 15625) >> 10,
|
|
|
|
(state->src_y >> 16),
|
|
|
|
((state->src_y & 0xffff) * 15625) >> 10,
|
|
|
|
(state->src_w >> 16),
|
|
|
|
((state->src_w & 0xffff) * 15625) >> 10,
|
|
|
|
(state->src_h >> 16),
|
|
|
|
((state->src_h & 0xffff) * 15625) >> 10,
|
|
|
|
state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
|
|
|
|
plane_rotation(state->rotation));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
|
|
|
|
{
|
|
|
|
struct intel_crtc_state *pipe_config;
|
|
|
|
int num_scalers = intel_crtc->num_scalers;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
pipe_config = to_intel_crtc_state(intel_crtc->base.state);
|
|
|
|
|
|
|
|
/* Not all platformas have a scaler */
|
|
|
|
if (num_scalers) {
|
|
|
|
seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
|
|
|
|
num_scalers,
|
|
|
|
pipe_config->scaler_state.scaler_users,
|
|
|
|
pipe_config->scaler_state.scaler_id);
|
|
|
|
|
|
|
|
for (i = 0; i < SKL_NUM_SCALERS; i++) {
|
|
|
|
struct intel_scaler *sc =
|
|
|
|
&pipe_config->scaler_state.scalers[i];
|
|
|
|
|
|
|
|
seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
|
|
|
|
i, yesno(sc->in_use), sc->mode);
|
|
|
|
}
|
|
|
|
seq_puts(m, "\n");
|
|
|
|
} else {
|
|
|
|
seq_puts(m, "\tNo scalers available on this platform\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-02-08 04:48:15 +08:00
|
|
|
static int i915_display_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
2014-05-13 22:30:28 +08:00
|
|
|
struct drm_info_node *node = m->private;
|
2014-02-08 04:48:15 +08:00
|
|
|
struct drm_device *dev = node->minor->dev;
|
2014-04-02 01:55:10 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-12 17:13:13 +08:00
|
|
|
struct intel_crtc *crtc;
|
2014-02-08 04:48:15 +08:00
|
|
|
struct drm_connector *connector;
|
|
|
|
|
2014-04-02 01:55:10 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2014-02-08 04:48:15 +08:00
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
seq_printf(m, "CRTC info\n");
|
|
|
|
seq_printf(m, "---------\n");
|
2014-05-14 06:32:22 +08:00
|
|
|
for_each_intel_crtc(dev, crtc) {
|
2014-03-12 17:13:13 +08:00
|
|
|
bool active;
|
2015-06-01 18:50:08 +08:00
|
|
|
struct intel_crtc_state *pipe_config;
|
2014-03-12 17:13:13 +08:00
|
|
|
int x, y;
|
2014-02-08 04:48:15 +08:00
|
|
|
|
2015-06-01 18:50:08 +08:00
|
|
|
pipe_config = to_intel_crtc_state(crtc->base.state);
|
|
|
|
|
2015-10-27 23:58:32 +08:00
|
|
|
seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
|
2014-03-12 17:13:13 +08:00
|
|
|
crtc->base.base.id, pipe_name(crtc->pipe),
|
2015-06-01 18:50:08 +08:00
|
|
|
yesno(pipe_config->base.active),
|
2015-10-27 23:58:32 +08:00
|
|
|
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
|
|
|
|
yesno(pipe_config->dither), pipe_config->pipe_bpp);
|
|
|
|
|
2015-06-01 18:50:08 +08:00
|
|
|
if (pipe_config->base.active) {
|
2014-03-12 17:13:13 +08:00
|
|
|
intel_crtc_info(m, crtc);
|
|
|
|
|
2014-04-02 01:55:11 +08:00
|
|
|
active = cursor_position(dev, crtc->pipe, &x, &y);
|
2014-07-04 15:20:11 +08:00
|
|
|
seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
|
2014-05-30 21:35:26 +08:00
|
|
|
yesno(crtc->cursor_base),
|
2015-02-28 02:12:00 +08:00
|
|
|
x, y, crtc->base.cursor->state->crtc_w,
|
|
|
|
crtc->base.cursor->state->crtc_h,
|
2014-07-04 15:20:11 +08:00
|
|
|
crtc->cursor_addr, yesno(active));
|
2015-10-27 23:58:32 +08:00
|
|
|
intel_scaler_info(m, crtc);
|
|
|
|
intel_plane_info(m, crtc);
|
2014-04-02 01:55:11 +08:00
|
|
|
}
|
2014-05-22 23:56:31 +08:00
|
|
|
|
|
|
|
seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
|
|
|
|
yesno(!crtc->cpu_fifo_underrun_disabled),
|
|
|
|
yesno(!crtc->pch_fifo_underrun_disabled));
|
2014-02-08 04:48:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(m, "\n");
|
|
|
|
seq_printf(m, "Connector info\n");
|
|
|
|
seq_printf(m, "--------------\n");
|
|
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
|
|
intel_connector_info(m, connector);
|
|
|
|
}
|
|
|
|
drm_modeset_unlock_all(dev);
|
2014-04-02 01:55:10 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2014-02-08 04:48:15 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-01 00:53:42 +08:00
|
|
|
static int i915_semaphore_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2014-07-01 00:53:42 +08:00
|
|
|
int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
|
2016-03-24 02:19:53 +08:00
|
|
|
enum intel_engine_id id;
|
|
|
|
int j, ret;
|
2014-07-01 00:53:42 +08:00
|
|
|
|
2016-05-06 22:40:21 +08:00
|
|
|
if (!i915_semaphore_is_enabled(dev_priv)) {
|
2014-07-01 00:53:42 +08:00
|
|
|
seq_puts(m, "Semaphores are disabled\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-07-10 01:31:57 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2014-07-01 00:53:42 +08:00
|
|
|
|
|
|
|
if (IS_BROADWELL(dev)) {
|
|
|
|
struct page *page;
|
|
|
|
uint64_t *seqno;
|
|
|
|
|
|
|
|
page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
|
|
|
|
|
|
|
|
seqno = (uint64_t *)kmap_atomic(page);
|
2016-03-24 02:19:53 +08:00
|
|
|
for_each_engine_id(engine, dev_priv, id) {
|
2014-07-01 00:53:42 +08:00
|
|
|
uint64_t offset;
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, "%s\n", engine->name);
|
2014-07-01 00:53:42 +08:00
|
|
|
|
|
|
|
seq_puts(m, " Last signal:");
|
|
|
|
for (j = 0; j < num_rings; j++) {
|
2016-03-24 02:19:53 +08:00
|
|
|
offset = id * I915_NUM_ENGINES + j;
|
2014-07-01 00:53:42 +08:00
|
|
|
seq_printf(m, "0x%08llx (0x%02llx) ",
|
|
|
|
seqno[offset], offset * 8);
|
|
|
|
}
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
|
|
|
|
seq_puts(m, " Last wait: ");
|
|
|
|
for (j = 0; j < num_rings; j++) {
|
2016-03-24 02:19:53 +08:00
|
|
|
offset = id + (j * I915_NUM_ENGINES);
|
2014-07-01 00:53:42 +08:00
|
|
|
seq_printf(m, "0x%08llx (0x%02llx) ",
|
|
|
|
seqno[offset], offset * 8);
|
|
|
|
}
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
|
|
|
|
}
|
|
|
|
kunmap_atomic(seqno);
|
|
|
|
} else {
|
|
|
|
seq_puts(m, " Last signal:");
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv)
|
2014-07-01 00:53:42 +08:00
|
|
|
for (j = 0; j < num_rings; j++)
|
|
|
|
seq_printf(m, "0x%08x\n",
|
2016-03-16 19:00:36 +08:00
|
|
|
I915_READ(engine->semaphore.mbox.signal[j]));
|
2014-07-01 00:53:42 +08:00
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_puts(m, "\nSync seqno:\n");
|
2016-03-24 19:20:38 +08:00
|
|
|
for_each_engine(engine, dev_priv) {
|
|
|
|
for (j = 0; j < num_rings; j++)
|
2016-03-16 19:00:36 +08:00
|
|
|
seq_printf(m, " 0x%08x ",
|
|
|
|
engine->semaphore.sync_seqno[j]);
|
2014-07-01 00:53:42 +08:00
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
seq_putc(m, '\n');
|
|
|
|
|
2014-07-10 01:31:57 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2014-07-01 00:53:42 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-06-26 03:01:53 +08:00
|
|
|
static int i915_shared_dplls_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
|
|
|
|
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
|
|
|
|
|
|
|
|
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
|
2016-03-14 16:27:52 +08:00
|
|
|
seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
|
|
|
|
pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
|
2014-06-26 03:01:53 +08:00
|
|
|
seq_printf(m, " tracked hardware state:\n");
|
2014-10-29 17:32:32 +08:00
|
|
|
seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
|
|
|
|
seq_printf(m, " dpll_md: 0x%08x\n",
|
|
|
|
pll->config.hw_state.dpll_md);
|
|
|
|
seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
|
|
|
|
seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
|
|
|
|
seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
|
2014-06-26 03:01:53 +08:00
|
|
|
}
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-30 23:50:59 +08:00
|
|
|
static int i915_wa_registers(struct seq_file *m, void *unused)
|
2014-08-26 21:44:51 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int ret;
|
2016-03-16 19:00:36 +08:00
|
|
|
struct intel_engine_cs *engine;
|
2014-08-26 21:44:51 +08:00
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2016-01-22 05:43:47 +08:00
|
|
|
struct i915_workarounds *workarounds = &dev_priv->workarounds;
|
2016-03-24 02:19:53 +08:00
|
|
|
enum intel_engine_id id;
|
2014-08-26 21:44:51 +08:00
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2016-01-22 05:43:47 +08:00
|
|
|
seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
|
2016-03-24 02:19:53 +08:00
|
|
|
for_each_engine_id(engine, dev_priv, id)
|
2016-01-22 05:43:47 +08:00
|
|
|
seq_printf(m, "HW whitelist count for %s: %d\n",
|
2016-03-24 02:19:53 +08:00
|
|
|
engine->name, workarounds->hw_whitelist_count[id]);
|
2016-01-22 05:43:47 +08:00
|
|
|
for (i = 0; i < workarounds->count; ++i) {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 21:33:26 +08:00
|
|
|
i915_reg_t addr;
|
|
|
|
u32 mask, value, read;
|
2014-10-07 22:21:27 +08:00
|
|
|
bool ok;
|
2014-08-26 21:44:51 +08:00
|
|
|
|
2016-01-22 05:43:47 +08:00
|
|
|
addr = workarounds->reg[i].addr;
|
|
|
|
mask = workarounds->reg[i].mask;
|
|
|
|
value = workarounds->reg[i].value;
|
2014-10-07 22:21:27 +08:00
|
|
|
read = I915_READ(addr);
|
|
|
|
ok = (value & mask) == (read & mask);
|
|
|
|
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 21:33:26 +08:00
|
|
|
i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
|
2014-08-26 21:44:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-11-05 01:06:51 +08:00
|
|
|
static int i915_ddb_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct skl_ddb_allocation *ddb;
|
|
|
|
struct skl_ddb_entry *entry;
|
|
|
|
enum pipe pipe;
|
|
|
|
int plane;
|
|
|
|
|
2014-12-04 01:33:24 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 9)
|
|
|
|
return 0;
|
|
|
|
|
2014-11-05 01:06:51 +08:00
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
|
|
|
|
ddb = &dev_priv->wm.skl_hw.ddb;
|
|
|
|
|
|
|
|
seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
|
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
|
|
seq_printf(m, "Pipe %c\n", pipe_name(pipe));
|
|
|
|
|
2015-02-28 22:54:08 +08:00
|
|
|
for_each_plane(dev_priv, pipe, plane) {
|
2014-11-05 01:06:51 +08:00
|
|
|
entry = &ddb->plane[pipe][plane];
|
|
|
|
seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
|
|
|
|
entry->start, entry->end,
|
|
|
|
skl_ddb_entry_size(entry));
|
|
|
|
}
|
|
|
|
|
2015-09-25 06:53:10 +08:00
|
|
|
entry = &ddb->plane[pipe][PLANE_CURSOR];
|
2014-11-05 01:06:51 +08:00
|
|
|
seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
|
|
|
|
entry->end, skl_ddb_entry_size(entry));
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/i915: Add debugfs entry for DRRS
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
V5: [By Ram]: Rephrased to make it easy to understand.
And format is modified. [Rodrigo]
V6: [By Ram]: Modeset mutex are acquired for each crtc along with
renaming the Idleness detection states [Daniel]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: dump full busy_frontbuffer_bits and remove the dubios
computed logical state of DRRS - debugfs is about what is fact,
developers should reach their own conclusion when debugging issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-03-03 23:23:10 +08:00
|
|
|
static void drrs_status_per_crtc(struct seq_file *m,
|
|
|
|
struct drm_device *dev, struct intel_crtc *intel_crtc)
|
|
|
|
{
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct i915_drrs *drrs = &dev_priv->drrs;
|
|
|
|
int vrefresh = 0;
|
|
|
|
|
|
|
|
for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
|
|
|
|
/* Encoder connected on this CRTC */
|
|
|
|
switch (intel_encoder->type) {
|
|
|
|
case INTEL_OUTPUT_EDP:
|
|
|
|
seq_puts(m, "eDP:\n");
|
|
|
|
break;
|
|
|
|
case INTEL_OUTPUT_DSI:
|
|
|
|
seq_puts(m, "DSI:\n");
|
|
|
|
break;
|
|
|
|
case INTEL_OUTPUT_HDMI:
|
|
|
|
seq_puts(m, "HDMI:\n");
|
|
|
|
break;
|
|
|
|
case INTEL_OUTPUT_DISPLAYPORT:
|
|
|
|
seq_puts(m, "DP:\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
seq_printf(m, "Other encoder (id=%d).\n",
|
|
|
|
intel_encoder->type);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
|
|
|
|
seq_puts(m, "\tVBT: DRRS_type: Static");
|
|
|
|
else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
|
|
|
|
seq_puts(m, "\tVBT: DRRS_type: Seamless");
|
|
|
|
else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
|
|
|
|
seq_puts(m, "\tVBT: DRRS_type: None");
|
|
|
|
else
|
|
|
|
seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
|
|
|
|
|
|
|
|
seq_puts(m, "\n\n");
|
|
|
|
|
2015-06-01 18:50:08 +08:00
|
|
|
if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
|
drm/i915: Add debugfs entry for DRRS
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
V5: [By Ram]: Rephrased to make it easy to understand.
And format is modified. [Rodrigo]
V6: [By Ram]: Modeset mutex are acquired for each crtc along with
renaming the Idleness detection states [Daniel]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: dump full busy_frontbuffer_bits and remove the dubios
computed logical state of DRRS - debugfs is about what is fact,
developers should reach their own conclusion when debugging issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-03-03 23:23:10 +08:00
|
|
|
struct intel_panel *panel;
|
|
|
|
|
|
|
|
mutex_lock(&drrs->mutex);
|
|
|
|
/* DRRS Supported */
|
|
|
|
seq_puts(m, "\tDRRS Supported: Yes\n");
|
|
|
|
|
|
|
|
/* disable_drrs() will make drrs->dp NULL */
|
|
|
|
if (!drrs->dp) {
|
|
|
|
seq_puts(m, "Idleness DRRS: Disabled");
|
|
|
|
mutex_unlock(&drrs->mutex);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
panel = &drrs->dp->attached_connector->panel;
|
|
|
|
seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
|
|
|
|
drrs->busy_frontbuffer_bits);
|
|
|
|
|
|
|
|
seq_puts(m, "\n\t\t");
|
|
|
|
if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
|
|
|
|
seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
|
|
|
|
vrefresh = panel->fixed_mode->vrefresh;
|
|
|
|
} else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
|
|
|
|
seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
|
|
|
|
vrefresh = panel->downclock_mode->vrefresh;
|
|
|
|
} else {
|
|
|
|
seq_printf(m, "DRRS_State: Unknown(%d)\n",
|
|
|
|
drrs->refresh_rate_type);
|
|
|
|
mutex_unlock(&drrs->mutex);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
seq_printf(m, "\t\tVrefresh: %d", vrefresh);
|
|
|
|
|
|
|
|
seq_puts(m, "\n\t\t");
|
|
|
|
mutex_unlock(&drrs->mutex);
|
|
|
|
} else {
|
|
|
|
/* DRRS not supported. Print the VBT parameter*/
|
|
|
|
seq_puts(m, "\tDRRS Supported : No");
|
|
|
|
}
|
|
|
|
seq_puts(m, "\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_drrs_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct intel_crtc *intel_crtc;
|
|
|
|
int active_crtc_cnt = 0;
|
|
|
|
|
|
|
|
for_each_intel_crtc(dev, intel_crtc) {
|
|
|
|
drm_modeset_lock(&intel_crtc->base.mutex, NULL);
|
|
|
|
|
2015-06-01 18:50:08 +08:00
|
|
|
if (intel_crtc->base.state->active) {
|
drm/i915: Add debugfs entry for DRRS
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
V5: [By Ram]: Rephrased to make it easy to understand.
And format is modified. [Rodrigo]
V6: [By Ram]: Modeset mutex are acquired for each crtc along with
renaming the Idleness detection states [Daniel]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: dump full busy_frontbuffer_bits and remove the dubios
computed logical state of DRRS - debugfs is about what is fact,
developers should reach their own conclusion when debugging issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-03-03 23:23:10 +08:00
|
|
|
active_crtc_cnt++;
|
|
|
|
seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
|
|
|
|
|
|
|
|
drrs_status_per_crtc(m, dev, intel_crtc);
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_modeset_unlock(&intel_crtc->base.mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!active_crtc_cnt)
|
|
|
|
seq_puts(m, "No active crtc found\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
struct pipe_crc_info {
|
|
|
|
const char *name;
|
|
|
|
struct drm_device *dev;
|
|
|
|
enum pipe pipe;
|
|
|
|
};
|
|
|
|
|
2014-05-12 13:22:27 +08:00
|
|
|
static int i915_dp_mst_info(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
|
|
intel_encoder = to_intel_encoder(encoder);
|
|
|
|
if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
|
|
|
|
continue;
|
|
|
|
intel_dig_port = enc_to_dig_port(encoder);
|
|
|
|
if (!intel_dig_port->dp.can_mst)
|
|
|
|
continue;
|
2016-04-15 01:18:37 +08:00
|
|
|
seq_printf(m, "MST Source Port %c\n",
|
|
|
|
port_name(intel_dig_port->port));
|
2014-05-12 13:22:27 +08:00
|
|
|
drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
|
|
|
|
}
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
|
|
|
|
{
|
2013-10-16 01:55:41 +08:00
|
|
|
struct pipe_crc_info *info = inode->i_private;
|
|
|
|
struct drm_i915_private *dev_priv = info->dev->dev_private;
|
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
|
|
|
|
|
2013-11-14 18:30:43 +08:00
|
|
|
if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
|
|
|
|
|
|
if (pipe_crc->opened) {
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
2013-10-16 01:55:41 +08:00
|
|
|
return -EBUSY; /* already open */
|
|
|
|
}
|
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
pipe_crc->opened = true;
|
2013-10-16 01:55:40 +08:00
|
|
|
filep->private_data = inode->i_private;
|
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
|
|
|
|
{
|
2013-10-16 01:55:41 +08:00
|
|
|
struct pipe_crc_info *info = inode->i_private;
|
|
|
|
struct drm_i915_private *dev_priv = info->dev->dev_private;
|
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
|
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
|
|
pipe_crc->opened = false;
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
2013-10-16 01:55:41 +08:00
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* (6 fields, 8 chars each, space separated (5) + '\n') */
|
|
|
|
#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
|
|
|
|
/* account for \'0' */
|
|
|
|
#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
|
|
|
|
|
|
|
|
static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
|
2013-10-16 01:55:27 +08:00
|
|
|
{
|
2013-10-21 21:29:30 +08:00
|
|
|
assert_spin_locked(&pipe_crc->lock);
|
|
|
|
return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
|
|
|
|
INTEL_PIPE_CRC_ENTRIES_NR);
|
2013-10-16 01:55:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t
|
|
|
|
i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
|
|
|
|
loff_t *pos)
|
|
|
|
{
|
|
|
|
struct pipe_crc_info *info = filep->private_data;
|
|
|
|
struct drm_device *dev = info->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
|
|
|
|
char buf[PIPE_CRC_BUFFER_LEN];
|
2014-12-10 03:28:32 +08:00
|
|
|
int n_entries;
|
2013-10-16 01:55:40 +08:00
|
|
|
ssize_t bytes_read;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't allow user space to provide buffers not big enough to hold
|
|
|
|
* a line of data.
|
|
|
|
*/
|
|
|
|
if (count < PIPE_CRC_LINE_LEN)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
|
2013-10-16 01:55:27 +08:00
|
|
|
return 0;
|
2013-10-16 01:55:40 +08:00
|
|
|
|
|
|
|
/* nothing to read */
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
2013-10-16 01:55:40 +08:00
|
|
|
while (pipe_crc_data_count(pipe_crc) == 0) {
|
2013-10-21 21:29:30 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (filep->f_flags & O_NONBLOCK) {
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
2013-10-16 01:55:40 +08:00
|
|
|
return -EAGAIN;
|
2013-10-21 21:29:30 +08:00
|
|
|
}
|
2013-10-16 01:55:40 +08:00
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
|
|
|
|
pipe_crc_data_count(pipe_crc), pipe_crc->lock);
|
|
|
|
if (ret) {
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
return ret;
|
|
|
|
}
|
2013-10-16 01:55:27 +08:00
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
/* We now have one or more entries to read */
|
2014-12-10 03:28:32 +08:00
|
|
|
n_entries = count / PIPE_CRC_LINE_LEN;
|
2013-10-21 21:29:30 +08:00
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
bytes_read = 0;
|
2014-12-10 03:28:32 +08:00
|
|
|
while (n_entries > 0) {
|
|
|
|
struct intel_pipe_crc_entry *entry =
|
|
|
|
&pipe_crc->entries[pipe_crc->tail];
|
2013-10-16 01:55:40 +08:00
|
|
|
int ret;
|
2013-10-16 01:55:27 +08:00
|
|
|
|
2014-12-10 03:28:32 +08:00
|
|
|
if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
|
|
|
|
INTEL_PIPE_CRC_ENTRIES_NR) < 1)
|
|
|
|
break;
|
|
|
|
|
|
|
|
BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
|
|
|
|
pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
|
|
|
|
"%8u %8x %8x %8x %8x %8x\n",
|
|
|
|
entry->frame, entry->crc[0],
|
|
|
|
entry->crc[1], entry->crc[2],
|
|
|
|
entry->crc[3], entry->crc[4]);
|
|
|
|
|
2014-12-10 03:28:32 +08:00
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
|
|
|
|
ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
|
2013-10-16 01:55:40 +08:00
|
|
|
if (ret == PIPE_CRC_LINE_LEN)
|
|
|
|
return -EFAULT;
|
2013-10-16 01:55:29 +08:00
|
|
|
|
2014-12-10 03:28:32 +08:00
|
|
|
user_buf += PIPE_CRC_LINE_LEN;
|
|
|
|
n_entries--;
|
|
|
|
|
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
|
|
}
|
2013-10-16 01:55:27 +08:00
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
return bytes_read;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_pipe_crc_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_pipe_crc_open,
|
|
|
|
.read = i915_pipe_crc_read,
|
|
|
|
.release = i915_pipe_crc_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
|
|
|
|
{
|
|
|
|
.name = "i915_pipe_A_crc",
|
|
|
|
.pipe = PIPE_A,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "i915_pipe_B_crc",
|
|
|
|
.pipe = PIPE_B,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "i915_pipe_C_crc",
|
|
|
|
.pipe = PIPE_C,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
|
|
|
|
enum pipe pipe)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = minor->dev;
|
|
|
|
struct dentry *ent;
|
|
|
|
struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
|
|
|
|
|
|
|
|
info->dev = dev;
|
|
|
|
ent = debugfs_create_file(info->name, S_IRUGO, root, info,
|
|
|
|
&i915_pipe_crc_fops);
|
2013-12-16 14:13:25 +08:00
|
|
|
if (!ent)
|
|
|
|
return -ENOMEM;
|
2013-10-16 01:55:40 +08:00
|
|
|
|
|
|
|
return drm_add_fake_info_node(minor, ent, info);
|
2013-10-16 01:55:27 +08:00
|
|
|
}
|
|
|
|
|
2013-10-16 17:51:54 +08:00
|
|
|
static const char * const pipe_crc_sources[] = {
|
2013-10-16 19:30:34 +08:00
|
|
|
"none",
|
|
|
|
"plane1",
|
|
|
|
"plane2",
|
|
|
|
"pf",
|
2013-10-17 04:55:48 +08:00
|
|
|
"pipe",
|
2013-10-17 04:55:58 +08:00
|
|
|
"TV",
|
|
|
|
"DP-B",
|
|
|
|
"DP-C",
|
|
|
|
"DP-D",
|
2013-11-01 17:50:20 +08:00
|
|
|
"auto",
|
2013-10-16 19:30:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
|
|
|
|
{
|
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
|
|
|
|
return pipe_crc_sources[source];
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
static int display_crc_ctl_show(struct seq_file *m, void *data)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < I915_MAX_PIPES; i++)
|
|
|
|
seq_printf(m, "%c %s\n", pipe_name(i),
|
|
|
|
pipe_crc_source_name(dev_priv->pipe_crc[i].source));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
static int display_crc_ctl_open(struct inode *inode, struct file *file)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
return single_open(file, display_crc_ctl_show, dev);
|
2013-10-16 19:30:34 +08:00
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:20 +08:00
|
|
|
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
|
2013-10-21 23:26:38 +08:00
|
|
|
uint32_t *val)
|
|
|
|
{
|
2013-11-01 17:50:20 +08:00
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
|
|
|
|
|
|
|
|
switch (*source) {
|
2013-10-21 23:26:38 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
|
|
*val = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:20 +08:00
|
|
|
static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
|
|
|
|
enum intel_pipe_crc_source *source)
|
|
|
|
{
|
|
|
|
struct intel_encoder *encoder;
|
|
|
|
struct intel_crtc *crtc;
|
2013-11-01 17:50:23 +08:00
|
|
|
struct intel_digital_port *dig_port;
|
2013-11-01 17:50:20 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
|
|
|
|
|
drm: Split connection_mutex out of mode_config.mutex (v3)
After the split-out of crtc locks from the big mode_config.mutex
there's still two major areas it protects:
- Various connector probe states, like connector->status, EDID
properties, probed mode lists and similar information.
- The links from connector->encoder and encoder->crtc and other
modeset-relevant connector state (e.g. properties which control the
panel fitter).
The later is used by modeset operations. But they don't really care
about the former since it's allowed to e.g. enable a disconnected VGA
output or with a mode not in the probed list.
Thus far this hasn't been a problem, but for the atomic modeset
conversion Rob Clark needs to convert all modeset relevant locks into
w/w locks. This is required because the order of acquisition is
determined by how userspace supplies the atomic modeset data. This has
run into troubles in the detect path since the i915 load detect code
needs _both_ protections offered by the mode_config.mutex: It updates
probe state and it needs to change the modeset configuration to enable
the temporary load detect pipe.
The big deal here is that for the probe/detect users of this lock a
plain mutex fits best, but for atomic modesets we really want a w/w
mutex. To fix this lets split out a new connection_mutex lock for the
modeset relevant parts.
For simplicity I've decided to only add one additional lock for all
connector/encoder links and modeset configuration states. We have
piles of different modeset objects in addition to those (like bridges
or panels), so adding per-object locks would be much more effort.
Also, we're guaranteed (at least for now) to do a full modeset if we
need to acquire this lock. Which means that fine-grained locking is
fairly irrelevant compared to the amount of time the full modeset will
take.
I've done a full audit, and there's just a few things that justify
special focus:
- Locking in drm_sysfs.c is almost completely absent. We should
sprinkle mode_config.connection_mutex over this file a bit, but
since it already lacks mode_config.mutex this patch wont make the
situation any worse. This is material for a follow-up patch.
- omap has a omap_framebuffer_flush function which walks the
connector->encoder->crtc links and is called from many contexts.
Some look like they don't acquire mode_config.mutex, so this is
already racy. Again fixing this is material for a separate patch.
- The radeon hot_plug function to retrain DP links looks at
connector->dpms. Currently this happens without any locking, so is
already racy. I think radeon_hotplug_work_func should gain
mutex_lock/unlock calls for the mode_config.connection_mutex.
- Same applies to i915's intel_dp_hot_plug. But again, this is already
racy.
- i915 load_detect code needs to acquire this lock. Which means the
w/w dance due to Rob's work will be nicely contained to _just_ this
function.
I've added fixme comments everywhere where it looks suspicious but in
the sysfs code. After a quick irc discussion with Dave Airlie it
sounds like the lack of locking in there is due to sysfs cleanup fun
at module unload.
v1: original (only compile tested)
v2: missing mutex_init(), etc (from Rob Clark)
v3: i915 needs more care in the conversion:
- Protect the edp pp logic with the connection_mutex.
- Use connection_mutex in the backlight code due to
get_pipe_from_connector.
- Use drm_modeset_lock_all in suspend/resume paths.
- Update lock checks in the overlay code.
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-05-30 05:54:47 +08:00
|
|
|
drm_modeset_lock_all(dev);
|
2014-08-05 18:29:37 +08:00
|
|
|
for_each_intel_encoder(dev, encoder) {
|
2013-11-01 17:50:20 +08:00
|
|
|
if (!encoder->base.crtc)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
crtc = to_intel_crtc(encoder->base.crtc);
|
|
|
|
|
|
|
|
if (crtc->pipe != pipe)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
switch (encoder->type) {
|
|
|
|
case INTEL_OUTPUT_TVOUT:
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_TV;
|
|
|
|
break;
|
|
|
|
case INTEL_OUTPUT_DISPLAYPORT:
|
|
|
|
case INTEL_OUTPUT_EDP:
|
2013-11-01 17:50:23 +08:00
|
|
|
dig_port = enc_to_dig_port(&encoder->base);
|
|
|
|
switch (dig_port->port) {
|
|
|
|
case PORT_B:
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_DP_B;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_DP_C;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_DP_D;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "nonexisting DP port %c\n",
|
|
|
|
port_name(dig_port->port));
|
|
|
|
break;
|
|
|
|
}
|
2013-11-01 17:50:20 +08:00
|
|
|
break;
|
2014-10-28 03:47:52 +08:00
|
|
|
default:
|
|
|
|
break;
|
2013-11-01 17:50:20 +08:00
|
|
|
}
|
|
|
|
}
|
drm: Split connection_mutex out of mode_config.mutex (v3)
After the split-out of crtc locks from the big mode_config.mutex
there's still two major areas it protects:
- Various connector probe states, like connector->status, EDID
properties, probed mode lists and similar information.
- The links from connector->encoder and encoder->crtc and other
modeset-relevant connector state (e.g. properties which control the
panel fitter).
The later is used by modeset operations. But they don't really care
about the former since it's allowed to e.g. enable a disconnected VGA
output or with a mode not in the probed list.
Thus far this hasn't been a problem, but for the atomic modeset
conversion Rob Clark needs to convert all modeset relevant locks into
w/w locks. This is required because the order of acquisition is
determined by how userspace supplies the atomic modeset data. This has
run into troubles in the detect path since the i915 load detect code
needs _both_ protections offered by the mode_config.mutex: It updates
probe state and it needs to change the modeset configuration to enable
the temporary load detect pipe.
The big deal here is that for the probe/detect users of this lock a
plain mutex fits best, but for atomic modesets we really want a w/w
mutex. To fix this lets split out a new connection_mutex lock for the
modeset relevant parts.
For simplicity I've decided to only add one additional lock for all
connector/encoder links and modeset configuration states. We have
piles of different modeset objects in addition to those (like bridges
or panels), so adding per-object locks would be much more effort.
Also, we're guaranteed (at least for now) to do a full modeset if we
need to acquire this lock. Which means that fine-grained locking is
fairly irrelevant compared to the amount of time the full modeset will
take.
I've done a full audit, and there's just a few things that justify
special focus:
- Locking in drm_sysfs.c is almost completely absent. We should
sprinkle mode_config.connection_mutex over this file a bit, but
since it already lacks mode_config.mutex this patch wont make the
situation any worse. This is material for a follow-up patch.
- omap has a omap_framebuffer_flush function which walks the
connector->encoder->crtc links and is called from many contexts.
Some look like they don't acquire mode_config.mutex, so this is
already racy. Again fixing this is material for a separate patch.
- The radeon hot_plug function to retrain DP links looks at
connector->dpms. Currently this happens without any locking, so is
already racy. I think radeon_hotplug_work_func should gain
mutex_lock/unlock calls for the mode_config.connection_mutex.
- Same applies to i915's intel_dp_hot_plug. But again, this is already
racy.
- i915 load_detect code needs to acquire this lock. Which means the
w/w dance due to Rob's work will be nicely contained to _just_ this
function.
I've added fixme comments everywhere where it looks suspicious but in
the sysfs code. After a quick irc discussion with Dave Airlie it
sounds like the lack of locking in there is due to sysfs cleanup fun
at module unload.
v1: original (only compile tested)
v2: missing mutex_init(), etc (from Rob Clark)
v3: i915 needs more care in the conversion:
- Protect the edp pp logic with the connection_mutex.
- Use connection_mutex in the backlight code due to
get_pipe_from_connector.
- Use drm_modeset_lock_all in suspend/resume paths.
- Update lock checks in the overlay code.
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-05-30 05:54:47 +08:00
|
|
|
drm_modeset_unlock_all(dev);
|
2013-11-01 17:50:20 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
|
|
|
|
enum pipe pipe,
|
|
|
|
enum intel_pipe_crc_source *source,
|
2013-10-18 22:37:06 +08:00
|
|
|
uint32_t *val)
|
|
|
|
{
|
2013-11-01 17:50:22 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
bool need_stable_symbols = false;
|
|
|
|
|
2013-11-01 17:50:20 +08:00
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
|
|
|
|
int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (*source) {
|
2013-10-18 22:37:06 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_DP_B:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
|
2013-11-01 17:50:22 +08:00
|
|
|
need_stable_symbols = true;
|
2013-10-18 22:37:06 +08:00
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_DP_C:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
|
2013-11-01 17:50:22 +08:00
|
|
|
need_stable_symbols = true;
|
2013-10-18 22:37:06 +08:00
|
|
|
break;
|
2014-12-10 03:28:29 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_DP_D:
|
|
|
|
if (!IS_CHERRYVIEW(dev))
|
|
|
|
return -EINVAL;
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
|
|
|
|
need_stable_symbols = true;
|
|
|
|
break;
|
2013-10-18 22:37:06 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
|
|
*val = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:22 +08:00
|
|
|
/*
|
|
|
|
* When the pipe CRC tap point is after the transcoders we need
|
|
|
|
* to tweak symbol-level features to produce a deterministic series of
|
|
|
|
* symbols for a given frame. We need to reset those features only once
|
|
|
|
* a frame (instead of every nth symbol):
|
|
|
|
* - DC-balance: used to ensure a better clock recovery from the data
|
|
|
|
* link (SDVO)
|
|
|
|
* - DisplayPort scrambling: used for EMI reduction
|
|
|
|
*/
|
|
|
|
if (need_stable_symbols) {
|
|
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
|
|
|
|
tmp |= DC_BALANCE_RESET_VLV;
|
2014-12-10 03:28:28 +08:00
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
2013-11-01 17:50:22 +08:00
|
|
|
tmp |= PIPE_A_SCRAMBLE_RESET;
|
2014-12-10 03:28:28 +08:00
|
|
|
break;
|
|
|
|
case PIPE_B:
|
2013-11-01 17:50:22 +08:00
|
|
|
tmp |= PIPE_B_SCRAMBLE_RESET;
|
2014-12-10 03:28:28 +08:00
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
tmp |= PIPE_C_SCRAMBLE_RESET;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-11-01 17:50:22 +08:00
|
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
|
|
}
|
|
|
|
|
2013-10-18 22:37:06 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-17 04:55:59 +08:00
|
|
|
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
|
2013-11-01 17:50:20 +08:00
|
|
|
enum pipe pipe,
|
|
|
|
enum intel_pipe_crc_source *source,
|
2013-10-17 04:55:59 +08:00
|
|
|
uint32_t *val)
|
|
|
|
{
|
2013-11-01 17:50:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
bool need_stable_symbols = false;
|
|
|
|
|
2013-11-01 17:50:20 +08:00
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
|
|
|
|
int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (*source) {
|
2013-10-17 04:55:59 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_TV:
|
|
|
|
if (!SUPPORTS_TV(dev))
|
|
|
|
return -EINVAL;
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_DP_B:
|
|
|
|
if (!IS_G4X(dev))
|
|
|
|
return -EINVAL;
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
|
2013-11-01 17:50:21 +08:00
|
|
|
need_stable_symbols = true;
|
2013-10-17 04:55:59 +08:00
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_DP_C:
|
|
|
|
if (!IS_G4X(dev))
|
|
|
|
return -EINVAL;
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
|
2013-11-01 17:50:21 +08:00
|
|
|
need_stable_symbols = true;
|
2013-10-17 04:55:59 +08:00
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_DP_D:
|
|
|
|
if (!IS_G4X(dev))
|
|
|
|
return -EINVAL;
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
|
2013-11-01 17:50:21 +08:00
|
|
|
need_stable_symbols = true;
|
2013-10-17 04:55:59 +08:00
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
|
|
*val = 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:21 +08:00
|
|
|
/*
|
|
|
|
* When the pipe CRC tap point is after the transcoders we need
|
|
|
|
* to tweak symbol-level features to produce a deterministic series of
|
|
|
|
* symbols for a given frame. We need to reset those features only once
|
|
|
|
* a frame (instead of every nth symbol):
|
|
|
|
* - DC-balance: used to ensure a better clock recovery from the data
|
|
|
|
* link (SDVO)
|
|
|
|
* - DisplayPort scrambling: used for EMI reduction
|
|
|
|
*/
|
|
|
|
if (need_stable_symbols) {
|
|
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
|
|
|
|
WARN_ON(!IS_G4X(dev));
|
|
|
|
|
|
|
|
I915_WRITE(PORT_DFT_I9XX,
|
|
|
|
I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
|
|
|
|
|
|
|
|
if (pipe == PIPE_A)
|
|
|
|
tmp |= PIPE_A_SCRAMBLE_RESET;
|
|
|
|
else
|
|
|
|
tmp |= PIPE_B_SCRAMBLE_RESET;
|
|
|
|
|
|
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
|
|
}
|
|
|
|
|
2013-10-17 04:55:59 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:22 +08:00
|
|
|
static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
|
|
|
|
enum pipe pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
|
2014-12-10 03:28:28 +08:00
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
2013-11-01 17:50:22 +08:00
|
|
|
tmp &= ~PIPE_A_SCRAMBLE_RESET;
|
2014-12-10 03:28:28 +08:00
|
|
|
break;
|
|
|
|
case PIPE_B:
|
2013-11-01 17:50:22 +08:00
|
|
|
tmp &= ~PIPE_B_SCRAMBLE_RESET;
|
2014-12-10 03:28:28 +08:00
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
tmp &= ~PIPE_C_SCRAMBLE_RESET;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
2013-11-01 17:50:22 +08:00
|
|
|
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
|
|
|
|
tmp &= ~DC_BALANCE_RESET_VLV;
|
|
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:21 +08:00
|
|
|
static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
|
|
|
|
enum pipe pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
|
|
|
|
|
|
|
|
if (pipe == PIPE_A)
|
|
|
|
tmp &= ~PIPE_A_SCRAMBLE_RESET;
|
|
|
|
else
|
|
|
|
tmp &= ~PIPE_B_SCRAMBLE_RESET;
|
|
|
|
I915_WRITE(PORT_DFT2_G4X, tmp);
|
|
|
|
|
|
|
|
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
|
|
|
|
I915_WRITE(PORT_DFT_I9XX,
|
|
|
|
I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-01 17:50:20 +08:00
|
|
|
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
|
2013-10-17 04:55:48 +08:00
|
|
|
uint32_t *val)
|
|
|
|
{
|
2013-11-01 17:50:20 +08:00
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
|
|
|
|
|
|
|
|
switch (*source) {
|
2013-10-17 04:55:48 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
|
|
|
|
break;
|
2013-10-17 04:55:58 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
2013-10-17 04:55:48 +08:00
|
|
|
*val = 0;
|
|
|
|
break;
|
2013-10-17 04:55:58 +08:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
2013-10-17 04:55:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-08-05 18:36:59 +08:00
|
|
|
static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
|
2014-05-29 20:10:22 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *crtc =
|
|
|
|
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
|
2015-06-01 18:50:08 +08:00
|
|
|
struct intel_crtc_state *pipe_config;
|
2015-08-05 18:36:59 +08:00
|
|
|
struct drm_atomic_state *state;
|
|
|
|
int ret = 0;
|
2014-05-29 20:10:22 +08:00
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
2015-08-05 18:36:59 +08:00
|
|
|
state = drm_atomic_state_alloc(dev);
|
|
|
|
if (!state) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out;
|
2014-05-29 20:10:22 +08:00
|
|
|
}
|
|
|
|
|
2015-08-05 18:36:59 +08:00
|
|
|
state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
|
|
|
|
pipe_config = intel_atomic_get_crtc_state(state, crtc);
|
|
|
|
if (IS_ERR(pipe_config)) {
|
|
|
|
ret = PTR_ERR(pipe_config);
|
|
|
|
goto out;
|
|
|
|
}
|
2014-05-29 20:10:22 +08:00
|
|
|
|
2015-08-05 18:36:59 +08:00
|
|
|
pipe_config->pch_pfit.force_thru = enable;
|
|
|
|
if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
|
|
|
|
pipe_config->pch_pfit.enabled != enable)
|
|
|
|
pipe_config->base.connectors_changed = true;
|
2015-06-01 18:49:48 +08:00
|
|
|
|
2015-08-05 18:36:59 +08:00
|
|
|
ret = drm_atomic_commit(state);
|
|
|
|
out:
|
2014-05-29 20:10:22 +08:00
|
|
|
drm_modeset_unlock_all(dev);
|
2015-08-05 18:36:59 +08:00
|
|
|
WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
|
|
|
|
if (ret)
|
|
|
|
drm_atomic_state_free(state);
|
2014-05-29 20:10:22 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
|
|
|
|
enum pipe pipe,
|
|
|
|
enum intel_pipe_crc_source *source,
|
2013-10-17 04:55:48 +08:00
|
|
|
uint32_t *val)
|
|
|
|
{
|
2013-11-01 17:50:20 +08:00
|
|
|
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
|
|
|
|
*source = INTEL_PIPE_CRC_SOURCE_PF;
|
|
|
|
|
|
|
|
switch (*source) {
|
2013-10-17 04:55:48 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
|
|
|
|
break;
|
|
|
|
case INTEL_PIPE_CRC_SOURCE_PF:
|
2014-05-29 20:10:22 +08:00
|
|
|
if (IS_HASWELL(dev) && pipe == PIPE_A)
|
2015-08-05 18:36:59 +08:00
|
|
|
hsw_trans_edp_pipe_A_crc_wa(dev, true);
|
2014-05-29 20:10:22 +08:00
|
|
|
|
2013-10-17 04:55:48 +08:00
|
|
|
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
|
|
|
|
break;
|
2013-10-17 04:55:58 +08:00
|
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
2013-10-17 04:55:48 +08:00
|
|
|
*val = 0;
|
|
|
|
break;
|
2013-10-17 04:55:58 +08:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
2013-10-17 04:55:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-16 19:30:34 +08:00
|
|
|
static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
|
|
|
|
enum intel_pipe_crc_source source)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-16 01:55:31 +08:00
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
2014-10-18 05:42:03 +08:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
|
|
|
|
pipe));
|
2016-02-13 00:55:17 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
2013-11-21 23:49:46 +08:00
|
|
|
u32 val = 0; /* shut up gcc */
|
2013-10-17 04:55:48 +08:00
|
|
|
int ret;
|
2013-10-16 19:30:34 +08:00
|
|
|
|
2013-10-16 01:55:31 +08:00
|
|
|
if (pipe_crc->source == source)
|
|
|
|
return 0;
|
|
|
|
|
2013-10-16 01:55:32 +08:00
|
|
|
/* forbid changing the source without going back to 'none' */
|
|
|
|
if (pipe_crc->source && source)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2016-02-13 00:55:17 +08:00
|
|
|
power_domain = POWER_DOMAIN_PIPE(pipe);
|
|
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
|
2014-11-25 21:00:40 +08:00
|
|
|
DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2013-10-21 23:26:38 +08:00
|
|
|
if (IS_GEN2(dev))
|
2013-11-01 17:50:20 +08:00
|
|
|
ret = i8xx_pipe_crc_ctl_reg(&source, &val);
|
2013-10-21 23:26:38 +08:00
|
|
|
else if (INTEL_INFO(dev)->gen < 5)
|
2013-11-01 17:50:20 +08:00
|
|
|
ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
|
2015-12-10 04:29:35 +08:00
|
|
|
else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
2014-05-29 20:10:22 +08:00
|
|
|
ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
|
2013-10-17 04:55:59 +08:00
|
|
|
else if (IS_GEN5(dev) || IS_GEN6(dev))
|
2013-11-01 17:50:20 +08:00
|
|
|
ret = ilk_pipe_crc_ctl_reg(&source, &val);
|
2013-10-17 04:55:48 +08:00
|
|
|
else
|
2014-05-29 20:10:22 +08:00
|
|
|
ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
|
2013-10-17 04:55:48 +08:00
|
|
|
|
|
|
|
if (ret != 0)
|
2016-02-13 00:55:17 +08:00
|
|
|
goto out;
|
2013-10-17 04:55:48 +08:00
|
|
|
|
2013-10-16 01:55:33 +08:00
|
|
|
/* none -> real source transition */
|
|
|
|
if (source) {
|
2014-12-10 03:28:30 +08:00
|
|
|
struct intel_pipe_crc_entry *entries;
|
|
|
|
|
2013-10-16 01:55:38 +08:00
|
|
|
DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
|
|
|
|
pipe_name(pipe), pipe_crc_source_name(source));
|
|
|
|
|
2014-12-10 03:28:31 +08:00
|
|
|
entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
|
|
|
|
sizeof(pipe_crc->entries[0]),
|
2014-12-10 03:28:30 +08:00
|
|
|
GFP_KERNEL);
|
2016-02-13 00:55:17 +08:00
|
|
|
if (!entries) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out;
|
|
|
|
}
|
2013-10-16 01:55:34 +08:00
|
|
|
|
2014-10-18 05:42:03 +08:00
|
|
|
/*
|
|
|
|
* When IPS gets enabled, the pipe CRC changes. Since IPS gets
|
|
|
|
* enabled and disabled dynamically based on package C states,
|
|
|
|
* user space can't make reliable use of the CRCs, so let's just
|
|
|
|
* completely disable it.
|
|
|
|
*/
|
|
|
|
hsw_disable_ips(crtc);
|
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
2014-12-10 18:00:29 +08:00
|
|
|
kfree(pipe_crc->entries);
|
2014-12-10 03:28:30 +08:00
|
|
|
pipe_crc->entries = entries;
|
2013-10-21 21:29:30 +08:00
|
|
|
pipe_crc->head = 0;
|
|
|
|
pipe_crc->tail = 0;
|
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
2013-10-16 01:55:33 +08:00
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:31 +08:00
|
|
|
pipe_crc->source = source;
|
2013-10-16 19:30:34 +08:00
|
|
|
|
|
|
|
I915_WRITE(PIPE_CRC_CTL(pipe), val);
|
|
|
|
POSTING_READ(PIPE_CRC_CTL(pipe));
|
|
|
|
|
2013-10-16 01:55:34 +08:00
|
|
|
/* real source -> none transition */
|
|
|
|
if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
|
2013-10-21 21:29:30 +08:00
|
|
|
struct intel_pipe_crc_entry *entries;
|
2014-06-06 14:22:08 +08:00
|
|
|
struct intel_crtc *crtc =
|
|
|
|
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
2013-10-21 21:29:30 +08:00
|
|
|
|
2013-10-16 01:55:38 +08:00
|
|
|
DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
|
|
|
|
pipe_name(pipe));
|
|
|
|
|
2014-06-06 14:22:08 +08:00
|
|
|
drm_modeset_lock(&crtc->base.mutex, NULL);
|
2015-06-01 18:50:08 +08:00
|
|
|
if (crtc->base.state->active)
|
2014-06-06 14:22:08 +08:00
|
|
|
intel_wait_for_vblank(dev, pipe);
|
|
|
|
drm_modeset_unlock(&crtc->base.mutex);
|
2013-10-17 04:55:50 +08:00
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
|
|
entries = pipe_crc->entries;
|
2013-10-16 01:55:34 +08:00
|
|
|
pipe_crc->entries = NULL;
|
2014-12-10 03:28:32 +08:00
|
|
|
pipe_crc->head = 0;
|
|
|
|
pipe_crc->tail = 0;
|
2013-10-21 21:29:30 +08:00
|
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
|
|
|
|
kfree(entries);
|
2013-11-01 17:50:21 +08:00
|
|
|
|
|
|
|
if (IS_G4X(dev))
|
|
|
|
g4x_undo_pipe_scramble_reset(dev, pipe);
|
2015-12-10 04:29:35 +08:00
|
|
|
else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
|
2013-11-01 17:50:22 +08:00
|
|
|
vlv_undo_pipe_scramble_reset(dev, pipe);
|
2014-05-29 20:10:22 +08:00
|
|
|
else if (IS_HASWELL(dev) && pipe == PIPE_A)
|
2015-08-05 18:36:59 +08:00
|
|
|
hsw_trans_edp_pipe_A_crc_wa(dev, false);
|
2014-10-18 05:42:03 +08:00
|
|
|
|
|
|
|
hsw_enable_ips(crtc);
|
2013-10-16 01:55:34 +08:00
|
|
|
}
|
|
|
|
|
2016-02-13 00:55:17 +08:00
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
out:
|
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
|
|
|
|
return ret;
|
2013-10-16 19:30:34 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Parse pipe CRC command strings:
|
2013-10-16 01:55:35 +08:00
|
|
|
* command: wsp* object wsp+ name wsp+ source wsp*
|
|
|
|
* object: 'pipe'
|
|
|
|
* name: (A | B | C)
|
2013-10-16 19:30:34 +08:00
|
|
|
* source: (none | plane1 | plane2 | pf)
|
|
|
|
* wsp: (#0x20 | #0x9 | #0xA)+
|
|
|
|
*
|
|
|
|
* eg.:
|
2013-10-16 01:55:35 +08:00
|
|
|
* "pipe A plane1" -> Start CRC computations on plane1 of pipe A
|
|
|
|
* "pipe A none" -> Stop CRC
|
2013-10-16 19:30:34 +08:00
|
|
|
*/
|
2013-10-16 01:55:36 +08:00
|
|
|
static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
|
|
|
int n_words = 0;
|
|
|
|
|
|
|
|
while (*buf) {
|
|
|
|
char *end;
|
|
|
|
|
|
|
|
/* skip leading white space */
|
|
|
|
buf = skip_spaces(buf);
|
|
|
|
if (!*buf)
|
|
|
|
break; /* end of buffer */
|
|
|
|
|
|
|
|
/* find end of word */
|
|
|
|
for (end = buf; *end && !isspace(*end); end++)
|
|
|
|
;
|
|
|
|
|
|
|
|
if (n_words == max_words) {
|
|
|
|
DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
|
|
|
|
max_words);
|
|
|
|
return -EINVAL; /* ran out of words[] before bytes */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (*end)
|
|
|
|
*end++ = '\0';
|
|
|
|
words[n_words++] = buf;
|
|
|
|
buf = end;
|
|
|
|
}
|
|
|
|
|
|
|
|
return n_words;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:35 +08:00
|
|
|
enum intel_pipe_crc_object {
|
|
|
|
PIPE_CRC_OBJECT_PIPE,
|
|
|
|
};
|
|
|
|
|
2013-10-16 17:51:54 +08:00
|
|
|
static const char * const pipe_crc_objects[] = {
|
2013-10-16 01:55:35 +08:00
|
|
|
"pipe",
|
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
2013-10-16 01:55:36 +08:00
|
|
|
display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
|
2013-10-16 01:55:35 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
|
|
|
|
if (!strcmp(buf, pipe_crc_objects[i])) {
|
2013-10-16 01:55:36 +08:00
|
|
|
*o = i;
|
2013-10-16 01:55:35 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
|
|
|
const char name = buf[0];
|
|
|
|
|
|
|
|
if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
*pipe = name - 'A';
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2013-10-16 01:55:36 +08:00
|
|
|
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
|
|
|
|
if (!strcmp(buf, pipe_crc_sources[i])) {
|
2013-10-16 01:55:36 +08:00
|
|
|
*s = i;
|
2013-10-16 19:30:34 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
2013-10-16 01:55:35 +08:00
|
|
|
#define N_WORDS 3
|
2013-10-16 19:30:34 +08:00
|
|
|
int n_words;
|
2013-10-16 01:55:35 +08:00
|
|
|
char *words[N_WORDS];
|
2013-10-16 19:30:34 +08:00
|
|
|
enum pipe pipe;
|
2013-10-16 01:55:35 +08:00
|
|
|
enum intel_pipe_crc_object object;
|
2013-10-16 19:30:34 +08:00
|
|
|
enum intel_pipe_crc_source source;
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
|
2013-10-16 01:55:35 +08:00
|
|
|
if (n_words != N_WORDS) {
|
|
|
|
DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
|
|
|
|
N_WORDS);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
if (display_crc_ctl_parse_object(words[0], &object) < 0) {
|
2013-10-16 01:55:35 +08:00
|
|
|
DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
|
2013-10-16 19:30:34 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
|
2013-10-16 01:55:35 +08:00
|
|
|
DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
|
2013-10-16 19:30:34 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
if (display_crc_ctl_parse_source(words[2], &source) < 0) {
|
2013-10-16 01:55:35 +08:00
|
|
|
DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
|
2013-10-16 19:30:34 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return pipe_crc_set_source(dev, pipe, source);
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
|
|
|
|
size_t len, loff_t *offp)
|
2013-10-16 19:30:34 +08:00
|
|
|
{
|
|
|
|
struct seq_file *m = file->private_data;
|
|
|
|
struct drm_device *dev = m->private;
|
|
|
|
char *tmpbuf;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (len == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (len > PAGE_SIZE - 1) {
|
|
|
|
DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
|
|
|
|
PAGE_SIZE);
|
|
|
|
return -E2BIG;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmpbuf = kmalloc(len + 1, GFP_KERNEL);
|
|
|
|
if (!tmpbuf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (copy_from_user(tmpbuf, ubuf, len)) {
|
|
|
|
ret = -EFAULT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
tmpbuf[len] = '\0';
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
ret = display_crc_ctl_parse(dev, tmpbuf, len);
|
2013-10-16 19:30:34 +08:00
|
|
|
|
|
|
|
out:
|
|
|
|
kfree(tmpbuf);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
*offp += len;
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
2013-10-16 01:55:36 +08:00
|
|
|
static const struct file_operations i915_display_crc_ctl_fops = {
|
2013-10-16 19:30:34 +08:00
|
|
|
.owner = THIS_MODULE,
|
2013-10-16 01:55:36 +08:00
|
|
|
.open = display_crc_ctl_open,
|
2013-10-16 19:30:34 +08:00
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
2013-10-16 01:55:36 +08:00
|
|
|
.write = display_crc_ctl_write
|
2013-10-16 19:30:34 +08:00
|
|
|
};
|
|
|
|
|
2015-04-18 15:04:19 +08:00
|
|
|
static ssize_t i915_displayport_test_active_write(struct file *file,
|
|
|
|
const char __user *ubuf,
|
|
|
|
size_t len, loff_t *offp)
|
|
|
|
{
|
|
|
|
char *input_buffer;
|
|
|
|
int status = 0;
|
|
|
|
struct drm_device *dev;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
struct list_head *connector_list;
|
|
|
|
struct intel_dp *intel_dp;
|
|
|
|
int val = 0;
|
|
|
|
|
2015-07-21 20:06:45 +08:00
|
|
|
dev = ((struct seq_file *)file->private_data)->private;
|
2015-04-18 15:04:19 +08:00
|
|
|
|
|
|
|
connector_list = &dev->mode_config.connector_list;
|
|
|
|
|
|
|
|
if (len == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
input_buffer = kmalloc(len + 1, GFP_KERNEL);
|
|
|
|
if (!input_buffer)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (copy_from_user(input_buffer, ubuf, len)) {
|
|
|
|
status = -EFAULT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
input_buffer[len] = '\0';
|
|
|
|
DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
|
|
|
|
|
|
|
|
list_for_each_entry(connector, connector_list, head) {
|
|
|
|
|
|
|
|
if (connector->connector_type !=
|
|
|
|
DRM_MODE_CONNECTOR_DisplayPort)
|
|
|
|
continue;
|
|
|
|
|
2015-07-21 20:06:46 +08:00
|
|
|
if (connector->status == connector_status_connected &&
|
2015-04-18 15:04:19 +08:00
|
|
|
connector->encoder != NULL) {
|
|
|
|
intel_dp = enc_to_intel_dp(connector->encoder);
|
|
|
|
status = kstrtoint(input_buffer, 10, &val);
|
|
|
|
if (status < 0)
|
|
|
|
goto out;
|
|
|
|
DRM_DEBUG_DRIVER("Got %d for test active\n", val);
|
|
|
|
/* To prevent erroneous activation of the compliance
|
|
|
|
* testing code, only accept an actual value of 1 here
|
|
|
|
*/
|
|
|
|
if (val == 1)
|
|
|
|
intel_dp->compliance_test_active = 1;
|
|
|
|
else
|
|
|
|
intel_dp->compliance_test_active = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
kfree(input_buffer);
|
|
|
|
if (status < 0)
|
|
|
|
return status;
|
|
|
|
|
|
|
|
*offp += len;
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_displayport_test_active_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
struct list_head *connector_list = &dev->mode_config.connector_list;
|
|
|
|
struct intel_dp *intel_dp;
|
|
|
|
|
|
|
|
list_for_each_entry(connector, connector_list, head) {
|
|
|
|
|
|
|
|
if (connector->connector_type !=
|
|
|
|
DRM_MODE_CONNECTOR_DisplayPort)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (connector->status == connector_status_connected &&
|
|
|
|
connector->encoder != NULL) {
|
|
|
|
intel_dp = enc_to_intel_dp(connector->encoder);
|
|
|
|
if (intel_dp->compliance_test_active)
|
|
|
|
seq_puts(m, "1");
|
|
|
|
else
|
|
|
|
seq_puts(m, "0");
|
|
|
|
} else
|
|
|
|
seq_puts(m, "0");
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_displayport_test_active_open(struct inode *inode,
|
|
|
|
struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
|
|
|
return single_open(file, i915_displayport_test_active_show, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_displayport_test_active_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_displayport_test_active_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
.write = i915_displayport_test_active_write
|
|
|
|
};
|
|
|
|
|
|
|
|
static int i915_displayport_test_data_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
struct list_head *connector_list = &dev->mode_config.connector_list;
|
|
|
|
struct intel_dp *intel_dp;
|
|
|
|
|
|
|
|
list_for_each_entry(connector, connector_list, head) {
|
|
|
|
|
|
|
|
if (connector->connector_type !=
|
|
|
|
DRM_MODE_CONNECTOR_DisplayPort)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (connector->status == connector_status_connected &&
|
|
|
|
connector->encoder != NULL) {
|
|
|
|
intel_dp = enc_to_intel_dp(connector->encoder);
|
|
|
|
seq_printf(m, "%lx", intel_dp->compliance_test_data);
|
|
|
|
} else
|
|
|
|
seq_puts(m, "0");
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static int i915_displayport_test_data_open(struct inode *inode,
|
|
|
|
struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
|
|
|
return single_open(file, i915_displayport_test_data_show, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_displayport_test_data_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_displayport_test_data_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release
|
|
|
|
};
|
|
|
|
|
|
|
|
static int i915_displayport_test_type_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
struct list_head *connector_list = &dev->mode_config.connector_list;
|
|
|
|
struct intel_dp *intel_dp;
|
|
|
|
|
|
|
|
list_for_each_entry(connector, connector_list, head) {
|
|
|
|
|
|
|
|
if (connector->connector_type !=
|
|
|
|
DRM_MODE_CONNECTOR_DisplayPort)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (connector->status == connector_status_connected &&
|
|
|
|
connector->encoder != NULL) {
|
|
|
|
intel_dp = enc_to_intel_dp(connector->encoder);
|
|
|
|
seq_printf(m, "%02lx", intel_dp->compliance_test_type);
|
|
|
|
} else
|
|
|
|
seq_puts(m, "0");
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_displayport_test_type_open(struct inode *inode,
|
|
|
|
struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
|
|
|
return single_open(file, i915_displayport_test_type_show, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_displayport_test_type_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_displayport_test_type_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release
|
|
|
|
};
|
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
|
2014-01-22 20:36:08 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
|
|
|
int level;
|
2015-06-25 03:00:09 +08:00
|
|
|
int num_levels;
|
|
|
|
|
|
|
|
if (IS_CHERRYVIEW(dev))
|
|
|
|
num_levels = 3;
|
|
|
|
else if (IS_VALLEYVIEW(dev))
|
|
|
|
num_levels = 1;
|
|
|
|
else
|
|
|
|
num_levels = ilk_wm_max_level(dev) + 1;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
|
|
|
|
for (level = 0; level < num_levels; level++) {
|
|
|
|
unsigned int latency = wm[level];
|
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
/*
|
|
|
|
* - WM1+ latency values in 0.5us units
|
2015-06-25 03:00:09 +08:00
|
|
|
* - latencies are in us on gen9/vlv/chv
|
2014-11-05 01:06:50 +08:00
|
|
|
*/
|
2015-12-10 04:29:35 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
|
|
|
|
IS_CHERRYVIEW(dev))
|
2014-11-05 01:06:50 +08:00
|
|
|
latency *= 10;
|
|
|
|
else if (level > 0)
|
2014-01-22 20:36:08 +08:00
|
|
|
latency *= 5;
|
|
|
|
|
|
|
|
seq_printf(m, "WM%d %u (%u.%u usec)\n",
|
2014-11-05 01:06:50 +08:00
|
|
|
level, wm[level], latency / 10, latency % 10);
|
2014-01-22 20:36:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pri_wm_latency_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
const uint16_t *latencies;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
|
latencies = dev_priv->wm.skl_latency;
|
|
|
|
else
|
|
|
|
latencies = to_i915(dev)->wm.pri_latency;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
wm_latency_show(m, latencies);
|
2014-01-22 20:36:08 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int spr_wm_latency_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
const uint16_t *latencies;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
|
latencies = dev_priv->wm.skl_latency;
|
|
|
|
else
|
|
|
|
latencies = to_i915(dev)->wm.spr_latency;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
wm_latency_show(m, latencies);
|
2014-01-22 20:36:08 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cur_wm_latency_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
const uint16_t *latencies;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
|
latencies = dev_priv->wm.skl_latency;
|
|
|
|
else
|
|
|
|
latencies = to_i915(dev)->wm.cur_latency;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
wm_latency_show(m, latencies);
|
2014-01-22 20:36:08 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pri_wm_latency_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
2015-06-25 03:00:09 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 5)
|
2014-01-22 20:36:08 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return single_open(file, pri_wm_latency_show, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int spr_wm_latency_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
2014-07-21 17:53:39 +08:00
|
|
|
if (HAS_GMCH_DISPLAY(dev))
|
2014-01-22 20:36:08 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return single_open(file, spr_wm_latency_show, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cur_wm_latency_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
|
2014-07-21 17:53:39 +08:00
|
|
|
if (HAS_GMCH_DISPLAY(dev))
|
2014-01-22 20:36:08 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
return single_open(file, cur_wm_latency_show, dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
|
2014-11-05 01:06:50 +08:00
|
|
|
size_t len, loff_t *offp, uint16_t wm[8])
|
2014-01-22 20:36:08 +08:00
|
|
|
{
|
|
|
|
struct seq_file *m = file->private_data;
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
uint16_t new[8] = { 0 };
|
2015-06-25 03:00:09 +08:00
|
|
|
int num_levels;
|
2014-01-22 20:36:08 +08:00
|
|
|
int level;
|
|
|
|
int ret;
|
|
|
|
char tmp[32];
|
|
|
|
|
2015-06-25 03:00:09 +08:00
|
|
|
if (IS_CHERRYVIEW(dev))
|
|
|
|
num_levels = 3;
|
|
|
|
else if (IS_VALLEYVIEW(dev))
|
|
|
|
num_levels = 1;
|
|
|
|
else
|
|
|
|
num_levels = ilk_wm_max_level(dev) + 1;
|
|
|
|
|
2014-01-22 20:36:08 +08:00
|
|
|
if (len >= sizeof(tmp))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (copy_from_user(tmp, ubuf, len))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
tmp[len] = '\0';
|
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
|
|
|
|
&new[0], &new[1], &new[2], &new[3],
|
|
|
|
&new[4], &new[5], &new[6], &new[7]);
|
2014-01-22 20:36:08 +08:00
|
|
|
if (ret != num_levels)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
|
|
|
|
for (level = 0; level < num_levels; level++)
|
|
|
|
wm[level] = new[level];
|
|
|
|
|
|
|
|
drm_modeset_unlock_all(dev);
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
|
|
|
|
size_t len, loff_t *offp)
|
|
|
|
{
|
|
|
|
struct seq_file *m = file->private_data;
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint16_t *latencies;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
|
latencies = dev_priv->wm.skl_latency;
|
|
|
|
else
|
|
|
|
latencies = to_i915(dev)->wm.pri_latency;
|
|
|
|
|
|
|
|
return wm_latency_write(file, ubuf, len, offp, latencies);
|
2014-01-22 20:36:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
|
|
|
|
size_t len, loff_t *offp)
|
|
|
|
{
|
|
|
|
struct seq_file *m = file->private_data;
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint16_t *latencies;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
|
latencies = dev_priv->wm.skl_latency;
|
|
|
|
else
|
|
|
|
latencies = to_i915(dev)->wm.spr_latency;
|
|
|
|
|
|
|
|
return wm_latency_write(file, ubuf, len, offp, latencies);
|
2014-01-22 20:36:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
|
|
|
|
size_t len, loff_t *offp)
|
|
|
|
{
|
|
|
|
struct seq_file *m = file->private_data;
|
|
|
|
struct drm_device *dev = m->private;
|
2014-11-05 01:06:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint16_t *latencies;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
|
|
latencies = dev_priv->wm.skl_latency;
|
|
|
|
else
|
|
|
|
latencies = to_i915(dev)->wm.cur_latency;
|
2014-01-22 20:36:08 +08:00
|
|
|
|
2014-11-05 01:06:50 +08:00
|
|
|
return wm_latency_write(file, ubuf, len, offp, latencies);
|
2014-01-22 20:36:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_pri_wm_latency_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = pri_wm_latency_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
.write = pri_wm_latency_write
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct file_operations i915_spr_wm_latency_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = spr_wm_latency_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
.write = spr_wm_latency_write
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct file_operations i915_cur_wm_latency_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = cur_wm_latency_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
.write = cur_wm_latency_write
|
|
|
|
};
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_wedged_get(void *data, u64 *val)
|
2009-10-14 05:20:20 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2009-10-14 05:20:20 +08:00
|
|
|
|
2016-04-14 00:35:05 +08:00
|
|
|
*val = i915_terminally_wedged(&dev_priv->gpu_error);
|
2009-10-14 05:20:20 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2009-10-14 05:20:20 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_wedged_set(void *data, u64 val)
|
2009-10-14 05:20:20 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-04-15 01:24:27 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2015-01-28 23:03:14 +08:00
|
|
|
/*
|
|
|
|
* There is no safeguard against this debugfs entry colliding
|
|
|
|
* with the hangcheck calling same i915_handle_error() in
|
|
|
|
* parallel, causing an explosion. For now we assume that the
|
|
|
|
* test harness is responsible enough not to inject gpu hangs
|
|
|
|
* while it is writing to 'i915_wedged'
|
|
|
|
*/
|
|
|
|
|
2016-04-14 00:35:05 +08:00
|
|
|
if (i915_reset_in_progress(&dev_priv->gpu_error))
|
2015-01-28 23:03:14 +08:00
|
|
|
return -EAGAIN;
|
|
|
|
|
2014-04-15 01:24:27 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2009-10-14 05:20:20 +08:00
|
|
|
|
2016-05-06 22:40:21 +08:00
|
|
|
i915_handle_error(dev_priv, val,
|
2014-02-25 23:11:26 +08:00
|
|
|
"Manually setting wedged to %llu", val);
|
2014-04-15 01:24:27 +08:00
|
|
|
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2009-10-14 05:20:20 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
|
|
|
|
i915_wedged_get, i915_wedged_set,
|
2013-04-12 17:10:05 +08:00
|
|
|
"%llu\n");
|
2009-10-14 05:20:20 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_ring_stop_get(void *data, u64 *val)
|
2012-05-03 20:48:16 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-05-03 20:48:16 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
*val = dev_priv->gpu_error.stop_rings;
|
2012-05-03 20:48:16 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2012-05-03 20:48:16 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_ring_stop_set(void *data, u64 val)
|
2012-05-03 20:48:16 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2012-05-03 20:48:16 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2012-05-03 20:48:16 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
|
2012-05-03 20:48:16 +08:00
|
|
|
|
2012-08-09 21:07:02 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-11-15 00:14:04 +08:00
|
|
|
dev_priv->gpu_error.stop_rings = val;
|
2012-05-03 20:48:16 +08:00
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2012-05-03 20:48:16 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
|
|
|
|
i915_ring_stop_get, i915_ring_stop_set,
|
|
|
|
"0x%08llx\n");
|
2012-04-27 21:17:40 +08:00
|
|
|
|
2013-09-26 00:34:55 +08:00
|
|
|
static int
|
|
|
|
i915_ring_missed_irq_get(void *data, u64 *val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
*val = dev_priv->gpu_error.missed_irq_rings;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
i915_ring_missed_irq_set(void *data, u64 val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Lock against concurrent debugfs callers */
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
dev_priv->gpu_error.missed_irq_rings = val;
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
|
|
|
|
i915_ring_missed_irq_get, i915_ring_missed_irq_set,
|
|
|
|
"0x%08llx\n");
|
|
|
|
|
|
|
|
static int
|
|
|
|
i915_ring_test_irq_get(void *data, u64 *val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
*val = dev_priv->gpu_error.test_irq_rings;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
i915_ring_test_irq_set(void *data, u64 val)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = data;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
|
|
|
|
|
|
|
|
/* Lock against concurrent debugfs callers */
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
dev_priv->gpu_error.test_irq_rings = val;
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
|
|
|
|
i915_ring_test_irq_get, i915_ring_test_irq_set,
|
|
|
|
"0x%08llx\n");
|
|
|
|
|
2013-01-15 20:39:35 +08:00
|
|
|
#define DROP_UNBOUND 0x1
|
|
|
|
#define DROP_BOUND 0x2
|
|
|
|
#define DROP_RETIRE 0x4
|
|
|
|
#define DROP_ACTIVE 0x8
|
|
|
|
#define DROP_ALL (DROP_UNBOUND | \
|
|
|
|
DROP_BOUND | \
|
|
|
|
DROP_RETIRE | \
|
|
|
|
DROP_ACTIVE)
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_drop_caches_get(void *data, u64 *val)
|
2013-01-15 20:39:35 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
*val = DROP_ALL;
|
2013-01-15 20:39:35 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2013-01-15 20:39:35 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_drop_caches_set(void *data, u64 val)
|
2013-01-15 20:39:35 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2013-01-15 20:39:35 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2013-01-15 20:39:35 +08:00
|
|
|
|
2013-11-26 01:54:37 +08:00
|
|
|
DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
|
2013-01-15 20:39:35 +08:00
|
|
|
|
|
|
|
/* No need to check and wait for gpu resets, only libdrm auto-restarts
|
|
|
|
* on ioctls on -EAGAIN. */
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (val & DROP_ACTIVE) {
|
|
|
|
ret = i915_gpu_idle(dev);
|
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (val & (DROP_RETIRE | DROP_ACTIVE))
|
2016-05-06 22:40:21 +08:00
|
|
|
i915_gem_retire_requests(dev_priv);
|
2013-01-15 20:39:35 +08:00
|
|
|
|
2014-09-09 18:16:08 +08:00
|
|
|
if (val & DROP_BOUND)
|
|
|
|
i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
|
2014-09-04 02:23:37 +08:00
|
|
|
|
2014-09-09 18:16:08 +08:00
|
|
|
if (val & DROP_UNBOUND)
|
|
|
|
i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
|
2013-01-15 20:39:35 +08:00
|
|
|
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return ret;
|
2013-01-15 20:39:35 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
|
|
|
|
i915_drop_caches_get, i915_drop_caches_set,
|
|
|
|
"0x%08llx\n");
|
2013-01-15 20:39:35 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_max_freq_get(void *data, u64 *val)
|
2011-07-28 02:53:01 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2012-08-09 21:07:01 +08:00
|
|
|
|
2014-05-31 07:22:10 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2012-08-09 21:07:01 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
2013-09-17 05:56:43 +08:00
|
|
|
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
|
2012-08-09 21:07:01 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-07-28 02:53:01 +08:00
|
|
|
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2011-07-28 02:53:01 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2011-07-28 02:53:01 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_max_freq_set(void *data, u64 val)
|
2011-07-28 02:53:01 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2011-07-28 02:53:01 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.
v2: Reverted the changes in i915_frequency_info function, to continue report
back the frequency values, as per the actual Hw state (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-26 18:39:47 +08:00
|
|
|
u32 hw_max, hw_min;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2012-08-09 21:07:01 +08:00
|
|
|
|
2014-05-31 07:22:10 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2012-08-09 21:07:01 +08:00
|
|
|
return -ENODEV;
|
2011-07-28 02:53:01 +08:00
|
|
|
|
2013-09-17 05:56:43 +08:00
|
|
|
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
|
2011-07-28 02:53:01 +08:00
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
|
2012-08-09 21:07:01 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-07-28 02:53:01 +08:00
|
|
|
/*
|
|
|
|
* Turbo will still be enabled, but won't go above the set value.
|
|
|
|
*/
|
drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.
v2: Reverted the changes in i915_frequency_info function, to continue report
back the frequency values, as per the actual Hw state (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-26 18:39:47 +08:00
|
|
|
val = intel_freq_opcode(dev_priv, val);
|
2014-02-05 01:32:31 +08:00
|
|
|
|
drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.
v2: Reverted the changes in i915_frequency_info function, to continue report
back the frequency values, as per the actual Hw state (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-26 18:39:47 +08:00
|
|
|
hw_max = dev_priv->rps.max_freq;
|
|
|
|
hw_min = dev_priv->rps.min_freq;
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2014-03-20 09:31:11 +08:00
|
|
|
if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
|
2014-02-05 01:32:31 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
return -EINVAL;
|
2013-04-18 06:54:58 +08:00
|
|
|
}
|
|
|
|
|
2014-03-20 09:31:11 +08:00
|
|
|
dev_priv->rps.max_freq_softlimit = val;
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2016-05-10 21:10:04 +08:00
|
|
|
intel_set_rps(dev_priv, val);
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2011-07-28 02:53:01 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2011-07-28 02:53:01 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
|
|
|
|
i915_max_freq_get, i915_max_freq_set,
|
2013-04-12 17:10:05 +08:00
|
|
|
"%llu\n");
|
2011-07-28 02:53:01 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_min_freq_get(void *data, u64 *val)
|
2012-05-26 03:34:54 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2012-08-09 21:07:01 +08:00
|
|
|
|
2014-05-31 07:22:10 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2012-08-09 21:07:01 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
2013-09-17 05:56:43 +08:00
|
|
|
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
|
2012-08-09 21:07:01 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2012-05-26 03:34:54 +08:00
|
|
|
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-24 03:04:26 +08:00
|
|
|
*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2012-05-26 03:34:54 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2012-05-26 03:34:54 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_min_freq_set(void *data, u64 val)
|
2012-05-26 03:34:54 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2012-05-26 03:34:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.
v2: Reverted the changes in i915_frequency_info function, to continue report
back the frequency values, as per the actual Hw state (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-26 18:39:47 +08:00
|
|
|
u32 hw_max, hw_min;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2012-08-09 21:07:01 +08:00
|
|
|
|
2014-05-31 07:22:10 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2012-08-09 21:07:01 +08:00
|
|
|
return -ENODEV;
|
2012-05-26 03:34:54 +08:00
|
|
|
|
2013-09-17 05:56:43 +08:00
|
|
|
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
|
2012-05-26 03:34:54 +08:00
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
|
2012-08-09 21:07:01 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-05-26 03:34:54 +08:00
|
|
|
/*
|
|
|
|
* Turbo will still be enabled, but won't go below the set value.
|
|
|
|
*/
|
drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.
v2: Reverted the changes in i915_frequency_info function, to continue report
back the frequency values, as per the actual Hw state (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-26 18:39:47 +08:00
|
|
|
val = intel_freq_opcode(dev_priv, val);
|
2014-02-05 01:32:31 +08:00
|
|
|
|
drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.
v2: Reverted the changes in i915_frequency_info function, to continue report
back the frequency values, as per the actual Hw state (Chris)
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-26 18:39:47 +08:00
|
|
|
hw_max = dev_priv->rps.max_freq;
|
|
|
|
hw_min = dev_priv->rps.min_freq;
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2014-03-20 09:31:11 +08:00
|
|
|
if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
|
2014-02-05 01:32:31 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
return -EINVAL;
|
2013-04-18 06:54:58 +08:00
|
|
|
}
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2014-03-20 09:31:11 +08:00
|
|
|
dev_priv->rps.min_freq_softlimit = val;
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2016-05-10 21:10:04 +08:00
|
|
|
intel_set_rps(dev_priv, val);
|
2014-02-05 01:32:31 +08:00
|
|
|
|
2012-11-03 02:14:01 +08:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2012-05-26 03:34:54 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2012-05-26 03:34:54 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
|
|
|
|
i915_min_freq_get, i915_min_freq_set,
|
2013-04-12 17:10:05 +08:00
|
|
|
"%llu\n");
|
2012-05-26 03:34:54 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_cache_sharing_get(void *data, u64 *val)
|
2011-08-04 02:28:44 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2014-03-31 19:27:14 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-08-04 02:28:44 +08:00
|
|
|
u32 snpcr;
|
2013-03-11 05:10:06 +08:00
|
|
|
int ret;
|
2011-08-04 02:28:44 +08:00
|
|
|
|
2012-08-09 21:07:01 +08:00
|
|
|
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2012-08-09 21:07:02 +08:00
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2012-08-09 21:07:02 +08:00
|
|
|
|
2011-08-04 02:28:44 +08:00
|
|
|
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
|
2013-11-28 04:21:54 +08:00
|
|
|
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
2011-08-04 02:28:44 +08:00
|
|
|
mutex_unlock(&dev_priv->dev->struct_mutex);
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
|
2011-08-04 02:28:44 +08:00
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2011-08-04 02:28:44 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
static int
|
|
|
|
i915_cache_sharing_set(void *data, u64 val)
|
2011-08-04 02:28:44 +08:00
|
|
|
{
|
2013-03-11 05:10:06 +08:00
|
|
|
struct drm_device *dev = data;
|
2011-08-04 02:28:44 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 snpcr;
|
|
|
|
|
2012-08-09 21:07:01 +08:00
|
|
|
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
if (val > 3)
|
2011-08-04 02:28:44 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2013-03-11 05:10:06 +08:00
|
|
|
DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
|
2011-08-04 02:28:44 +08:00
|
|
|
|
|
|
|
/* Update the cache sharing policy here as well */
|
|
|
|
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
|
|
|
|
snpcr &= ~GEN6_MBC_SNPCR_MASK;
|
|
|
|
snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
|
|
|
|
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2013-03-11 05:10:06 +08:00
|
|
|
return 0;
|
2011-08-04 02:28:44 +08:00
|
|
|
}
|
|
|
|
|
2013-03-11 05:10:06 +08:00
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
|
|
|
|
i915_cache_sharing_get, i915_cache_sharing_set,
|
|
|
|
"%llu\n");
|
2011-08-04 02:28:44 +08:00
|
|
|
|
2015-04-04 09:13:17 +08:00
|
|
|
struct sseu_dev_status {
|
|
|
|
unsigned int slice_total;
|
|
|
|
unsigned int subslice_total;
|
|
|
|
unsigned int subslice_per_slice;
|
|
|
|
unsigned int eu_total;
|
|
|
|
unsigned int eu_per_subslice;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void cherryview_sseu_device_status(struct drm_device *dev,
|
|
|
|
struct sseu_dev_status *stat)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2015-08-22 01:45:27 +08:00
|
|
|
int ss_max = 2;
|
2015-04-04 09:13:17 +08:00
|
|
|
int ss;
|
|
|
|
u32 sig1[ss_max], sig2[ss_max];
|
|
|
|
|
|
|
|
sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
|
|
|
|
sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
|
|
|
|
sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
|
|
|
|
sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
|
|
|
|
|
|
|
|
for (ss = 0; ss < ss_max; ss++) {
|
|
|
|
unsigned int eu_cnt;
|
|
|
|
|
|
|
|
if (sig1[ss] & CHV_SS_PG_ENABLE)
|
|
|
|
/* skip disabled subslice */
|
|
|
|
continue;
|
|
|
|
|
|
|
|
stat->slice_total = 1;
|
|
|
|
stat->subslice_per_slice++;
|
|
|
|
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
|
|
|
|
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
|
|
|
|
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
|
|
|
|
((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
|
|
|
|
stat->eu_total += eu_cnt;
|
|
|
|
stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
|
|
|
|
}
|
|
|
|
stat->subslice_total = stat->subslice_per_slice;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen9_sseu_device_status(struct drm_device *dev,
|
|
|
|
struct sseu_dev_status *stat)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2015-04-04 09:13:18 +08:00
|
|
|
int s_max = 3, ss_max = 4;
|
2015-04-04 09:13:17 +08:00
|
|
|
int s, ss;
|
|
|
|
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
|
|
|
|
|
2015-04-04 09:13:18 +08:00
|
|
|
/* BXT has a single slice and at most 3 subslices. */
|
|
|
|
if (IS_BROXTON(dev)) {
|
|
|
|
s_max = 1;
|
|
|
|
ss_max = 3;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (s = 0; s < s_max; s++) {
|
|
|
|
s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
|
|
|
|
eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
|
|
|
|
eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
|
|
|
|
}
|
|
|
|
|
2015-04-04 09:13:17 +08:00
|
|
|
eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
|
|
|
|
GEN9_PGCTL_SSA_EU19_ACK |
|
|
|
|
GEN9_PGCTL_SSA_EU210_ACK |
|
|
|
|
GEN9_PGCTL_SSA_EU311_ACK;
|
|
|
|
eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
|
|
|
|
GEN9_PGCTL_SSB_EU19_ACK |
|
|
|
|
GEN9_PGCTL_SSB_EU210_ACK |
|
|
|
|
GEN9_PGCTL_SSB_EU311_ACK;
|
|
|
|
|
|
|
|
for (s = 0; s < s_max; s++) {
|
2015-04-04 09:13:18 +08:00
|
|
|
unsigned int ss_cnt = 0;
|
|
|
|
|
2015-04-04 09:13:17 +08:00
|
|
|
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
|
|
|
|
/* skip disabled slice */
|
|
|
|
continue;
|
|
|
|
|
|
|
|
stat->slice_total++;
|
2015-04-04 09:13:18 +08:00
|
|
|
|
2015-10-28 19:16:45 +08:00
|
|
|
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
|
2015-04-04 09:13:18 +08:00
|
|
|
ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
|
|
|
|
|
2015-04-04 09:13:17 +08:00
|
|
|
for (ss = 0; ss < ss_max; ss++) {
|
|
|
|
unsigned int eu_cnt;
|
|
|
|
|
2015-04-04 09:13:18 +08:00
|
|
|
if (IS_BROXTON(dev) &&
|
|
|
|
!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
|
|
|
|
/* skip disabled subslice */
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (IS_BROXTON(dev))
|
|
|
|
ss_cnt++;
|
|
|
|
|
2015-04-04 09:13:17 +08:00
|
|
|
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
|
|
|
|
eu_mask[ss%2]);
|
|
|
|
stat->eu_total += eu_cnt;
|
|
|
|
stat->eu_per_subslice = max(stat->eu_per_subslice,
|
|
|
|
eu_cnt);
|
|
|
|
}
|
2015-04-04 09:13:18 +08:00
|
|
|
|
|
|
|
stat->subslice_total += ss_cnt;
|
|
|
|
stat->subslice_per_slice = max(stat->subslice_per_slice,
|
|
|
|
ss_cnt);
|
2015-04-04 09:13:17 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-25 17:54:58 +08:00
|
|
|
static void broadwell_sseu_device_status(struct drm_device *dev,
|
|
|
|
struct sseu_dev_status *stat)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int s;
|
|
|
|
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
|
|
|
|
|
|
|
|
stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
|
|
|
|
|
|
|
|
if (stat->slice_total) {
|
|
|
|
stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
|
|
|
|
stat->subslice_total = stat->slice_total *
|
|
|
|
stat->subslice_per_slice;
|
|
|
|
stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
|
|
|
|
stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
|
|
|
|
|
|
|
|
/* subtract fused off EU(s) from enabled slice(s) */
|
|
|
|
for (s = 0; s < stat->slice_total; s++) {
|
|
|
|
u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
|
|
|
|
|
|
|
|
stat->eu_total -= hweight8(subslice_7eu);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-02-14 00:27:54 +08:00
|
|
|
static int i915_sseu_status(struct seq_file *m, void *unused)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
2015-04-04 09:13:17 +08:00
|
|
|
struct sseu_dev_status stat;
|
2015-02-14 00:27:54 +08:00
|
|
|
|
2015-09-25 17:54:58 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 8)
|
2015-02-14 00:27:54 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
seq_puts(m, "SSEU Device Info\n");
|
|
|
|
seq_printf(m, " Available Slice Total: %u\n",
|
|
|
|
INTEL_INFO(dev)->slice_total);
|
|
|
|
seq_printf(m, " Available Subslice Total: %u\n",
|
|
|
|
INTEL_INFO(dev)->subslice_total);
|
|
|
|
seq_printf(m, " Available Subslice Per Slice: %u\n",
|
|
|
|
INTEL_INFO(dev)->subslice_per_slice);
|
|
|
|
seq_printf(m, " Available EU Total: %u\n",
|
|
|
|
INTEL_INFO(dev)->eu_total);
|
|
|
|
seq_printf(m, " Available EU Per Subslice: %u\n",
|
|
|
|
INTEL_INFO(dev)->eu_per_subslice);
|
|
|
|
seq_printf(m, " Has Slice Power Gating: %s\n",
|
|
|
|
yesno(INTEL_INFO(dev)->has_slice_pg));
|
|
|
|
seq_printf(m, " Has Subslice Power Gating: %s\n",
|
|
|
|
yesno(INTEL_INFO(dev)->has_subslice_pg));
|
|
|
|
seq_printf(m, " Has EU Power Gating: %s\n",
|
|
|
|
yesno(INTEL_INFO(dev)->has_eu_pg));
|
|
|
|
|
2015-02-14 00:27:55 +08:00
|
|
|
seq_puts(m, "SSEU Device Status\n");
|
2015-04-04 09:13:17 +08:00
|
|
|
memset(&stat, 0, sizeof(stat));
|
2015-02-28 02:22:32 +08:00
|
|
|
if (IS_CHERRYVIEW(dev)) {
|
2015-04-04 09:13:17 +08:00
|
|
|
cherryview_sseu_device_status(dev, &stat);
|
2015-09-25 17:54:58 +08:00
|
|
|
} else if (IS_BROADWELL(dev)) {
|
|
|
|
broadwell_sseu_device_status(dev, &stat);
|
2015-04-04 09:13:18 +08:00
|
|
|
} else if (INTEL_INFO(dev)->gen >= 9) {
|
2015-04-04 09:13:17 +08:00
|
|
|
gen9_sseu_device_status(dev, &stat);
|
2015-02-14 00:27:55 +08:00
|
|
|
}
|
2015-04-04 09:13:17 +08:00
|
|
|
seq_printf(m, " Enabled Slice Total: %u\n",
|
|
|
|
stat.slice_total);
|
|
|
|
seq_printf(m, " Enabled Subslice Total: %u\n",
|
|
|
|
stat.subslice_total);
|
|
|
|
seq_printf(m, " Enabled Subslice Per Slice: %u\n",
|
|
|
|
stat.subslice_per_slice);
|
|
|
|
seq_printf(m, " Enabled EU Total: %u\n",
|
|
|
|
stat.eu_total);
|
|
|
|
seq_printf(m, " Enabled EU Per Subslice: %u\n",
|
|
|
|
stat.eu_per_subslice);
|
2015-02-14 00:27:55 +08:00
|
|
|
|
2015-02-14 00:27:54 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-04-26 02:25:56 +08:00
|
|
|
static int i915_forcewake_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2012-01-24 16:44:28 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2011-04-26 02:25:56 +08:00
|
|
|
return 0;
|
|
|
|
|
2015-01-16 17:34:35 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
2015-01-16 17:34:40 +08:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2011-04-26 02:25:56 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-04-17 05:07:40 +08:00
|
|
|
static int i915_forcewake_release(struct inode *inode, struct file *file)
|
2011-04-26 02:25:56 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = inode->i_private;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2012-01-24 16:44:28 +08:00
|
|
|
if (INTEL_INFO(dev)->gen < 6)
|
2011-04-26 02:25:56 +08:00
|
|
|
return 0;
|
|
|
|
|
2015-01-16 17:34:40 +08:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2015-01-16 17:34:35 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2011-04-26 02:25:56 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_forcewake_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_forcewake_open,
|
|
|
|
.release = i915_forcewake_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = minor->dev;
|
|
|
|
struct dentry *ent;
|
|
|
|
|
|
|
|
ent = debugfs_create_file("i915_forcewake_user",
|
2011-05-12 06:10:58 +08:00
|
|
|
S_IRUSR,
|
2011-04-26 02:25:56 +08:00
|
|
|
root, dev,
|
|
|
|
&i915_forcewake_fops);
|
2013-12-16 14:13:25 +08:00
|
|
|
if (!ent)
|
|
|
|
return -ENOMEM;
|
2011-04-26 02:25:56 +08:00
|
|
|
|
2011-05-12 06:10:58 +08:00
|
|
|
return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
|
2011-04-26 02:25:56 +08:00
|
|
|
}
|
|
|
|
|
2011-12-14 20:57:11 +08:00
|
|
|
static int i915_debugfs_create(struct dentry *root,
|
|
|
|
struct drm_minor *minor,
|
|
|
|
const char *name,
|
|
|
|
const struct file_operations *fops)
|
2011-08-04 02:28:44 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = minor->dev;
|
|
|
|
struct dentry *ent;
|
|
|
|
|
2011-12-14 20:57:11 +08:00
|
|
|
ent = debugfs_create_file(name,
|
2011-08-04 02:28:44 +08:00
|
|
|
S_IRUGO | S_IWUSR,
|
|
|
|
root, dev,
|
2011-12-14 20:57:11 +08:00
|
|
|
fops);
|
2013-12-16 14:13:25 +08:00
|
|
|
if (!ent)
|
|
|
|
return -ENOMEM;
|
2011-08-04 02:28:44 +08:00
|
|
|
|
2011-12-14 20:57:11 +08:00
|
|
|
return drm_add_fake_info_node(minor, ent, fops);
|
2011-08-04 02:28:44 +08:00
|
|
|
}
|
|
|
|
|
2013-10-18 02:09:56 +08:00
|
|
|
static const struct drm_info_list i915_debugfs_list[] = {
|
2011-01-14 03:06:50 +08:00
|
|
|
{"i915_capabilities", i915_capabilities, 0},
|
2010-09-30 18:46:12 +08:00
|
|
|
{"i915_gem_objects", i915_gem_object_info, 0},
|
2011-01-10 08:00:24 +08:00
|
|
|
{"i915_gem_gtt", i915_gem_gtt_info, 0},
|
2012-04-24 22:47:30 +08:00
|
|
|
{"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
|
2009-02-18 09:08:51 +08:00
|
|
|
{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
|
|
|
|
{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
|
2013-08-08 01:30:54 +08:00
|
|
|
{"i915_gem_stolen", i915_gem_stolen_list_info },
|
2010-09-02 00:47:52 +08:00
|
|
|
{"i915_gem_pageflip", i915_gem_pageflip_info, 0},
|
2009-02-18 09:08:50 +08:00
|
|
|
{"i915_gem_request", i915_gem_request_info, 0},
|
|
|
|
{"i915_gem_seqno", i915_gem_seqno_info, 0},
|
2009-02-11 22:26:38 +08:00
|
|
|
{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
|
2009-02-18 09:08:50 +08:00
|
|
|
{"i915_gem_interrupt", i915_interrupt_info, 0},
|
2010-12-04 19:30:53 +08:00
|
|
|
{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
|
|
|
|
{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
|
|
|
|
{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
|
2013-05-30 00:22:36 +08:00
|
|
|
{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
|
2014-12-12 04:13:08 +08:00
|
|
|
{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
|
2015-08-12 22:43:44 +08:00
|
|
|
{"i915_guc_info", i915_guc_info, 0},
|
2015-08-12 22:43:37 +08:00
|
|
|
{"i915_guc_load_status", i915_guc_load_status_info, 0},
|
2015-08-12 22:43:40 +08:00
|
|
|
{"i915_guc_log_dump", i915_guc_log_dump, 0},
|
2014-03-31 14:00:02 +08:00
|
|
|
{"i915_frequency_info", i915_frequency_info, 0},
|
2015-01-27 00:03:04 +08:00
|
|
|
{"i915_hangcheck_info", i915_hangcheck_info, 0},
|
2010-01-30 03:27:07 +08:00
|
|
|
{"i915_drpc_info", i915_drpc_info, 0},
|
2010-05-21 05:28:11 +08:00
|
|
|
{"i915_emon_status", i915_emon_status, 0},
|
2011-06-29 04:04:16 +08:00
|
|
|
{"i915_ring_freq_table", i915_ring_freq_table, 0},
|
2015-06-18 16:30:22 +08:00
|
|
|
{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
|
2010-02-06 04:42:41 +08:00
|
|
|
{"i915_fbc_status", i915_fbc_status, 0},
|
2013-06-01 03:33:24 +08:00
|
|
|
{"i915_ips_status", i915_ips_status, 0},
|
2010-02-06 04:47:35 +08:00
|
|
|
{"i915_sr_status", i915_sr_status, 0},
|
2010-08-19 23:09:23 +08:00
|
|
|
{"i915_opregion", i915_opregion, 0},
|
2015-12-15 19:17:12 +08:00
|
|
|
{"i915_vbt", i915_vbt, 0},
|
2010-08-26 05:45:57 +08:00
|
|
|
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
|
2011-03-20 09:14:29 +08:00
|
|
|
{"i915_context_status", i915_context_status, 0},
|
2014-08-07 20:24:26 +08:00
|
|
|
{"i915_dump_lrc", i915_dump_lrc, 0},
|
2014-08-07 20:23:20 +08:00
|
|
|
{"i915_execlists", i915_execlists, 0},
|
2015-01-16 17:34:42 +08:00
|
|
|
{"i915_forcewake_domains", i915_forcewake_domains, 0},
|
2011-12-14 20:57:16 +08:00
|
|
|
{"i915_swizzle_info", i915_swizzle_info, 0},
|
2012-02-10 00:15:49 +08:00
|
|
|
{"i915_ppgtt_info", i915_ppgtt_info, 0},
|
2013-07-05 02:02:07 +08:00
|
|
|
{"i915_llc", i915_llc, 0},
|
2013-07-12 05:44:59 +08:00
|
|
|
{"i915_edp_psr_status", i915_edp_psr_status, 0},
|
2014-01-24 23:36:17 +08:00
|
|
|
{"i915_sink_crc_eDP1", i915_sink_crc, 0},
|
2013-08-20 17:29:23 +08:00
|
|
|
{"i915_energy_uJ", i915_energy_uJ, 0},
|
2015-06-05 01:23:57 +08:00
|
|
|
{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
|
2013-11-25 23:15:35 +08:00
|
|
|
{"i915_power_domain_info", i915_power_domain_info, 0},
|
2015-10-27 20:47:01 +08:00
|
|
|
{"i915_dmc_info", i915_dmc_info, 0},
|
2014-02-08 04:48:15 +08:00
|
|
|
{"i915_display_info", i915_display_info, 0},
|
2014-07-01 00:53:42 +08:00
|
|
|
{"i915_semaphore_status", i915_semaphore_status, 0},
|
2014-06-26 03:01:53 +08:00
|
|
|
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
|
2014-05-12 13:22:27 +08:00
|
|
|
{"i915_dp_mst_info", i915_dp_mst_info, 0},
|
2014-08-30 23:50:59 +08:00
|
|
|
{"i915_wa_registers", i915_wa_registers, 0},
|
2014-11-05 01:06:51 +08:00
|
|
|
{"i915_ddb_info", i915_ddb_info, 0},
|
2015-02-14 00:27:54 +08:00
|
|
|
{"i915_sseu_status", i915_sseu_status, 0},
|
drm/i915: Add debugfs entry for DRRS
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
V5: [By Ram]: Rephrased to make it easy to understand.
And format is modified. [Rodrigo]
V6: [By Ram]: Modeset mutex are acquired for each crtc along with
renaming the Idleness detection states [Daniel]
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: dump full busy_frontbuffer_bits and remove the dubios
computed logical state of DRRS - debugfs is about what is fact,
developers should reach their own conclusion when debugging issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-03-03 23:23:10 +08:00
|
|
|
{"i915_drrs_status", i915_drrs_status, 0},
|
2015-04-07 23:20:32 +08:00
|
|
|
{"i915_rps_boost_info", i915_rps_boost_info, 0},
|
2009-02-18 09:08:50 +08:00
|
|
|
};
|
2009-07-02 10:26:52 +08:00
|
|
|
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
|
2009-02-18 09:08:50 +08:00
|
|
|
|
2013-10-18 02:09:56 +08:00
|
|
|
static const struct i915_debugfs_files {
|
2013-07-05 02:49:44 +08:00
|
|
|
const char *name;
|
|
|
|
const struct file_operations *fops;
|
|
|
|
} i915_debugfs_files[] = {
|
|
|
|
{"i915_wedged", &i915_wedged_fops},
|
|
|
|
{"i915_max_freq", &i915_max_freq_fops},
|
|
|
|
{"i915_min_freq", &i915_min_freq_fops},
|
|
|
|
{"i915_cache_sharing", &i915_cache_sharing_fops},
|
|
|
|
{"i915_ring_stop", &i915_ring_stop_fops},
|
2013-09-26 00:34:55 +08:00
|
|
|
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
|
|
|
|
{"i915_ring_test_irq", &i915_ring_test_irq_fops},
|
2013-07-05 02:49:44 +08:00
|
|
|
{"i915_gem_drop_caches", &i915_drop_caches_fops},
|
|
|
|
{"i915_error_state", &i915_error_state_fops},
|
|
|
|
{"i915_next_seqno", &i915_next_seqno_fops},
|
2013-10-16 01:55:36 +08:00
|
|
|
{"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
|
2014-01-22 20:36:08 +08:00
|
|
|
{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
|
|
|
|
{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
|
|
|
|
{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
|
2014-08-01 17:04:45 +08:00
|
|
|
{"i915_fbc_false_color", &i915_fbc_fc_fops},
|
2015-04-18 15:04:19 +08:00
|
|
|
{"i915_dp_test_data", &i915_displayport_test_data_fops},
|
|
|
|
{"i915_dp_test_type", &i915_displayport_test_type_fops},
|
|
|
|
{"i915_dp_test_active", &i915_displayport_test_active_fops}
|
2013-07-05 02:49:44 +08:00
|
|
|
};
|
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
void intel_display_crc_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-11-14 18:30:42 +08:00
|
|
|
enum pipe pipe;
|
2013-10-16 01:55:40 +08:00
|
|
|
|
2014-08-18 20:49:10 +08:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2013-11-14 18:30:42 +08:00
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
2013-10-16 01:55:40 +08:00
|
|
|
|
2013-10-21 21:29:30 +08:00
|
|
|
pipe_crc->opened = false;
|
|
|
|
spin_lock_init(&pipe_crc->lock);
|
2013-10-16 01:55:40 +08:00
|
|
|
init_waitqueue_head(&pipe_crc->wq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-02 10:26:52 +08:00
|
|
|
int i915_debugfs_init(struct drm_minor *minor)
|
2009-02-18 09:08:50 +08:00
|
|
|
{
|
2013-07-05 02:49:44 +08:00
|
|
|
int ret, i;
|
2009-10-14 05:20:20 +08:00
|
|
|
|
2011-04-26 02:25:56 +08:00
|
|
|
ret = i915_forcewake_create(minor->debugfs_root, minor);
|
2011-07-28 02:53:01 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-12-14 20:57:11 +08:00
|
|
|
|
2013-10-16 01:55:40 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
|
|
|
|
ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-07-05 02:49:44 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
|
|
|
|
ret = i915_debugfs_create(minor->debugfs_root, minor,
|
|
|
|
i915_debugfs_files[i].name,
|
|
|
|
i915_debugfs_files[i].fops);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2012-12-04 21:12:00 +08:00
|
|
|
|
2009-07-02 10:26:52 +08:00
|
|
|
return drm_debugfs_create_files(i915_debugfs_list,
|
|
|
|
I915_DEBUGFS_ENTRIES,
|
2009-02-18 09:08:50 +08:00
|
|
|
minor->debugfs_root, minor);
|
|
|
|
}
|
|
|
|
|
2009-07-02 10:26:52 +08:00
|
|
|
void i915_debugfs_cleanup(struct drm_minor *minor)
|
2009-02-18 09:08:50 +08:00
|
|
|
{
|
2013-07-05 02:49:44 +08:00
|
|
|
int i;
|
|
|
|
|
2009-07-02 10:26:52 +08:00
|
|
|
drm_debugfs_remove_files(i915_debugfs_list,
|
|
|
|
I915_DEBUGFS_ENTRIES, minor);
|
2013-10-16 01:55:40 +08:00
|
|
|
|
2011-04-26 02:25:56 +08:00
|
|
|
drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
|
|
|
|
1, minor);
|
2013-10-16 01:55:40 +08:00
|
|
|
|
2013-10-17 04:55:51 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
|
2013-10-16 01:55:40 +08:00
|
|
|
struct drm_info_list *info_list =
|
|
|
|
(struct drm_info_list *)&i915_pipe_crc_data[i];
|
|
|
|
|
|
|
|
drm_debugfs_remove_files(info_list, 1, minor);
|
|
|
|
}
|
|
|
|
|
2013-07-05 02:49:44 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
|
|
|
|
struct drm_info_list *info_list =
|
|
|
|
(struct drm_info_list *) i915_debugfs_files[i].fops;
|
|
|
|
|
|
|
|
drm_debugfs_remove_files(info_list, 1, minor);
|
|
|
|
}
|
2009-02-18 09:08:50 +08:00
|
|
|
}
|
2015-04-01 16:15:21 +08:00
|
|
|
|
|
|
|
struct dpcd_block {
|
|
|
|
/* DPCD dump start address. */
|
|
|
|
unsigned int offset;
|
|
|
|
/* DPCD dump end address, inclusive. If unset, .size will be used. */
|
|
|
|
unsigned int end;
|
|
|
|
/* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
|
|
|
|
size_t size;
|
|
|
|
/* Only valid for eDP. */
|
|
|
|
bool edp;
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct dpcd_block i915_dpcd_debug[] = {
|
|
|
|
{ .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
|
|
|
|
{ .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
|
|
|
|
{ .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
|
|
|
|
{ .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
|
|
|
|
{ .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
|
|
|
|
{ .offset = DP_SET_POWER },
|
|
|
|
{ .offset = DP_EDP_DPCD_REV },
|
|
|
|
{ .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
|
|
|
|
{ .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
|
|
|
|
{ .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
|
|
|
|
};
|
|
|
|
|
|
|
|
static int i915_dpcd_show(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_connector *connector = m->private;
|
|
|
|
struct intel_dp *intel_dp =
|
|
|
|
enc_to_intel_dp(&intel_attached_encoder(connector)->base);
|
|
|
|
uint8_t buf[16];
|
|
|
|
ssize_t err;
|
|
|
|
int i;
|
|
|
|
|
2015-05-15 18:09:21 +08:00
|
|
|
if (connector->status != connector_status_connected)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2015-04-01 16:15:21 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
|
|
|
|
const struct dpcd_block *b = &i915_dpcd_debug[i];
|
|
|
|
size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
|
|
|
|
|
|
|
|
if (b->edp &&
|
|
|
|
connector->connector_type != DRM_MODE_CONNECTOR_eDP)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* low tech for now */
|
|
|
|
if (WARN_ON(size > sizeof(buf)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
|
|
|
|
if (err <= 0) {
|
|
|
|
DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
|
|
|
|
size, b->offset, err);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
|
2015-04-16 18:34:06 +08:00
|
|
|
}
|
2015-04-01 16:15:21 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_dpcd_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
return single_open(file, i915_dpcd_show, inode->i_private);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations i915_dpcd_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = i915_dpcd_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_debugfs_connector_add - add i915 specific connector debugfs files
|
|
|
|
* @connector: pointer to a registered drm_connector
|
|
|
|
*
|
|
|
|
* Cleanup will be done by drm_connector_unregister() through a call to
|
|
|
|
* drm_debugfs_connector_remove().
|
|
|
|
*
|
|
|
|
* Returns 0 on success, negative error codes on error.
|
|
|
|
*/
|
|
|
|
int i915_debugfs_connector_add(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct dentry *root = connector->debugfs_entry;
|
|
|
|
|
|
|
|
/* The connector must have been registered beforehands. */
|
|
|
|
if (!root)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
|
|
|
|
connector->connector_type == DRM_MODE_CONNECTOR_eDP)
|
|
|
|
debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
|
|
|
|
&i915_dpcd_fops);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|