2015-12-15 08:58:26 +08:00
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author:Mark Yao <mark.yao@rock-chips.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ROCKCHIP_VOP_REG_H
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#define _ROCKCHIP_VOP_REG_H
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2015-12-15 09:57:13 +08:00
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/* rk3288 register definition */
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#define RK3288_REG_CFG_DONE 0x0000
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#define RK3288_VERSION_INFO 0x0004
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#define RK3288_SYS_CTRL 0x0008
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#define RK3288_SYS_CTRL1 0x000c
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#define RK3288_DSP_CTRL0 0x0010
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#define RK3288_DSP_CTRL1 0x0014
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#define RK3288_DSP_BG 0x0018
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#define RK3288_MCU_CTRL 0x001c
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#define RK3288_INTR_CTRL0 0x0020
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#define RK3288_INTR_CTRL1 0x0024
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#define RK3288_WIN0_CTRL0 0x0030
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#define RK3288_WIN0_CTRL1 0x0034
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#define RK3288_WIN0_COLOR_KEY 0x0038
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#define RK3288_WIN0_VIR 0x003c
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#define RK3288_WIN0_YRGB_MST 0x0040
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#define RK3288_WIN0_CBR_MST 0x0044
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#define RK3288_WIN0_ACT_INFO 0x0048
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#define RK3288_WIN0_DSP_INFO 0x004c
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#define RK3288_WIN0_DSP_ST 0x0050
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#define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
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#define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
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#define RK3288_WIN0_SCL_OFFSET 0x005c
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#define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
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#define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
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#define RK3288_WIN0_FADING_CTRL 0x0068
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2015-12-15 08:58:26 +08:00
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/* win1 register */
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2015-12-15 09:57:13 +08:00
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#define RK3288_WIN1_CTRL0 0x0070
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#define RK3288_WIN1_CTRL1 0x0074
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#define RK3288_WIN1_COLOR_KEY 0x0078
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#define RK3288_WIN1_VIR 0x007c
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#define RK3288_WIN1_YRGB_MST 0x0080
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#define RK3288_WIN1_CBR_MST 0x0084
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#define RK3288_WIN1_ACT_INFO 0x0088
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#define RK3288_WIN1_DSP_INFO 0x008c
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#define RK3288_WIN1_DSP_ST 0x0090
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#define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
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#define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
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#define RK3288_WIN1_SCL_OFFSET 0x009c
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#define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
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#define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
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#define RK3288_WIN1_FADING_CTRL 0x00a8
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2015-12-15 08:58:26 +08:00
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/* win2 register */
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2015-12-15 09:57:13 +08:00
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#define RK3288_WIN2_CTRL0 0x00b0
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#define RK3288_WIN2_CTRL1 0x00b4
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#define RK3288_WIN2_VIR0_1 0x00b8
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#define RK3288_WIN2_VIR2_3 0x00bc
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#define RK3288_WIN2_MST0 0x00c0
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#define RK3288_WIN2_DSP_INFO0 0x00c4
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#define RK3288_WIN2_DSP_ST0 0x00c8
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#define RK3288_WIN2_COLOR_KEY 0x00cc
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#define RK3288_WIN2_MST1 0x00d0
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#define RK3288_WIN2_DSP_INFO1 0x00d4
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#define RK3288_WIN2_DSP_ST1 0x00d8
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#define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
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#define RK3288_WIN2_MST2 0x00e0
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#define RK3288_WIN2_DSP_INFO2 0x00e4
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#define RK3288_WIN2_DSP_ST2 0x00e8
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#define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
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#define RK3288_WIN2_MST3 0x00f0
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#define RK3288_WIN2_DSP_INFO3 0x00f4
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#define RK3288_WIN2_DSP_ST3 0x00f8
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#define RK3288_WIN2_FADING_CTRL 0x00fc
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2015-12-15 08:58:26 +08:00
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/* win3 register */
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2015-12-15 09:57:13 +08:00
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#define RK3288_WIN3_CTRL0 0x0100
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#define RK3288_WIN3_CTRL1 0x0104
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#define RK3288_WIN3_VIR0_1 0x0108
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#define RK3288_WIN3_VIR2_3 0x010c
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#define RK3288_WIN3_MST0 0x0110
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#define RK3288_WIN3_DSP_INFO0 0x0114
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#define RK3288_WIN3_DSP_ST0 0x0118
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#define RK3288_WIN3_COLOR_KEY 0x011c
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#define RK3288_WIN3_MST1 0x0120
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#define RK3288_WIN3_DSP_INFO1 0x0124
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#define RK3288_WIN3_DSP_ST1 0x0128
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#define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
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#define RK3288_WIN3_MST2 0x0130
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#define RK3288_WIN3_DSP_INFO2 0x0134
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#define RK3288_WIN3_DSP_ST2 0x0138
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#define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
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#define RK3288_WIN3_MST3 0x0140
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#define RK3288_WIN3_DSP_INFO3 0x0144
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#define RK3288_WIN3_DSP_ST3 0x0148
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#define RK3288_WIN3_FADING_CTRL 0x014c
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2015-12-15 08:58:26 +08:00
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/* hwc register */
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2015-12-15 09:57:13 +08:00
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#define RK3288_HWC_CTRL0 0x0150
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#define RK3288_HWC_CTRL1 0x0154
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#define RK3288_HWC_MST 0x0158
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#define RK3288_HWC_DSP_ST 0x015c
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#define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
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#define RK3288_HWC_DST_ALPHA_CTRL 0x0164
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#define RK3288_HWC_FADING_CTRL 0x0168
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2015-12-15 08:58:26 +08:00
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/* post process register */
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2015-12-15 09:57:13 +08:00
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#define RK3288_POST_DSP_HACT_INFO 0x0170
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#define RK3288_POST_DSP_VACT_INFO 0x0174
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#define RK3288_POST_SCL_FACTOR_YRGB 0x0178
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#define RK3288_POST_SCL_CTRL 0x0180
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#define RK3288_POST_DSP_VACT_INFO_F1 0x0184
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#define RK3288_DSP_HTOTAL_HS_END 0x0188
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#define RK3288_DSP_HACT_ST_END 0x018c
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#define RK3288_DSP_VTOTAL_VS_END 0x0190
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#define RK3288_DSP_VACT_ST_END 0x0194
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#define RK3288_DSP_VS_ST_END_F1 0x0198
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#define RK3288_DSP_VACT_ST_END_F1 0x019c
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2015-12-15 08:58:26 +08:00
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/* register definition end */
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2015-12-15 09:57:13 +08:00
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/* rk3036 register definition */
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#define RK3036_SYS_CTRL 0x00
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#define RK3036_DSP_CTRL0 0x04
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#define RK3036_DSP_CTRL1 0x08
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#define RK3036_INT_STATUS 0x10
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#define RK3036_ALPHA_CTRL 0x14
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#define RK3036_WIN0_COLOR_KEY 0x18
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#define RK3036_WIN1_COLOR_KEY 0x1c
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#define RK3036_WIN0_YRGB_MST 0x20
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#define RK3036_WIN0_CBR_MST 0x24
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#define RK3036_WIN1_VIR 0x28
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#define RK3036_AXI_BUS_CTRL 0x2c
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#define RK3036_WIN0_VIR 0x30
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#define RK3036_WIN0_ACT_INFO 0x34
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#define RK3036_WIN0_DSP_INFO 0x38
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#define RK3036_WIN0_DSP_ST 0x3c
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#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
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#define RK3036_WIN0_SCL_FACTOR_CBR 0x44
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#define RK3036_WIN0_SCL_OFFSET 0x48
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#define RK3036_HWC_MST 0x58
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#define RK3036_HWC_DSP_ST 0x5c
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#define RK3036_DSP_HTOTAL_HS_END 0x6c
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#define RK3036_DSP_HACT_ST_END 0x70
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#define RK3036_DSP_VTOTAL_VS_END 0x74
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#define RK3036_DSP_VACT_ST_END 0x78
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#define RK3036_DSP_VS_ST_END_F1 0x7c
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#define RK3036_DSP_VACT_ST_END_F1 0x80
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#define RK3036_GATHER_TRANSFER 0x84
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#define RK3036_VERSION_INFO 0x94
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#define RK3036_REG_CFG_DONE 0x90
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#define RK3036_WIN1_MST 0xa0
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#define RK3036_WIN1_ACT_INFO 0xb4
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#define RK3036_WIN1_DSP_INFO 0xb8
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#define RK3036_WIN1_DSP_ST 0xbc
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#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
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#define RK3036_WIN1_SCL_OFFSET 0xc8
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#define RK3036_BCSH_CTRL 0xd0
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#define RK3036_BCSH_COLOR_BAR 0xd4
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#define RK3036_BCSH_BCS 0xd8
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#define RK3036_BCSH_H 0xdc
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#define RK3036_WIN1_LUT_ADDR 0x400
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#define RK3036_HWC_LUT_ADDR 0x800
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/* rk3036 register definition end */
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2016-04-20 14:18:16 +08:00
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/* rk3399 register definition */
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#define RK3399_REG_CFG_DONE 0x00000
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#define RK3399_VERSION_INFO 0x00004
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#define RK3399_SYS_CTRL 0x00008
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#define RK3399_SYS_CTRL1 0x0000c
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#define RK3399_DSP_CTRL0 0x00010
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#define RK3399_DSP_CTRL1 0x00014
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#define RK3399_DSP_BG 0x00018
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#define RK3399_MCU_CTRL 0x0001c
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#define RK3399_WB_CTRL0 0x00020
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#define RK3399_WB_CTRL1 0x00024
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#define RK3399_WB_YRGB_MST 0x00028
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#define RK3399_WB_CBR_MST 0x0002c
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#define RK3399_WIN0_CTRL0 0x00030
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#define RK3399_WIN0_CTRL1 0x00034
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#define RK3399_WIN0_COLOR_KEY 0x00038
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#define RK3399_WIN0_VIR 0x0003c
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#define RK3399_WIN0_YRGB_MST 0x00040
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#define RK3399_WIN0_CBR_MST 0x00044
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#define RK3399_WIN0_ACT_INFO 0x00048
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#define RK3399_WIN0_DSP_INFO 0x0004c
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#define RK3399_WIN0_DSP_ST 0x00050
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#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054
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#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058
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#define RK3399_WIN0_SCL_OFFSET 0x0005c
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#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060
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#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064
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#define RK3399_WIN0_FADING_CTRL 0x00068
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#define RK3399_WIN0_CTRL2 0x0006c
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#define RK3399_WIN1_CTRL0 0x00070
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#define RK3399_WIN1_CTRL1 0x00074
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#define RK3399_WIN1_COLOR_KEY 0x00078
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#define RK3399_WIN1_VIR 0x0007c
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#define RK3399_WIN1_YRGB_MST 0x00080
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#define RK3399_WIN1_CBR_MST 0x00084
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#define RK3399_WIN1_ACT_INFO 0x00088
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#define RK3399_WIN1_DSP_INFO 0x0008c
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#define RK3399_WIN1_DSP_ST 0x00090
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#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094
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#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098
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#define RK3399_WIN1_SCL_OFFSET 0x0009c
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#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0
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#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4
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#define RK3399_WIN1_FADING_CTRL 0x000a8
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#define RK3399_WIN1_CTRL2 0x000ac
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#define RK3399_WIN2_CTRL0 0x000b0
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#define RK3399_WIN2_CTRL1 0x000b4
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#define RK3399_WIN2_VIR0_1 0x000b8
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#define RK3399_WIN2_VIR2_3 0x000bc
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#define RK3399_WIN2_MST0 0x000c0
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#define RK3399_WIN2_DSP_INFO0 0x000c4
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#define RK3399_WIN2_DSP_ST0 0x000c8
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#define RK3399_WIN2_COLOR_KEY 0x000cc
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#define RK3399_WIN2_MST1 0x000d0
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#define RK3399_WIN2_DSP_INFO1 0x000d4
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#define RK3399_WIN2_DSP_ST1 0x000d8
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#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc
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#define RK3399_WIN2_MST2 0x000e0
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#define RK3399_WIN2_DSP_INFO2 0x000e4
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#define RK3399_WIN2_DSP_ST2 0x000e8
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#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec
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#define RK3399_WIN2_MST3 0x000f0
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#define RK3399_WIN2_DSP_INFO3 0x000f4
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#define RK3399_WIN2_DSP_ST3 0x000f8
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#define RK3399_WIN2_FADING_CTRL 0x000fc
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#define RK3399_WIN3_CTRL0 0x00100
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#define RK3399_WIN3_CTRL1 0x00104
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#define RK3399_WIN3_VIR0_1 0x00108
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#define RK3399_WIN3_VIR2_3 0x0010c
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#define RK3399_WIN3_MST0 0x00110
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#define RK3399_WIN3_DSP_INFO0 0x00114
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#define RK3399_WIN3_DSP_ST0 0x00118
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#define RK3399_WIN3_COLOR_KEY 0x0011c
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#define RK3399_WIN3_MST1 0x00120
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#define RK3399_WIN3_DSP_INFO1 0x00124
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#define RK3399_WIN3_DSP_ST1 0x00128
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#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c
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#define RK3399_WIN3_MST2 0x00130
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#define RK3399_WIN3_DSP_INFO2 0x00134
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#define RK3399_WIN3_DSP_ST2 0x00138
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#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c
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#define RK3399_WIN3_MST3 0x00140
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#define RK3399_WIN3_DSP_INFO3 0x00144
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#define RK3399_WIN3_DSP_ST3 0x00148
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#define RK3399_WIN3_FADING_CTRL 0x0014c
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#define RK3399_HWC_CTRL0 0x00150
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#define RK3399_HWC_CTRL1 0x00154
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#define RK3399_HWC_MST 0x00158
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#define RK3399_HWC_DSP_ST 0x0015c
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#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160
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#define RK3399_HWC_DST_ALPHA_CTRL 0x00164
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#define RK3399_HWC_FADING_CTRL 0x00168
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#define RK3399_HWC_RESERVED1 0x0016c
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#define RK3399_POST_DSP_HACT_INFO 0x00170
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#define RK3399_POST_DSP_VACT_INFO 0x00174
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#define RK3399_POST_SCL_FACTOR_YRGB 0x00178
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#define RK3399_POST_RESERVED 0x0017c
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#define RK3399_POST_SCL_CTRL 0x00180
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#define RK3399_POST_DSP_VACT_INFO_F1 0x00184
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#define RK3399_DSP_HTOTAL_HS_END 0x00188
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#define RK3399_DSP_HACT_ST_END 0x0018c
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#define RK3399_DSP_VTOTAL_VS_END 0x00190
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#define RK3399_DSP_VACT_ST_END 0x00194
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#define RK3399_DSP_VS_ST_END_F1 0x00198
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#define RK3399_DSP_VACT_ST_END_F1 0x0019c
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#define RK3399_PWM_CTRL 0x001a0
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#define RK3399_PWM_PERIOD_HPR 0x001a4
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#define RK3399_PWM_DUTY_LPR 0x001a8
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#define RK3399_PWM_CNT 0x001ac
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#define RK3399_BCSH_COLOR_BAR 0x001b0
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#define RK3399_BCSH_BCS 0x001b4
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#define RK3399_BCSH_H 0x001b8
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#define RK3399_BCSH_CTRL 0x001bc
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#define RK3399_CABC_CTRL0 0x001c0
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#define RK3399_CABC_CTRL1 0x001c4
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#define RK3399_CABC_CTRL2 0x001c8
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#define RK3399_CABC_CTRL3 0x001cc
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#define RK3399_CABC_GAUSS_LINE0_0 0x001d0
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#define RK3399_CABC_GAUSS_LINE0_1 0x001d4
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#define RK3399_CABC_GAUSS_LINE1_0 0x001d8
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#define RK3399_CABC_GAUSS_LINE1_1 0x001dc
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#define RK3399_CABC_GAUSS_LINE2_0 0x001e0
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#define RK3399_CABC_GAUSS_LINE2_1 0x001e4
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#define RK3399_FRC_LOWER01_0 0x001e8
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#define RK3399_FRC_LOWER01_1 0x001ec
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#define RK3399_FRC_LOWER10_0 0x001f0
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#define RK3399_FRC_LOWER10_1 0x001f4
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#define RK3399_FRC_LOWER11_0 0x001f8
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#define RK3399_FRC_LOWER11_1 0x001fc
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#define RK3399_AFBCD0_CTRL 0x00200
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#define RK3399_AFBCD0_HDR_PTR 0x00204
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#define RK3399_AFBCD0_PIC_SIZE 0x00208
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#define RK3399_AFBCD0_STATUS 0x0020c
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#define RK3399_AFBCD1_CTRL 0x00220
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#define RK3399_AFBCD1_HDR_PTR 0x00224
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#define RK3399_AFBCD1_PIC_SIZE 0x00228
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#define RK3399_AFBCD1_STATUS 0x0022c
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#define RK3399_AFBCD2_CTRL 0x00240
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#define RK3399_AFBCD2_HDR_PTR 0x00244
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#define RK3399_AFBCD2_PIC_SIZE 0x00248
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#define RK3399_AFBCD2_STATUS 0x0024c
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#define RK3399_AFBCD3_CTRL 0x00260
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#define RK3399_AFBCD3_HDR_PTR 0x00264
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#define RK3399_AFBCD3_PIC_SIZE 0x00268
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#define RK3399_AFBCD3_STATUS 0x0026c
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#define RK3399_INTR_EN0 0x00280
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#define RK3399_INTR_CLEAR0 0x00284
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#define RK3399_INTR_STATUS0 0x00288
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#define RK3399_INTR_RAW_STATUS0 0x0028c
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#define RK3399_INTR_EN1 0x00290
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#define RK3399_INTR_CLEAR1 0x00294
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#define RK3399_INTR_STATUS1 0x00298
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#define RK3399_INTR_RAW_STATUS1 0x0029c
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#define RK3399_LINE_FLAG 0x002a0
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#define RK3399_VOP_STATUS 0x002a4
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#define RK3399_BLANKING_VALUE 0x002a8
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#define RK3399_MCU_BYPASS_PORT 0x002ac
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#define RK3399_WIN0_DSP_BG 0x002b0
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#define RK3399_WIN1_DSP_BG 0x002b4
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#define RK3399_WIN2_DSP_BG 0x002b8
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#define RK3399_WIN3_DSP_BG 0x002bc
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#define RK3399_YUV2YUV_WIN 0x002c0
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#define RK3399_YUV2YUV_POST 0x002c4
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#define RK3399_AUTO_GATING_EN 0x002cc
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#define RK3399_WIN0_CSC_COE 0x003a0
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#define RK3399_WIN1_CSC_COE 0x003c0
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#define RK3399_WIN2_CSC_COE 0x003e0
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#define RK3399_WIN3_CSC_COE 0x00400
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#define RK3399_HWC_CSC_COE 0x00420
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#define RK3399_BCSH_R2Y_CSC_COE 0x00440
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#define RK3399_BCSH_Y2R_CSC_COE 0x00460
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#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480
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#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0
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#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0
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#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0
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#define RK3399_WIN0_YUV2YUV_3X3 0x00500
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#define RK3399_WIN0_YUV2YUV_R2Y 0x00520
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#define RK3399_WIN1_YUV2YUV_Y2R 0x00540
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#define RK3399_WIN1_YUV2YUV_3X3 0x00560
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#define RK3399_WIN1_YUV2YUV_R2Y 0x00580
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#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0
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#define RK3399_WIN2_YUV2YUV_3X3 0x005c0
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#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0
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#define RK3399_WIN3_YUV2YUV_Y2R 0x00600
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#define RK3399_WIN3_YUV2YUV_3X3 0x00620
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#define RK3399_WIN3_YUV2YUV_R2Y 0x00640
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#define RK3399_WIN2_LUT_ADDR 0x01000
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#define RK3399_WIN3_LUT_ADDR 0x01400
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#define RK3399_HWC_LUT_ADDR 0x01800
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#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00
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#define RK3399_GAMMA_LUT_ADDR 0x02000
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/* rk3399 register definition end */
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2015-12-15 08:58:26 +08:00
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#endif /* _ROCKCHIP_VOP_REG_H */
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