2015-05-16 01:04:04 +08:00
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/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "dsi_pll.h"
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#include "dsi.xml.h"
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/*
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* DSI PLL 28nm - clock diagram (eg: DSI0):
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*
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* dsi0analog_postdiv_clk
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* | dsi0indirect_path_div2_clk
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* | |
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* +------+ | +----+ | |\ dsi0byte_mux
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* dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ |
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* | +------+ +----+ | m| | +----+
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* | | u|--o--| /4 |-- dsi0pllbyte
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* | | x| +----+
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* o--------------------------| /
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* | |/
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* | +------+
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* o----------| DIV3 |------------------------- dsi0pll
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* +------+
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*/
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#define POLL_MAX_READS 10
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#define POLL_TIMEOUT_US 50
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#define NUM_PROVIDED_CLKS 2
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#define VCO_REF_CLK_RATE 19200000
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#define VCO_MIN_RATE 350000000
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#define VCO_MAX_RATE 750000000
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#define DSI_BYTE_PLL_CLK 0
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#define DSI_PIXEL_PLL_CLK 1
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#define LPFR_LUT_SIZE 10
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struct lpfr_cfg {
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unsigned long vco_rate;
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u32 resistance;
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};
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/* Loop filter resistance: */
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static const struct lpfr_cfg lpfr_lut[LPFR_LUT_SIZE] = {
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{ 479500000, 8 },
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{ 480000000, 11 },
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{ 575500000, 8 },
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{ 576000000, 12 },
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{ 610500000, 8 },
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{ 659500000, 9 },
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{ 671500000, 10 },
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{ 672000000, 14 },
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{ 708500000, 10 },
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{ 750000000, 11 },
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};
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struct pll_28nm_cached_state {
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unsigned long vco_rate;
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u8 postdiv3;
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u8 postdiv1;
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u8 byte_mux;
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};
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struct dsi_pll_28nm {
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struct msm_dsi_pll base;
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int id;
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struct platform_device *pdev;
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void __iomem *mmio;
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int vco_delay;
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/* private clocks: */
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struct clk *clks[NUM_DSI_CLOCKS_MAX];
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u32 num_clks;
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/* clock-provider: */
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struct clk *provided_clks[NUM_PROVIDED_CLKS];
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struct clk_onecell_data clk_data;
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struct pll_28nm_cached_state cached_state;
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};
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#define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
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static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
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u32 nb_tries, u32 timeout_us)
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{
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bool pll_locked = false;
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u32 val;
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while (nb_tries--) {
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val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
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pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
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if (pll_locked)
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break;
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udelay(timeout_us);
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}
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DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
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return pll_locked;
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}
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static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
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{
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void __iomem *base = pll_28nm->mmio;
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/*
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* Add HW recommended delays after toggling the software
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* reset bit off and back on.
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*/
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pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
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DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1);
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pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
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}
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/*
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* Clock Callbacks
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*/
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static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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struct device *dev = &pll_28nm->pdev->dev;
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void __iomem *base = pll_28nm->mmio;
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unsigned long div_fbx1000, gen_vco_clk;
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u32 refclk_cfg, frac_n_mode, frac_n_value;
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u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
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u32 cal_cfg10, cal_cfg11;
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u32 rem;
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int i;
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VERB("rate=%lu, parent's=%lu", rate, parent_rate);
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/* Force postdiv2 to be div-4 */
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pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
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/* Configure the Loop filter resistance */
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for (i = 0; i < LPFR_LUT_SIZE; i++)
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if (rate <= lpfr_lut[i].vco_rate)
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break;
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if (i == LPFR_LUT_SIZE) {
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dev_err(dev, "unable to get loop filter resistance. vco=%lu\n",
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rate);
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return -EINVAL;
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}
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pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance);
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/* Loop filter capacitance values : c1 and c2 */
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pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
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pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
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rem = rate % VCO_REF_CLK_RATE;
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if (rem) {
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refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
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frac_n_mode = 1;
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div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
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gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
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} else {
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refclk_cfg = 0x0;
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frac_n_mode = 0;
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div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
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gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
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}
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DBG("refclk_cfg = %d", refclk_cfg);
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rem = div_fbx1000 % 1000;
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frac_n_value = (rem << 16) / 1000;
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DBG("div_fb = %lu", div_fbx1000);
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DBG("frac_n_value = %d", frac_n_value);
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DBG("Generated VCO Clock: %lu", gen_vco_clk);
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rem = 0;
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sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
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sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
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if (frac_n_mode) {
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sdm_cfg0 = 0x0;
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sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0);
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sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(
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(u32)(((div_fbx1000 / 1000) & 0x3f) - 1));
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sdm_cfg3 = frac_n_value >> 8;
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sdm_cfg2 = frac_n_value & 0xff;
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} else {
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sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP;
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sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(
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(u32)(((div_fbx1000 / 1000) & 0x3f) - 1));
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sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0);
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sdm_cfg2 = 0;
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sdm_cfg3 = 0;
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}
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DBG("sdm_cfg0=%d", sdm_cfg0);
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DBG("sdm_cfg1=%d", sdm_cfg1);
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DBG("sdm_cfg2=%d", sdm_cfg2);
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DBG("sdm_cfg3=%d", sdm_cfg3);
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cal_cfg11 = (u32)(gen_vco_clk / (256 * 1000000));
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cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000);
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DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
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pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
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pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
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pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
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DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2));
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pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
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DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3));
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pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
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/* Add hardware recommended delay for correct PLL configuration */
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if (pll_28nm->vco_delay)
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udelay(pll_28nm->vco_delay);
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pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
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pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
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pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
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pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff);
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pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff);
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pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
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return 0;
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}
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static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
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{
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struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
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POLL_TIMEOUT_US);
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}
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static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
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struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
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void __iomem *base = pll_28nm->mmio;
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u32 sdm0, doubler, sdm_byp_div;
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u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
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u32 ref_clk = VCO_REF_CLK_RATE;
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unsigned long vco_rate;
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VERB("parent_rate=%lu", parent_rate);
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/* Check to see if the ref clk doubler is enabled */
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doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
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DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
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ref_clk += (doubler * VCO_REF_CLK_RATE);
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/* see if it is integer mode or sdm mode */
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sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
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if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) {
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/* integer mode */
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sdm_byp_div = FIELD(
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pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
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DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1;
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vco_rate = ref_clk * sdm_byp_div;
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} else {
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/* sdm mode */
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sdm_dc_off = FIELD(
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pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
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DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET);
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DBG("sdm_dc_off = %d", sdm_dc_off);
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sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
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DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0);
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sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
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DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8);
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sdm_freq_seed = (sdm3 << 8) | sdm2;
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DBG("sdm_freq_seed = %d", sdm_freq_seed);
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vco_rate = (ref_clk * (sdm_dc_off + 1)) +
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mult_frac(ref_clk, sdm_freq_seed, BIT(16));
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DBG("vco rate = %lu", vco_rate);
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}
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DBG("returning vco rate = %lu", vco_rate);
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return vco_rate;
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}
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static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
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.round_rate = msm_dsi_pll_helper_clk_round_rate,
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.set_rate = dsi_pll_28nm_clk_set_rate,
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.recalc_rate = dsi_pll_28nm_clk_recalc_rate,
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.prepare = msm_dsi_pll_helper_clk_prepare,
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.unprepare = msm_dsi_pll_helper_clk_unprepare,
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.is_enabled = dsi_pll_28nm_clk_is_enabled,
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};
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/*
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* PLL Callbacks
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*/
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static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
struct device *dev = &pll_28nm->pdev->dev;
|
|
|
|
void __iomem *base = pll_28nm->mmio;
|
|
|
|
u32 max_reads = 5, timeout_us = 100;
|
|
|
|
bool locked;
|
|
|
|
u32 val;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DBG("id=%d", pll_28nm->id);
|
|
|
|
|
|
|
|
pll_28nm_software_reset(pll_28nm);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PLL power up sequence.
|
|
|
|
* Add necessary delays recommended by hardware.
|
|
|
|
*/
|
|
|
|
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
|
|
|
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
/* DSI Uniphy lock detect setting */
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
|
|
|
|
0x0c, 100);
|
|
|
|
pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
|
|
|
|
|
|
|
|
/* poll for PLL ready status */
|
|
|
|
locked = pll_28nm_poll_for_ready(pll_28nm,
|
|
|
|
max_reads, timeout_us);
|
|
|
|
if (locked)
|
|
|
|
break;
|
|
|
|
|
|
|
|
pll_28nm_software_reset(pll_28nm);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PLL power up sequence.
|
|
|
|
* Add necessary delays recommended by hardware.
|
|
|
|
*/
|
|
|
|
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
|
|
|
|
|
|
|
|
val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(!locked))
|
|
|
|
dev_err(dev, "DSI PLL lock failed\n");
|
|
|
|
else
|
|
|
|
DBG("DSI PLL Lock success");
|
|
|
|
|
|
|
|
return locked ? 0 : -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
struct device *dev = &pll_28nm->pdev->dev;
|
|
|
|
void __iomem *base = pll_28nm->mmio;
|
|
|
|
bool locked;
|
|
|
|
u32 max_reads = 10, timeout_us = 50;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
DBG("id=%d", pll_28nm->id);
|
|
|
|
|
|
|
|
pll_28nm_software_reset(pll_28nm);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PLL power up sequence.
|
|
|
|
* Add necessary delays recommended by hardware.
|
|
|
|
*/
|
|
|
|
pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500);
|
|
|
|
|
|
|
|
val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
|
|
|
|
pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
|
|
|
|
pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
|
|
|
|
|
|
|
|
val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B |
|
|
|
|
DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
|
|
|
|
pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
|
|
|
|
|
|
|
|
/* DSI PLL toggle lock detect setting */
|
|
|
|
pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500);
|
|
|
|
pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);
|
|
|
|
|
|
|
|
locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
|
|
|
|
|
|
|
|
if (unlikely(!locked))
|
|
|
|
dev_err(dev, "DSI PLL lock failed\n");
|
|
|
|
else
|
|
|
|
DBG("DSI PLL lock success");
|
|
|
|
|
|
|
|
return locked ? 0 : -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
|
|
|
|
DBG("id=%d", pll_28nm->id);
|
|
|
|
pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
|
|
|
|
void __iomem *base = pll_28nm->mmio;
|
|
|
|
|
|
|
|
cached_state->postdiv3 =
|
|
|
|
pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
|
|
|
|
cached_state->postdiv1 =
|
|
|
|
pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
|
|
|
|
cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
|
2015-07-31 08:20:57 +08:00
|
|
|
cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
|
2015-05-16 01:04:04 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
|
|
|
|
void __iomem *base = pll_28nm->mmio;
|
|
|
|
int ret;
|
|
|
|
|
2015-07-03 22:09:46 +08:00
|
|
|
ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
|
|
|
|
cached_state->vco_rate, 0);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pll_28nm->pdev->dev,
|
|
|
|
"restore vco rate failed. ret=%d\n", ret);
|
|
|
|
return ret;
|
2015-05-16 01:04:04 +08:00
|
|
|
}
|
|
|
|
|
2015-07-03 22:09:46 +08:00
|
|
|
pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
|
|
|
|
cached_state->postdiv3);
|
|
|
|
pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
|
|
|
|
cached_state->postdiv1);
|
|
|
|
pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
|
|
|
|
cached_state->byte_mux);
|
|
|
|
|
2015-05-16 01:04:04 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
|
|
|
|
struct clk **byte_clk_provider,
|
|
|
|
struct clk **pixel_clk_provider)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
|
|
|
|
if (byte_clk_provider)
|
|
|
|
*byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
|
|
|
|
if (pixel_clk_provider)
|
|
|
|
*pixel_clk_provider =
|
|
|
|
pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
|
|
|
|
pll_28nm->clks, pll_28nm->num_clks);
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_PROVIDED_CLKS; i++)
|
|
|
|
pll_28nm->provided_clks[i] = NULL;
|
|
|
|
|
|
|
|
pll_28nm->num_clks = 0;
|
|
|
|
pll_28nm->clk_data.clks = NULL;
|
|
|
|
pll_28nm->clk_data.clk_num = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
|
|
|
|
{
|
|
|
|
char clk_name[32], parent1[32], parent2[32], vco_name[32];
|
|
|
|
struct clk_init_data vco_init = {
|
|
|
|
.parent_names = (const char *[]){ "xo" },
|
|
|
|
.num_parents = 1,
|
|
|
|
.name = vco_name,
|
2016-10-27 14:27:15 +08:00
|
|
|
.flags = CLK_IGNORE_UNUSED,
|
2015-05-16 01:04:04 +08:00
|
|
|
.ops = &clk_ops_dsi_pll_28nm_vco,
|
|
|
|
};
|
|
|
|
struct device *dev = &pll_28nm->pdev->dev;
|
|
|
|
struct clk **clks = pll_28nm->clks;
|
|
|
|
struct clk **provided_clks = pll_28nm->provided_clks;
|
|
|
|
int num = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
DBG("%d", pll_28nm->id);
|
|
|
|
|
|
|
|
snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
|
|
|
|
pll_28nm->base.clk_hw.init = &vco_init;
|
|
|
|
clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
|
|
|
|
|
|
|
|
snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
|
|
|
|
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
|
|
|
|
clks[num++] = clk_register_divider(dev, clk_name,
|
|
|
|
parent1, CLK_SET_RATE_PARENT,
|
|
|
|
pll_28nm->mmio +
|
|
|
|
REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
|
|
|
|
0, 4, 0, NULL);
|
|
|
|
|
|
|
|
snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
|
|
|
|
snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
|
|
|
|
clks[num++] = clk_register_fixed_factor(dev, clk_name,
|
|
|
|
parent1, CLK_SET_RATE_PARENT,
|
|
|
|
1, 2);
|
|
|
|
|
|
|
|
snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
|
|
|
|
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
|
|
|
|
clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
|
|
|
|
clk_register_divider(dev, clk_name,
|
|
|
|
parent1, 0, pll_28nm->mmio +
|
|
|
|
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
|
|
|
|
0, 8, 0, NULL);
|
|
|
|
|
|
|
|
snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
|
|
|
|
snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
|
|
|
|
snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
|
|
|
|
clks[num++] = clk_register_mux(dev, clk_name,
|
|
|
|
(const char *[]){
|
|
|
|
parent1, parent2
|
|
|
|
}, 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
|
|
|
|
REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
|
|
|
|
|
|
|
|
snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
|
|
|
|
snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
|
|
|
|
clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
|
|
|
|
clk_register_fixed_factor(dev, clk_name,
|
|
|
|
parent1, CLK_SET_RATE_PARENT, 1, 4);
|
|
|
|
|
|
|
|
pll_28nm->num_clks = num;
|
|
|
|
|
|
|
|
pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
|
|
|
|
pll_28nm->clk_data.clks = provided_clks;
|
|
|
|
|
|
|
|
ret = of_clk_add_provider(dev->of_node,
|
|
|
|
of_clk_src_onecell_get, &pll_28nm->clk_data);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to register clk provider: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
|
|
|
|
enum msm_dsi_phy_type type, int id)
|
|
|
|
{
|
|
|
|
struct dsi_pll_28nm *pll_28nm;
|
|
|
|
struct msm_dsi_pll *pll;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!pdev)
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
|
|
|
|
pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);
|
|
|
|
if (!pll_28nm)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
pll_28nm->pdev = pdev;
|
|
|
|
pll_28nm->id = id;
|
|
|
|
|
|
|
|
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
|
|
|
|
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
|
|
|
|
dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
pll = &pll_28nm->base;
|
|
|
|
pll->min_rate = VCO_MIN_RATE;
|
|
|
|
pll->max_rate = VCO_MAX_RATE;
|
|
|
|
pll->get_provider = dsi_pll_28nm_get_provider;
|
|
|
|
pll->destroy = dsi_pll_28nm_destroy;
|
|
|
|
pll->disable_seq = dsi_pll_28nm_disable_seq;
|
|
|
|
pll->save_state = dsi_pll_28nm_save_state;
|
|
|
|
pll->restore_state = dsi_pll_28nm_restore_state;
|
|
|
|
|
|
|
|
if (type == MSM_DSI_PHY_28NM_HPM) {
|
|
|
|
pll_28nm->vco_delay = 1;
|
|
|
|
|
|
|
|
pll->en_seq_cnt = 3;
|
|
|
|
pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm;
|
|
|
|
pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm;
|
|
|
|
pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm;
|
|
|
|
} else if (type == MSM_DSI_PHY_28NM_LP) {
|
|
|
|
pll_28nm->vco_delay = 1000;
|
|
|
|
|
|
|
|
pll->en_seq_cnt = 1;
|
|
|
|
pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp;
|
|
|
|
} else {
|
|
|
|
dev_err(&pdev->dev, "phy type (%d) is not 28nm\n", type);
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = pll_28nm_register(pll_28nm);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
return pll;
|
|
|
|
}
|
|
|
|
|