88 lines
2.8 KiB
C
88 lines
2.8 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/gic.h>
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#include <asm/irq_cpu.h>
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#include <asm/setup.h>
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#include <asm/mips-boards/sead3int.h>
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#define SEAD_CONFIG_GIC_PRESENT_SHF 1
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#define SEAD_CONFIG_GIC_PRESENT_MSK (1 << SEAD_CONFIG_GIC_PRESENT_SHF)
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#define SEAD_CONFIG_BASE 0x1b100110
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#define SEAD_CONFIG_SIZE 4
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static unsigned long sead3_config_reg;
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/*
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* This table defines the setup for each external GIC interrupt. It is
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* indexed by interrupt number.
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*/
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#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
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static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
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{ 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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{ GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED, GIC_UNUSED },
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};
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int irq;
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irq = (fls(pending) - CAUSEB_IP - 1);
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if (irq >= 0)
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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else
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spurious_interrupt();
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}
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void __init arch_init_irq(void)
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{
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int i;
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if (!cpu_has_veic) {
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mips_cpu_irq_init();
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if (cpu_has_vint) {
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/* install generic handler */
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for (i = 0; i < 8; i++)
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set_vi_handler(i, plat_irq_dispatch);
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}
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}
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sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE,
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SEAD_CONFIG_SIZE);
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gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >>
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SEAD_CONFIG_GIC_PRESENT_SHF;
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pr_info("GIC: %spresent\n", (gic_present) ? "" : "not ");
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pr_info("EIC: %s\n",
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(current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");
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if (gic_present)
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gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
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ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
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}
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