2017-05-23 21:39:33 +08:00
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/*
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* Driver for Amlogic Meson SPI communication controller (SPICC)
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*
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* Copyright (C) BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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2020-03-12 21:31:24 +08:00
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#include <linux/clk-provider.h>
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2017-05-23 21:39:33 +08:00
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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2020-03-12 21:31:24 +08:00
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#include <linux/of_device.h>
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2017-05-23 21:39:33 +08:00
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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2022-10-21 21:31:26 +08:00
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#include <linux/pinctrl/consumer.h>
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2017-05-23 21:39:33 +08:00
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/*
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* The Meson SPICC controller could support DMA based transfers, but is not
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* implemented by the vendor code, and while having the registers documentation
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* it has never worked on the GXL Hardware.
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* The PIO mode is the only mode implemented, and due to badly designed HW :
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* - all transfers are cutted in 16 words burst because the FIFO hangs on
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* TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
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* FIFO max size chunk only
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* - CS management is dumb, and goes UP between every burst, so is really a
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* "Data Valid" signal than a Chip Select, GPIO link should be used instead
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* to have a CS go down over the full transfer
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*/
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#define SPICC_MAX_BURST 128
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/* Register Map */
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#define SPICC_RXDATA 0x00
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#define SPICC_TXDATA 0x04
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#define SPICC_CONREG 0x08
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#define SPICC_ENABLE BIT(0)
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#define SPICC_MODE_MASTER BIT(1)
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#define SPICC_XCH BIT(2)
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#define SPICC_SMC BIT(3)
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#define SPICC_POL BIT(4)
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#define SPICC_PHA BIT(5)
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#define SPICC_SSCTL BIT(6)
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#define SPICC_SSPOL BIT(7)
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#define SPICC_DRCTL_MASK GENMASK(9, 8)
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#define SPICC_DRCTL_IGNORE 0
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#define SPICC_DRCTL_FALLING 1
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#define SPICC_DRCTL_LOWLEVEL 2
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#define SPICC_CS_MASK GENMASK(13, 12)
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#define SPICC_DATARATE_MASK GENMASK(18, 16)
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#define SPICC_DATARATE_DIV4 0
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#define SPICC_DATARATE_DIV8 1
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#define SPICC_DATARATE_DIV16 2
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#define SPICC_DATARATE_DIV32 3
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#define SPICC_BITLENGTH_MASK GENMASK(24, 19)
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#define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)
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#define SPICC_INTREG 0x0c
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#define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
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#define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
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#define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
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#define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
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#define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
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#define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
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#define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
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#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
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#define SPICC_DMAREG 0x10
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#define SPICC_DMA_ENABLE BIT(0)
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#define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
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#define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
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#define SPICC_READ_BURST_MASK GENMASK(14, 11)
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#define SPICC_WRITE_BURST_MASK GENMASK(18, 15)
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#define SPICC_DMA_URGENT BIT(19)
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#define SPICC_DMA_THREADID_MASK GENMASK(25, 20)
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#define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)
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#define SPICC_STATREG 0x14
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#define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
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#define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
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#define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
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#define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
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#define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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#define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
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#define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
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#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */
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#define SPICC_PERIODREG 0x18
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#define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */
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#define SPICC_TESTREG 0x1c
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#define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
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#define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
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#define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
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#define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
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#define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
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#define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
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#define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
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#define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
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2020-03-12 21:31:28 +08:00
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#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
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#define SPICC_MO_NO_DELAY 0
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#define SPICC_MO_DELAY_1_CYCLE 1
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#define SPICC_MO_DELAY_2_CYCLE 2
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#define SPICC_MO_DELAY_3_CYCLE 3
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#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
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#define SPICC_MI_NO_DELAY 0
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#define SPICC_MI_DELAY_1_CYCLE 1
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#define SPICC_MI_DELAY_2_CYCLE 2
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#define SPICC_MI_DELAY_3_CYCLE 3
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#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
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#define SPICC_CAP_AHEAD_2_CYCLE 0
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#define SPICC_CAP_AHEAD_1_CYCLE 1
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#define SPICC_CAP_NO_DELAY 2
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#define SPICC_CAP_DELAY_1_CYCLE 3
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2017-05-23 21:39:33 +08:00
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#define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
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#define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
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#define SPICC_DRADDR 0x20 /* Read Address of DMA */
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#define SPICC_DWADDR 0x24 /* Write Address of DMA */
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2020-03-12 21:31:24 +08:00
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#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
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2020-03-12 21:31:25 +08:00
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#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
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#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)
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#define SPICC_ENH_DATARATE_EN BIT(24)
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2020-03-12 21:31:24 +08:00
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#define SPICC_ENH_MOSI_OEN BIT(25)
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#define SPICC_ENH_CLK_OEN BIT(26)
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#define SPICC_ENH_CS_OEN BIT(27)
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#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
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#define SPICC_ENH_MAIN_CLK_AO BIT(29)
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2017-05-23 21:39:33 +08:00
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#define writel_bits_relaxed(mask, val, addr) \
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writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
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2020-03-12 21:31:24 +08:00
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struct meson_spicc_data {
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2020-03-12 21:31:26 +08:00
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unsigned int max_speed_hz;
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2020-03-12 21:31:27 +08:00
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unsigned int min_speed_hz;
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2020-03-12 21:31:29 +08:00
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unsigned int fifo_size;
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2020-03-12 21:31:24 +08:00
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bool has_oen;
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2020-03-12 21:31:25 +08:00
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bool has_enhance_clk_div;
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2020-03-12 21:31:31 +08:00
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bool has_pclk;
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2020-03-12 21:31:24 +08:00
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};
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2017-05-23 21:39:33 +08:00
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struct meson_spicc_device {
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struct spi_master *master;
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struct platform_device *pdev;
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void __iomem *base;
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struct clk *core;
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2020-03-12 21:31:31 +08:00
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struct clk *pclk;
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2022-08-11 21:44:45 +08:00
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struct clk_divider pow2_div;
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2020-03-12 21:31:25 +08:00
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struct clk *clk;
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2017-05-23 21:39:33 +08:00
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struct spi_message *message;
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struct spi_transfer *xfer;
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2022-10-26 15:58:28 +08:00
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struct completion done;
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2020-03-12 21:31:24 +08:00
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const struct meson_spicc_data *data;
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2017-05-23 21:39:33 +08:00
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u8 *tx_buf;
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u8 *rx_buf;
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unsigned int bytes_per_word;
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unsigned long tx_remain;
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unsigned long rx_remain;
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unsigned long xfer_remain;
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2022-10-21 21:31:26 +08:00
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_idle_high;
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struct pinctrl_state *pins_idle_low;
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2017-05-23 21:39:33 +08:00
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};
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2022-08-11 21:44:45 +08:00
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#define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
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2020-03-12 21:31:24 +08:00
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static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
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{
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u32 conf;
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2022-10-21 21:31:26 +08:00
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if (!spicc->data->has_oen) {
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/* Try to get pinctrl states for idle high/low */
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spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl,
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"idle-high");
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if (IS_ERR(spicc->pins_idle_high)) {
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dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n");
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spicc->pins_idle_high = NULL;
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}
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spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl,
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"idle-low");
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if (IS_ERR(spicc->pins_idle_low)) {
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dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n");
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spicc->pins_idle_low = NULL;
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}
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2020-03-12 21:31:24 +08:00
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return;
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2022-10-21 21:31:26 +08:00
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}
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2020-03-12 21:31:24 +08:00
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conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
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SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
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writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
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}
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2017-05-23 21:39:33 +08:00
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static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
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{
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return !!FIELD_GET(SPICC_TF,
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readl_relaxed(spicc->base + SPICC_STATREG));
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}
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static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
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{
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2020-03-12 21:31:29 +08:00
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return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
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2017-05-23 21:39:33 +08:00
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readl_relaxed(spicc->base + SPICC_STATREG));
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}
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static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
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{
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unsigned int bytes = spicc->bytes_per_word;
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unsigned int byte_shift = 0;
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u32 data = 0;
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u8 byte;
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while (bytes--) {
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byte = *spicc->tx_buf++;
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data |= (byte & 0xff) << byte_shift;
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byte_shift += 8;
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}
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spicc->tx_remain--;
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return data;
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}
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static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
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u32 data)
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{
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unsigned int bytes = spicc->bytes_per_word;
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unsigned int byte_shift = 0;
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u8 byte;
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while (bytes--) {
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byte = (data >> byte_shift) & 0xff;
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*spicc->rx_buf++ = byte;
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byte_shift += 8;
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}
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spicc->rx_remain--;
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}
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static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
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{
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/* Empty RX FIFO */
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while (spicc->rx_remain &&
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meson_spicc_rxready(spicc))
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meson_spicc_push_data(spicc,
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readl_relaxed(spicc->base + SPICC_RXDATA));
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}
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static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
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{
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/* Fill Up TX FIFO */
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while (spicc->tx_remain &&
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!meson_spicc_txfull(spicc))
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writel_relaxed(meson_spicc_pull_data(spicc),
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spicc->base + SPICC_TXDATA);
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}
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2020-03-12 21:31:29 +08:00
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static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
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2017-05-23 21:39:33 +08:00
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{
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2020-03-12 21:31:29 +08:00
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unsigned int burst_len = min_t(unsigned int,
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spicc->xfer_remain /
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spicc->bytes_per_word,
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spicc->data->fifo_size);
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2017-05-23 21:39:33 +08:00
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/* Setup Xfer variables */
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spicc->tx_remain = burst_len;
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spicc->rx_remain = burst_len;
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spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
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/* Setup burst length */
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writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
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FIELD_PREP(SPICC_BURSTLENGTH_MASK,
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2020-03-12 21:31:29 +08:00
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burst_len - 1),
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2017-05-23 21:39:33 +08:00
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spicc->base + SPICC_CONREG);
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/* Fill TX FIFO */
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meson_spicc_tx(spicc);
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}
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static irqreturn_t meson_spicc_irq(int irq, void *data)
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{
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struct meson_spicc_device *spicc = (void *) data;
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2020-03-12 21:31:29 +08:00
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writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
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2017-05-23 21:39:33 +08:00
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/* Empty RX FIFO */
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meson_spicc_rx(spicc);
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|
2020-03-12 21:31:29 +08:00
|
|
|
if (!spicc->xfer_remain) {
|
|
|
|
/* Disable all IRQs */
|
|
|
|
writel(0, spicc->base + SPICC_INTREG);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2022-10-26 15:58:28 +08:00
|
|
|
complete(&spicc->done);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
return IRQ_HANDLED;
|
2017-05-23 21:39:33 +08:00
|
|
|
}
|
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
/* Setup burst */
|
|
|
|
meson_spicc_setup_burst(spicc);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
/* Start burst */
|
|
|
|
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2020-03-12 21:31:28 +08:00
|
|
|
static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
|
|
|
|
{
|
|
|
|
u32 div, hz;
|
|
|
|
u32 mi_delay, cap_delay;
|
|
|
|
u32 conf;
|
|
|
|
|
|
|
|
if (spicc->data->has_enhance_clk_div) {
|
|
|
|
div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
|
|
|
|
readl_relaxed(spicc->base + SPICC_ENH_CTL0));
|
|
|
|
div++;
|
|
|
|
div <<= 1;
|
|
|
|
} else {
|
|
|
|
div = FIELD_GET(SPICC_DATARATE_MASK,
|
|
|
|
readl_relaxed(spicc->base + SPICC_CONREG));
|
|
|
|
div += 2;
|
|
|
|
div = 1 << div;
|
|
|
|
}
|
|
|
|
|
|
|
|
mi_delay = SPICC_MI_NO_DELAY;
|
|
|
|
cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
|
|
|
|
hz = clk_get_rate(spicc->clk);
|
|
|
|
|
|
|
|
if (hz >= 100000000)
|
|
|
|
cap_delay = SPICC_CAP_DELAY_1_CYCLE;
|
|
|
|
else if (hz >= 80000000)
|
|
|
|
cap_delay = SPICC_CAP_NO_DELAY;
|
|
|
|
else if (hz >= 40000000)
|
|
|
|
cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
|
|
|
|
else if (div >= 16)
|
|
|
|
mi_delay = SPICC_MI_DELAY_3_CYCLE;
|
|
|
|
else if (div >= 8)
|
|
|
|
mi_delay = SPICC_MI_DELAY_2_CYCLE;
|
|
|
|
else if (div >= 6)
|
|
|
|
mi_delay = SPICC_MI_DELAY_1_CYCLE;
|
|
|
|
|
|
|
|
conf = readl_relaxed(spicc->base + SPICC_TESTREG);
|
|
|
|
conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
|
|
|
|
| SPICC_MI_CAP_DELAY_MASK);
|
|
|
|
conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
|
|
|
|
conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
|
|
|
|
writel_relaxed(conf, spicc->base + SPICC_TESTREG);
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
u32 conf, conf_orig;
|
|
|
|
|
|
|
|
/* Read original configuration */
|
|
|
|
conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
|
|
|
|
|
|
|
|
/* Setup word width */
|
|
|
|
conf &= ~SPICC_BITLENGTH_MASK;
|
|
|
|
conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
|
|
|
|
(spicc->bytes_per_word << 3) - 1);
|
|
|
|
|
|
|
|
/* Ignore if unchanged */
|
|
|
|
if (conf != conf_orig)
|
|
|
|
writel_relaxed(conf, spicc->base + SPICC_CONREG);
|
2020-03-12 21:31:25 +08:00
|
|
|
|
|
|
|
clk_set_rate(spicc->clk, xfer->speed_hz);
|
2020-03-12 21:31:28 +08:00
|
|
|
|
|
|
|
meson_spicc_auto_io_delay(spicc);
|
2020-03-12 21:31:29 +08:00
|
|
|
|
|
|
|
writel_relaxed(0, spicc->base + SPICC_DMAREG);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
|
|
|
|
{
|
|
|
|
if (spicc->data->has_oen)
|
|
|
|
writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
|
|
|
|
SPICC_ENH_MAIN_CLK_AO,
|
|
|
|
spicc->base + SPICC_ENH_CTL0);
|
|
|
|
|
|
|
|
writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
|
|
|
|
spicc->base + SPICC_TESTREG);
|
|
|
|
|
|
|
|
while (meson_spicc_rxready(spicc))
|
2020-07-17 21:54:16 +08:00
|
|
|
readl_relaxed(spicc->base + SPICC_RXDATA);
|
2020-03-12 21:31:29 +08:00
|
|
|
|
|
|
|
if (spicc->data->has_oen)
|
|
|
|
writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
|
|
|
|
spicc->base + SPICC_ENH_CTL0);
|
2017-05-23 21:39:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_transfer_one(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
struct meson_spicc_device *spicc = spi_master_get_devdata(master);
|
2022-11-02 16:46:01 +08:00
|
|
|
uint64_t timeout;
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
/* Store current transfer */
|
|
|
|
spicc->xfer = xfer;
|
|
|
|
|
|
|
|
/* Setup transfer parameters */
|
|
|
|
spicc->tx_buf = (u8 *)xfer->tx_buf;
|
|
|
|
spicc->rx_buf = (u8 *)xfer->rx_buf;
|
|
|
|
spicc->xfer_remain = xfer->len;
|
|
|
|
|
|
|
|
/* Pre-calculate word size */
|
|
|
|
spicc->bytes_per_word =
|
|
|
|
DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
|
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
if (xfer->len % spicc->bytes_per_word)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
/* Setup transfer parameters */
|
|
|
|
meson_spicc_setup_xfer(spicc, xfer);
|
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
meson_spicc_reset_fifo(spicc);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
/* Setup burst */
|
|
|
|
meson_spicc_setup_burst(spicc);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2022-10-26 15:58:28 +08:00
|
|
|
/* Setup wait for completion */
|
|
|
|
reinit_completion(&spicc->done);
|
|
|
|
|
|
|
|
/* For each byte we wait for 8 cycles of the SPI clock */
|
|
|
|
timeout = 8LL * MSEC_PER_SEC * xfer->len;
|
|
|
|
do_div(timeout, xfer->speed_hz);
|
|
|
|
|
|
|
|
/* Add 10us delay between each fifo bursts */
|
|
|
|
timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;
|
|
|
|
|
|
|
|
/* Increase it twice and add 200 ms tolerance */
|
|
|
|
timeout += timeout + 200;
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
/* Start burst */
|
|
|
|
writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
|
|
|
|
|
|
|
|
/* Enable interrupts */
|
2020-03-12 21:31:29 +08:00
|
|
|
writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2022-10-26 15:58:28 +08:00
|
|
|
if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
|
|
|
return 0;
|
2017-05-23 21:39:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_prepare_message(struct spi_master *master,
|
|
|
|
struct spi_message *message)
|
|
|
|
{
|
|
|
|
struct meson_spicc_device *spicc = spi_master_get_devdata(master);
|
|
|
|
struct spi_device *spi = message->spi;
|
2022-08-11 21:44:45 +08:00
|
|
|
u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
/* Store current message */
|
|
|
|
spicc->message = message;
|
|
|
|
|
|
|
|
/* Enable Master */
|
|
|
|
conf |= SPICC_ENABLE;
|
|
|
|
conf |= SPICC_MODE_MASTER;
|
|
|
|
|
|
|
|
/* SMC = 0 */
|
|
|
|
|
|
|
|
/* Setup transfer mode */
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
conf |= SPICC_POL;
|
|
|
|
else
|
|
|
|
conf &= ~SPICC_POL;
|
|
|
|
|
2022-10-21 21:31:26 +08:00
|
|
|
if (!spicc->data->has_oen) {
|
|
|
|
if (spi->mode & SPI_CPOL) {
|
|
|
|
if (spicc->pins_idle_high)
|
|
|
|
pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high);
|
|
|
|
} else {
|
|
|
|
if (spicc->pins_idle_low)
|
|
|
|
pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
if (spi->mode & SPI_CPHA)
|
|
|
|
conf |= SPICC_PHA;
|
|
|
|
else
|
|
|
|
conf &= ~SPICC_PHA;
|
|
|
|
|
|
|
|
/* SSCTL = 0 */
|
|
|
|
|
|
|
|
if (spi->mode & SPI_CS_HIGH)
|
|
|
|
conf |= SPICC_SSPOL;
|
|
|
|
else
|
|
|
|
conf &= ~SPICC_SSPOL;
|
|
|
|
|
|
|
|
if (spi->mode & SPI_READY)
|
|
|
|
conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
|
|
|
|
else
|
|
|
|
conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
|
|
|
|
|
|
|
|
/* Select CS */
|
2023-03-11 01:32:03 +08:00
|
|
|
conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
/* Default 8bit word */
|
|
|
|
conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
|
|
|
|
|
|
|
|
writel_relaxed(conf, spicc->base + SPICC_CONREG);
|
|
|
|
|
|
|
|
/* Setup no wait cycles by default */
|
|
|
|
writel_relaxed(0, spicc->base + SPICC_PERIODREG);
|
|
|
|
|
2020-03-12 21:31:29 +08:00
|
|
|
writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_unprepare_transfer(struct spi_master *master)
|
|
|
|
{
|
|
|
|
struct meson_spicc_device *spicc = spi_master_get_devdata(master);
|
2022-08-11 21:44:45 +08:00
|
|
|
u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
/* Disable all IRQs */
|
|
|
|
writel(0, spicc->base + SPICC_INTREG);
|
|
|
|
|
|
|
|
device_reset_optional(&spicc->pdev->dev);
|
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
/* Set default configuration, keeping datarate field */
|
|
|
|
writel_relaxed(conf, spicc->base + SPICC_CONREG);
|
|
|
|
|
2022-10-21 21:31:26 +08:00
|
|
|
if (!spicc->data->has_oen)
|
|
|
|
pinctrl_select_default_state(&spicc->pdev->dev);
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_setup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
if (!spi->controller_state)
|
|
|
|
spi->controller_state = spi_master_get_devdata(spi->master);
|
|
|
|
|
2019-12-05 16:39:15 +08:00
|
|
|
return 0;
|
2017-05-23 21:39:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void meson_spicc_cleanup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
spi->controller_state = NULL;
|
|
|
|
}
|
|
|
|
|
2020-03-12 21:31:25 +08:00
|
|
|
/*
|
|
|
|
* The Clock Mux
|
|
|
|
* x-----------------x x------------x x------\
|
|
|
|
* |---| pow2 fixed div |---| pow2 div |----| |
|
|
|
|
* | x-----------------x x------------x | |
|
|
|
|
* src ---| | mux |-- out
|
|
|
|
* | x-----------------x x------------x | |
|
|
|
|
* |---| enh fixed div |---| enh div |0---| |
|
|
|
|
* x-----------------x x------------x x------/
|
|
|
|
*
|
|
|
|
* Clk path for GX series:
|
|
|
|
* src -> pow2 fixed div -> pow2 div -> out
|
|
|
|
*
|
|
|
|
* Clk path for AXG series:
|
|
|
|
* src -> pow2 fixed div -> pow2 div -> mux -> out
|
|
|
|
* src -> enh fixed div -> enh div -> mux -> out
|
2020-03-12 21:31:31 +08:00
|
|
|
*
|
|
|
|
* Clk path for G12A series:
|
|
|
|
* pclk -> pow2 fixed div -> pow2 div -> mux -> out
|
|
|
|
* pclk -> enh fixed div -> enh div -> mux -> out
|
2022-08-11 21:44:45 +08:00
|
|
|
*
|
|
|
|
* The pow2 divider is tied to the controller HW state, and the
|
|
|
|
* divider is only valid when the controller is initialized.
|
|
|
|
*
|
|
|
|
* A set of clock ops is added to make sure we don't read/set this
|
|
|
|
* clock rate while the controller is in an unknown state.
|
2020-03-12 21:31:25 +08:00
|
|
|
*/
|
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_divider *divider = to_clk_divider(hw);
|
|
|
|
struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
|
|
|
|
|
2022-09-08 20:18:03 +08:00
|
|
|
if (!spicc->master->cur_msg)
|
2022-08-11 21:44:45 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
return clk_divider_ops.recalc_rate(hw, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
|
|
|
|
struct clk_rate_request *req)
|
|
|
|
{
|
|
|
|
struct clk_divider *divider = to_clk_divider(hw);
|
|
|
|
struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
|
|
|
|
|
2022-09-08 20:18:03 +08:00
|
|
|
if (!spicc->master->cur_msg)
|
2022-08-11 21:44:45 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return clk_divider_ops.determine_rate(hw, req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_divider *divider = to_clk_divider(hw);
|
|
|
|
struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
|
|
|
|
|
2022-09-08 20:18:03 +08:00
|
|
|
if (!spicc->master->cur_msg)
|
2022-08-11 21:44:45 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return clk_divider_ops.set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
2022-09-22 12:08:07 +08:00
|
|
|
static const struct clk_ops meson_spicc_pow2_clk_ops = {
|
2022-08-11 21:44:45 +08:00
|
|
|
.recalc_rate = meson_spicc_pow2_recalc_rate,
|
|
|
|
.determine_rate = meson_spicc_pow2_determine_rate,
|
|
|
|
.set_rate = meson_spicc_pow2_set_rate,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
|
2020-03-12 21:31:25 +08:00
|
|
|
{
|
|
|
|
struct device *dev = &spicc->pdev->dev;
|
2022-08-11 21:44:45 +08:00
|
|
|
struct clk_fixed_factor *pow2_fixed_div;
|
2020-03-12 21:31:25 +08:00
|
|
|
struct clk_init_data init;
|
|
|
|
struct clk *clk;
|
|
|
|
struct clk_parent_data parent_data[2];
|
|
|
|
char name[64];
|
|
|
|
|
|
|
|
memset(&init, 0, sizeof(init));
|
|
|
|
memset(&parent_data, 0, sizeof(parent_data));
|
|
|
|
|
|
|
|
init.parent_data = parent_data;
|
|
|
|
|
|
|
|
/* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
|
|
|
|
|
|
|
|
pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
|
|
|
|
if (!pow2_fixed_div)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
|
|
|
|
init.name = name;
|
|
|
|
init.ops = &clk_fixed_factor_ops;
|
|
|
|
init.flags = 0;
|
2020-03-12 21:31:31 +08:00
|
|
|
if (spicc->data->has_pclk)
|
|
|
|
parent_data[0].hw = __clk_get_hw(spicc->pclk);
|
|
|
|
else
|
|
|
|
parent_data[0].hw = __clk_get_hw(spicc->core);
|
2020-03-12 21:31:25 +08:00
|
|
|
init.num_parents = 1;
|
|
|
|
|
|
|
|
pow2_fixed_div->mult = 1,
|
|
|
|
pow2_fixed_div->div = 4,
|
|
|
|
pow2_fixed_div->hw.init = &init;
|
|
|
|
|
|
|
|
clk = devm_clk_register(dev, &pow2_fixed_div->hw);
|
|
|
|
if (WARN_ON(IS_ERR(clk)))
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
|
|
|
|
init.name = name;
|
2022-08-11 21:44:45 +08:00
|
|
|
init.ops = &meson_spicc_pow2_clk_ops;
|
|
|
|
/*
|
|
|
|
* Set NOCACHE here to make sure we read the actual HW value
|
|
|
|
* since we reset the HW after each transfer.
|
|
|
|
*/
|
|
|
|
init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
|
2020-03-12 21:31:25 +08:00
|
|
|
parent_data[0].hw = &pow2_fixed_div->hw;
|
|
|
|
init.num_parents = 1;
|
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
spicc->pow2_div.shift = 16,
|
|
|
|
spicc->pow2_div.width = 3,
|
|
|
|
spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
|
|
|
|
spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
|
|
|
|
spicc->pow2_div.hw.init = &init;
|
2020-03-12 21:31:25 +08:00
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
|
|
|
|
if (WARN_ON(IS_ERR(spicc->clk)))
|
|
|
|
return PTR_ERR(spicc->clk);
|
2020-03-12 21:31:25 +08:00
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
|
|
|
|
{
|
|
|
|
struct device *dev = &spicc->pdev->dev;
|
|
|
|
struct clk_fixed_factor *enh_fixed_div;
|
|
|
|
struct clk_divider *enh_div;
|
|
|
|
struct clk_mux *mux;
|
|
|
|
struct clk_init_data init;
|
|
|
|
struct clk *clk;
|
|
|
|
struct clk_parent_data parent_data[2];
|
|
|
|
char name[64];
|
|
|
|
|
|
|
|
memset(&init, 0, sizeof(init));
|
|
|
|
memset(&parent_data, 0, sizeof(parent_data));
|
|
|
|
|
|
|
|
init.parent_data = parent_data;
|
2020-03-12 21:31:25 +08:00
|
|
|
|
|
|
|
/* algorithm for enh div: rate = freq / 2 / (N + 1) */
|
|
|
|
|
|
|
|
enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
|
|
|
|
if (!enh_fixed_div)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
|
|
|
|
init.name = name;
|
|
|
|
init.ops = &clk_fixed_factor_ops;
|
|
|
|
init.flags = 0;
|
2020-03-12 21:31:31 +08:00
|
|
|
if (spicc->data->has_pclk)
|
|
|
|
parent_data[0].hw = __clk_get_hw(spicc->pclk);
|
|
|
|
else
|
|
|
|
parent_data[0].hw = __clk_get_hw(spicc->core);
|
2020-03-12 21:31:25 +08:00
|
|
|
init.num_parents = 1;
|
|
|
|
|
|
|
|
enh_fixed_div->mult = 1,
|
|
|
|
enh_fixed_div->div = 2,
|
|
|
|
enh_fixed_div->hw.init = &init;
|
|
|
|
|
|
|
|
clk = devm_clk_register(dev, &enh_fixed_div->hw);
|
|
|
|
if (WARN_ON(IS_ERR(clk)))
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
|
|
|
|
enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
|
|
|
|
if (!enh_div)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
|
|
|
|
init.name = name;
|
|
|
|
init.ops = &clk_divider_ops;
|
|
|
|
init.flags = CLK_SET_RATE_PARENT;
|
|
|
|
parent_data[0].hw = &enh_fixed_div->hw;
|
|
|
|
init.num_parents = 1;
|
|
|
|
|
|
|
|
enh_div->shift = 16,
|
|
|
|
enh_div->width = 8,
|
|
|
|
enh_div->reg = spicc->base + SPICC_ENH_CTL0;
|
|
|
|
enh_div->hw.init = &init;
|
|
|
|
|
|
|
|
clk = devm_clk_register(dev, &enh_div->hw);
|
|
|
|
if (WARN_ON(IS_ERR(clk)))
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
|
|
|
|
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
|
|
|
|
if (!mux)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
|
|
|
|
init.name = name;
|
|
|
|
init.ops = &clk_mux_ops;
|
2022-08-11 21:44:45 +08:00
|
|
|
parent_data[0].hw = &spicc->pow2_div.hw;
|
2020-03-12 21:31:25 +08:00
|
|
|
parent_data[1].hw = &enh_div->hw;
|
|
|
|
init.num_parents = 2;
|
|
|
|
init.flags = CLK_SET_RATE_PARENT;
|
|
|
|
|
|
|
|
mux->mask = 0x1,
|
|
|
|
mux->shift = 24,
|
|
|
|
mux->reg = spicc->base + SPICC_ENH_CTL0;
|
|
|
|
mux->hw.init = &init;
|
|
|
|
|
|
|
|
spicc->clk = devm_clk_register(dev, &mux->hw);
|
|
|
|
if (WARN_ON(IS_ERR(spicc->clk)))
|
|
|
|
return PTR_ERR(spicc->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
static int meson_spicc_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct spi_master *master;
|
|
|
|
struct meson_spicc_device *spicc;
|
2020-03-12 21:31:31 +08:00
|
|
|
int ret, irq;
|
2017-05-23 21:39:33 +08:00
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
|
|
|
|
if (!master) {
|
|
|
|
dev_err(&pdev->dev, "master allocation failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
spicc = spi_master_get_devdata(master);
|
|
|
|
spicc->master = master;
|
|
|
|
|
2020-03-12 21:31:24 +08:00
|
|
|
spicc->data = of_device_get_match_data(&pdev->dev);
|
|
|
|
if (!spicc->data) {
|
|
|
|
dev_err(&pdev->dev, "failed to get match data\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out_master;
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
spicc->pdev = pdev;
|
|
|
|
platform_set_drvdata(pdev, spicc);
|
|
|
|
|
2022-10-26 15:58:28 +08:00
|
|
|
init_completion(&spicc->done);
|
|
|
|
|
2019-09-04 21:58:57 +08:00
|
|
|
spicc->base = devm_platform_ioremap_resource(pdev, 0);
|
2017-05-23 21:39:33 +08:00
|
|
|
if (IS_ERR(spicc->base)) {
|
|
|
|
dev_err(&pdev->dev, "io resource mapping failed\n");
|
|
|
|
ret = PTR_ERR(spicc->base);
|
|
|
|
goto out_master;
|
|
|
|
}
|
|
|
|
|
2020-03-12 21:31:25 +08:00
|
|
|
/* Set master mode and enable controller */
|
|
|
|
writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
|
|
|
|
spicc->base + SPICC_CONREG);
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
/* Disable all IRQs */
|
|
|
|
writel_relaxed(0, spicc->base + SPICC_INTREG);
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2022-01-26 19:04:47 +08:00
|
|
|
if (irq < 0) {
|
|
|
|
ret = irq;
|
|
|
|
goto out_master;
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
|
|
|
|
0, NULL, spicc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "irq request failed\n");
|
|
|
|
goto out_master;
|
|
|
|
}
|
|
|
|
|
|
|
|
spicc->core = devm_clk_get(&pdev->dev, "core");
|
|
|
|
if (IS_ERR(spicc->core)) {
|
|
|
|
dev_err(&pdev->dev, "core clock request failed\n");
|
|
|
|
ret = PTR_ERR(spicc->core);
|
|
|
|
goto out_master;
|
|
|
|
}
|
|
|
|
|
2020-03-12 21:31:31 +08:00
|
|
|
if (spicc->data->has_pclk) {
|
|
|
|
spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
|
|
if (IS_ERR(spicc->pclk)) {
|
|
|
|
dev_err(&pdev->dev, "pclk clock request failed\n");
|
|
|
|
ret = PTR_ERR(spicc->pclk);
|
|
|
|
goto out_master;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
ret = clk_prepare_enable(spicc->core);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "core clock enable failed\n");
|
|
|
|
goto out_master;
|
|
|
|
}
|
2020-03-12 21:31:31 +08:00
|
|
|
|
|
|
|
ret = clk_prepare_enable(spicc->pclk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "pclk clock enable failed\n");
|
2021-06-13 13:29:32 +08:00
|
|
|
goto out_core_clk;
|
2020-03-12 21:31:31 +08:00
|
|
|
}
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2022-10-21 21:31:26 +08:00
|
|
|
spicc->pinctrl = devm_pinctrl_get(&pdev->dev);
|
|
|
|
if (IS_ERR(spicc->pinctrl)) {
|
|
|
|
ret = PTR_ERR(spicc->pinctrl);
|
|
|
|
goto out_clk;
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
device_reset_optional(&pdev->dev);
|
|
|
|
|
|
|
|
master->num_chipselect = 4;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
|
|
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
|
|
|
|
master->bits_per_word_mask = SPI_BPW_MASK(32) |
|
|
|
|
SPI_BPW_MASK(24) |
|
|
|
|
SPI_BPW_MASK(16) |
|
|
|
|
SPI_BPW_MASK(8);
|
|
|
|
master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
|
2020-03-12 21:31:27 +08:00
|
|
|
master->min_speed_hz = spicc->data->min_speed_hz;
|
2020-03-12 21:31:31 +08:00
|
|
|
master->max_speed_hz = spicc->data->max_speed_hz;
|
2017-05-23 21:39:33 +08:00
|
|
|
master->setup = meson_spicc_setup;
|
|
|
|
master->cleanup = meson_spicc_cleanup;
|
|
|
|
master->prepare_message = meson_spicc_prepare_message;
|
|
|
|
master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
|
|
|
|
master->transfer_one = meson_spicc_transfer_one;
|
2019-12-05 16:39:15 +08:00
|
|
|
master->use_gpio_descriptors = true;
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2020-03-12 21:31:24 +08:00
|
|
|
meson_spicc_oen_enable(spicc);
|
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
ret = meson_spicc_pow2_clk_init(spicc);
|
2020-03-12 21:31:25 +08:00
|
|
|
if (ret) {
|
2022-08-11 21:44:45 +08:00
|
|
|
dev_err(&pdev->dev, "pow2 clock registration failed\n");
|
2021-06-13 13:29:16 +08:00
|
|
|
goto out_clk;
|
2020-03-12 21:31:25 +08:00
|
|
|
}
|
|
|
|
|
2022-08-11 21:44:45 +08:00
|
|
|
if (spicc->data->has_enhance_clk_div) {
|
|
|
|
ret = meson_spicc_enh_clk_init(spicc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "clock registration failed\n");
|
|
|
|
goto out_clk;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
2018-04-29 06:46:23 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "spi master registration failed\n");
|
|
|
|
goto out_clk;
|
|
|
|
}
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2018-04-29 06:46:23 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_clk:
|
2020-03-12 21:31:31 +08:00
|
|
|
clk_disable_unprepare(spicc->pclk);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2021-06-13 13:29:32 +08:00
|
|
|
out_core_clk:
|
|
|
|
clk_disable_unprepare(spicc->core);
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
out_master:
|
|
|
|
spi_master_put(master);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2023-03-04 01:19:48 +08:00
|
|
|
static void meson_spicc_remove(struct platform_device *pdev)
|
2017-05-23 21:39:33 +08:00
|
|
|
{
|
|
|
|
struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
/* Disable SPI */
|
|
|
|
writel(0, spicc->base + SPICC_CONREG);
|
|
|
|
|
|
|
|
clk_disable_unprepare(spicc->core);
|
2020-03-12 21:31:31 +08:00
|
|
|
clk_disable_unprepare(spicc->pclk);
|
2017-05-23 21:39:33 +08:00
|
|
|
|
2021-07-20 18:01:16 +08:00
|
|
|
spi_master_put(spicc->master);
|
2017-05-23 21:39:33 +08:00
|
|
|
}
|
|
|
|
|
2020-03-12 21:31:24 +08:00
|
|
|
static const struct meson_spicc_data meson_spicc_gx_data = {
|
2020-03-12 21:31:26 +08:00
|
|
|
.max_speed_hz = 30000000,
|
2020-03-12 21:31:27 +08:00
|
|
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.min_speed_hz = 325000,
|
2020-03-12 21:31:29 +08:00
|
|
|
.fifo_size = 16,
|
2020-03-12 21:31:24 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct meson_spicc_data meson_spicc_axg_data = {
|
2020-03-12 21:31:26 +08:00
|
|
|
.max_speed_hz = 80000000,
|
2020-03-12 21:31:27 +08:00
|
|
|
.min_speed_hz = 325000,
|
2020-03-12 21:31:29 +08:00
|
|
|
.fifo_size = 16,
|
2020-03-12 21:31:24 +08:00
|
|
|
.has_oen = true,
|
2020-03-12 21:31:25 +08:00
|
|
|
.has_enhance_clk_div = true,
|
2020-03-12 21:31:24 +08:00
|
|
|
};
|
|
|
|
|
2020-03-12 21:31:31 +08:00
|
|
|
static const struct meson_spicc_data meson_spicc_g12a_data = {
|
|
|
|
.max_speed_hz = 166666666,
|
|
|
|
.min_speed_hz = 50000,
|
|
|
|
.fifo_size = 15,
|
|
|
|
.has_oen = true,
|
|
|
|
.has_enhance_clk_div = true,
|
|
|
|
.has_pclk = true,
|
|
|
|
};
|
|
|
|
|
2017-05-23 21:39:33 +08:00
|
|
|
static const struct of_device_id meson_spicc_of_match[] = {
|
2020-03-12 21:31:24 +08:00
|
|
|
{
|
|
|
|
.compatible = "amlogic,meson-gx-spicc",
|
|
|
|
.data = &meson_spicc_gx_data,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "amlogic,meson-axg-spicc",
|
|
|
|
.data = &meson_spicc_axg_data,
|
|
|
|
},
|
2020-03-12 21:31:31 +08:00
|
|
|
{
|
|
|
|
.compatible = "amlogic,meson-g12a-spicc",
|
|
|
|
.data = &meson_spicc_g12a_data,
|
|
|
|
},
|
2017-05-23 21:39:33 +08:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
|
|
|
|
|
|
|
|
static struct platform_driver meson_spicc_driver = {
|
|
|
|
.probe = meson_spicc_probe,
|
2023-03-04 01:19:48 +08:00
|
|
|
.remove_new = meson_spicc_remove,
|
2017-05-23 21:39:33 +08:00
|
|
|
.driver = {
|
|
|
|
.name = "meson-spicc",
|
|
|
|
.of_match_table = of_match_ptr(meson_spicc_of_match),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(meson_spicc_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
|
|
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|