2018-09-08 19:07:33 +08:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
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* bindings for MediaTek SoC.
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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* Zhiyong Tao <zhiyong.tao@mediatek.com>
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* Hongzhou.Yang <hongzhou.yang@mediatek.com>
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*/
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2018-09-19 06:03:13 +08:00
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#include <linux/gpio/driver.h>
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2020-04-08 04:08:16 +08:00
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#include <linux/module.h>
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2018-09-08 19:07:33 +08:00
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include "pinctrl-paris.h"
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#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
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/* Custom pinconf parameters */
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#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
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#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
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#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
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#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
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#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
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2018-09-08 19:07:33 +08:00
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static const struct pinconf_generic_params mtk_custom_bindings[] = {
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{"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
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{"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
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{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
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{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
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{"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
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2018-09-08 19:07:33 +08:00
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};
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#ifdef CONFIG_DEBUG_FS
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static const struct pin_config_item mtk_conf_items[] = {
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PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
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PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
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PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
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PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
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PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
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2018-09-08 19:07:33 +08:00
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};
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#endif
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static const char * const mtk_gpio_functions[] = {
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"func0", "func1", "func2", "func3",
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"func4", "func5", "func6", "func7",
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"func8", "func9", "func10", "func11",
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"func12", "func13", "func14", "func15",
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};
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2022-03-08 18:09:53 +08:00
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/*
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* This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
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* and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
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*
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* The custom value encodes three hardware bits as follows:
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*
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* | Bits |
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* | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
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* ------------------------------------------------
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* | x | x | 0 | disabled, use standard drive strength
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* -------------------------------------
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* | 0 | 0 | 1 | 125 uA
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* | 0 | 1 | 1 | 250 uA
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* | 1 | 0 | 1 | 500 uA
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* | 1 | 1 | 1 | 1000 uA
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*/
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static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
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static int mtk_drv_adv_to_uA(int val)
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{
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/* This should never happen. */
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if (WARN_ON_ONCE(val < 0 || val > 7))
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return -EINVAL;
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/* Bit 0 simply enables this hardware part */
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if (!(val & BIT(0)))
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return -EINVAL;
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return mtk_drv_adv_uA[(val >> 1)];
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}
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static int mtk_drv_uA_to_adv(int val)
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{
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switch (val) {
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case 125:
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return 0x1;
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case 250:
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return 0x3;
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case 500:
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return 0x5;
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case 1000:
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return 0x7;
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}
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return -EINVAL;
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}
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2018-09-08 19:07:33 +08:00
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static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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const struct mtk_pin_desc *desc;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
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hw->soc->gpio_m);
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}
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static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin, bool input)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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const struct mtk_pin_desc *desc;
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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/* hardware would take 0 as input direction */
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return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
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}
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static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int pin, unsigned long *config)
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{
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struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
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u32 param = pinconf_to_config_param(*config);
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2022-03-08 18:09:52 +08:00
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int pullup, reg, err = -ENOTSUPP, ret = 1;
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2018-09-08 19:07:33 +08:00
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const struct mtk_pin_desc *desc;
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2022-03-08 18:09:52 +08:00
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if (pin >= hw->soc->npins)
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return -EINVAL;
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2018-09-08 19:07:33 +08:00
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desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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2022-03-08 18:09:52 +08:00
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if (!hw->soc->bias_get_combo)
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break;
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err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
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if (err)
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break;
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if (ret == MTK_PUPD_SET_R1R0_00)
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ret = MTK_DISABLE;
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if (param == PIN_CONFIG_BIAS_DISABLE) {
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if (ret != MTK_DISABLE)
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err = -EINVAL;
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} else if (param == PIN_CONFIG_BIAS_PULL_UP) {
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if (!pullup || ret == MTK_DISABLE)
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err = -EINVAL;
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} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
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if (pullup || ret == MTK_DISABLE)
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err = -EINVAL;
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2020-01-22 14:53:13 +08:00
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}
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2018-09-08 19:07:33 +08:00
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break;
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case PIN_CONFIG_SLEW_RATE:
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2020-01-22 14:53:12 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
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2018-09-08 19:07:33 +08:00
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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case PIN_CONFIG_OUTPUT_ENABLE:
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2020-01-22 14:53:12 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
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2018-09-08 19:07:33 +08:00
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if (err)
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2022-03-08 18:09:52 +08:00
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break;
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2020-01-22 14:53:11 +08:00
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/* CONFIG Current direction return value
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* ------------- ----------------- ----------------------
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* OUTPUT_ENABLE output 1 (= HW value)
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* input 0 (= HW value)
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* INPUT_ENABLE output 0 (= reverse HW value)
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* input 1 (= reverse HW value)
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*/
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if (param == PIN_CONFIG_INPUT_ENABLE)
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2020-01-22 14:53:12 +08:00
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ret = !ret;
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2018-09-08 19:07:33 +08:00
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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2020-01-22 14:53:12 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
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2018-09-08 19:07:33 +08:00
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if (err)
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2022-03-08 18:09:52 +08:00
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break;
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2020-01-22 14:53:12 +08:00
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/* return error when in output mode
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* because schmitt trigger only work in input mode
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*/
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if (ret) {
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err = -EINVAL;
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2022-03-08 18:09:52 +08:00
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break;
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2020-01-22 14:53:12 +08:00
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}
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2018-09-08 19:07:33 +08:00
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2020-01-22 14:53:12 +08:00
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err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
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2018-09-08 19:07:33 +08:00
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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2022-03-08 18:09:52 +08:00
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if (!hw->soc->drive_get)
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break;
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2022-03-08 18:09:53 +08:00
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if (hw->soc->adv_drive_get) {
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err = hw->soc->adv_drive_get(hw, desc, &ret);
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if (!err) {
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err = mtk_drv_adv_to_uA(ret);
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if (err > 0) {
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/* PIN_CONFIG_DRIVE_STRENGTH_UA used */
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err = -EINVAL;
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break;
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}
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}
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}
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2022-03-08 18:09:52 +08:00
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err = hw->soc->drive_get(hw, desc, &ret);
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2018-09-08 19:07:33 +08:00
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break;
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2022-03-08 18:09:53 +08:00
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case PIN_CONFIG_DRIVE_STRENGTH_UA:
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if (!hw->soc->adv_drive_get)
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break;
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err = hw->soc->adv_drive_get(hw, desc, &ret);
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if (err)
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break;
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err = mtk_drv_adv_to_uA(ret);
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if (err < 0)
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break;
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ret = err;
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err = 0;
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break;
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2018-09-08 19:07:33 +08:00
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case MTK_PIN_CONFIG_TDSEL:
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case MTK_PIN_CONFIG_RDSEL:
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reg = (param == MTK_PIN_CONFIG_TDSEL) ?
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PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
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2020-01-22 14:53:12 +08:00
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err = mtk_hw_get_value(hw, desc, reg, &ret);
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2018-09-08 19:07:33 +08:00
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break;
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case MTK_PIN_CONFIG_PU_ADV:
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case MTK_PIN_CONFIG_PD_ADV:
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2022-03-08 18:09:52 +08:00
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if (!hw->soc->adv_pull_get)
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break;
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pullup = param == MTK_PIN_CONFIG_PU_ADV;
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err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
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2018-09-08 19:07:33 +08:00
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break;
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
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case MTK_PIN_CONFIG_DRV_ADV:
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2022-03-08 18:09:52 +08:00
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if (!hw->soc->adv_drive_get)
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break;
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err = hw->soc->adv_drive_get(hw, desc, &ret);
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
}
|
|
|
|
|
2020-01-22 14:53:11 +08:00
|
|
|
if (!err)
|
|
|
|
*config = pinconf_to_config_packed(param, ret);
|
2018-09-08 19:07:33 +08:00
|
|
|
|
2020-01-22 14:53:11 +08:00
|
|
|
return err;
|
2018-09-08 19:07:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
2022-03-08 18:09:48 +08:00
|
|
|
enum pin_config_param param, u32 arg)
|
2018-09-08 19:07:33 +08:00
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
const struct mtk_pin_desc *desc;
|
2022-03-08 18:09:52 +08:00
|
|
|
int err = -ENOTSUPP;
|
2018-09-08 19:07:33 +08:00
|
|
|
u32 reg;
|
|
|
|
|
2022-03-08 18:09:52 +08:00
|
|
|
if (pin >= hw->soc->npins)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
|
|
|
|
|
|
|
|
switch ((u32)param) {
|
|
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
2022-03-08 18:09:52 +08:00
|
|
|
if (!hw->soc->bias_set_combo)
|
|
|
|
break;
|
|
|
|
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
2022-03-08 18:09:52 +08:00
|
|
|
if (!hw->soc->bias_set_combo)
|
|
|
|
break;
|
|
|
|
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
|
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
2022-03-08 18:09:52 +08:00
|
|
|
if (!hw->soc->bias_set_combo)
|
|
|
|
break;
|
|
|
|
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
|
|
|
case PIN_CONFIG_OUTPUT_ENABLE:
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
|
|
|
|
MTK_DISABLE);
|
2020-01-22 14:53:11 +08:00
|
|
|
/* Keep set direction to consider the case that a GPIO pin
|
|
|
|
* does not have SMT control
|
|
|
|
*/
|
|
|
|
if (err != -ENOTSUPP)
|
2022-03-08 18:09:52 +08:00
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
|
|
|
|
MTK_OUTPUT);
|
|
|
|
break;
|
|
|
|
case PIN_CONFIG_INPUT_ENABLE:
|
2020-01-22 14:53:11 +08:00
|
|
|
/* regard all non-zero value as enable */
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
|
|
|
|
if (err)
|
2022-03-08 18:09:52 +08:00
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
|
|
|
|
MTK_INPUT);
|
|
|
|
break;
|
|
|
|
case PIN_CONFIG_SLEW_RATE:
|
2020-01-22 14:53:11 +08:00
|
|
|
/* regard all non-zero value as enable */
|
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
|
|
|
case PIN_CONFIG_OUTPUT:
|
2020-11-20 17:30:58 +08:00
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
|
|
|
|
arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
if (err)
|
2022-03-08 18:09:52 +08:00
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
|
2020-11-20 17:30:58 +08:00
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
|
|
|
|
MTK_OUTPUT);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
2020-01-22 14:53:11 +08:00
|
|
|
case PIN_CONFIG_INPUT_SCHMITT:
|
2018-09-08 19:07:33 +08:00
|
|
|
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
|
|
|
|
/* arg = 1: Input mode & SMT enable ;
|
|
|
|
* arg = 0: Output mode & SMT disable
|
|
|
|
*/
|
2020-01-22 14:53:11 +08:00
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
if (err)
|
2022-03-08 18:09:52 +08:00
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
|
2020-01-22 14:53:11 +08:00
|
|
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
2022-03-08 18:09:52 +08:00
|
|
|
if (!hw->soc->drive_set)
|
|
|
|
break;
|
|
|
|
err = hw->soc->drive_set(hw, desc, arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
2022-03-08 18:09:53 +08:00
|
|
|
case PIN_CONFIG_DRIVE_STRENGTH_UA:
|
|
|
|
if (!hw->soc->adv_drive_set)
|
|
|
|
break;
|
|
|
|
|
|
|
|
err = mtk_drv_uA_to_adv(arg);
|
|
|
|
if (err < 0)
|
|
|
|
break;
|
|
|
|
err = hw->soc->adv_drive_set(hw, desc, err);
|
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
case MTK_PIN_CONFIG_TDSEL:
|
|
|
|
case MTK_PIN_CONFIG_RDSEL:
|
|
|
|
reg = (param == MTK_PIN_CONFIG_TDSEL) ?
|
|
|
|
PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
|
|
|
|
err = mtk_hw_set_value(hw, desc, reg, arg);
|
|
|
|
break;
|
|
|
|
case MTK_PIN_CONFIG_PU_ADV:
|
|
|
|
case MTK_PIN_CONFIG_PD_ADV:
|
2022-03-08 18:09:52 +08:00
|
|
|
if (!hw->soc->adv_pull_set)
|
|
|
|
break;
|
|
|
|
err = hw->soc->adv_pull_set(hw, desc,
|
|
|
|
(param == MTK_PIN_CONFIG_PU_ADV),
|
|
|
|
arg);
|
2018-09-08 19:07:33 +08:00
|
|
|
break;
|
pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
|
|
|
case MTK_PIN_CONFIG_DRV_ADV:
|
2022-03-08 18:09:52 +08:00
|
|
|
if (!hw->soc->adv_drive_set)
|
|
|
|
break;
|
|
|
|
err = hw->soc->adv_drive_set(hw, desc, arg);
|
pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 11:35:35 +08:00
|
|
|
break;
|
2018-09-08 19:07:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct mtk_pinctrl_group *
|
|
|
|
mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->ngrps; i++) {
|
|
|
|
struct mtk_pinctrl_group *grp = hw->groups + i;
|
|
|
|
|
|
|
|
if (grp->pin == pin)
|
|
|
|
return grp;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mtk_func_desc *
|
|
|
|
mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
|
|
|
|
{
|
|
|
|
const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
|
|
|
|
const struct mtk_func_desc *func = pin->funcs;
|
|
|
|
|
|
|
|
while (func && func->name) {
|
|
|
|
if (func->muxval == fnum)
|
|
|
|
return func;
|
|
|
|
func++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
|
|
|
|
u32 fnum)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->npins; i++) {
|
|
|
|
const struct mtk_pin_desc *pin = hw->soc->pins + i;
|
|
|
|
|
|
|
|
if (pin->number == pin_num) {
|
|
|
|
const struct mtk_func_desc *func = pin->funcs;
|
|
|
|
|
|
|
|
while (func && func->name) {
|
|
|
|
if (func->muxval == fnum)
|
|
|
|
return true;
|
|
|
|
func++;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
|
|
|
|
u32 pin, u32 fnum,
|
|
|
|
struct mtk_pinctrl_group *grp,
|
|
|
|
struct pinctrl_map **map,
|
|
|
|
unsigned *reserved_maps,
|
|
|
|
unsigned *num_maps)
|
|
|
|
{
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
if (*num_maps == *reserved_maps)
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
|
|
|
|
(*map)[*num_maps].data.mux.group = grp->name;
|
|
|
|
|
|
|
|
ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
|
|
|
|
if (!ret) {
|
|
|
|
dev_err(pctl->dev, "invalid function %d on pin %d .\n",
|
|
|
|
fnum, pin);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
|
|
|
|
(*num_maps)++;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
|
|
|
|
struct device_node *node,
|
|
|
|
struct pinctrl_map **map,
|
|
|
|
unsigned *reserved_maps,
|
|
|
|
unsigned *num_maps)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
int num_pins, num_funcs, maps_per_pin, i, err;
|
|
|
|
struct mtk_pinctrl_group *grp;
|
|
|
|
unsigned int num_configs;
|
|
|
|
bool has_config = false;
|
|
|
|
unsigned long *configs;
|
|
|
|
u32 pinfunc, pin, func;
|
|
|
|
struct property *pins;
|
|
|
|
unsigned reserve = 0;
|
|
|
|
|
|
|
|
pins = of_find_property(node, "pinmux", NULL);
|
|
|
|
if (!pins) {
|
2018-11-17 06:05:40 +08:00
|
|
|
dev_err(hw->dev, "missing pins property in node %pOFn .\n",
|
|
|
|
node);
|
2018-09-08 19:07:33 +08:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
|
|
|
|
&num_configs);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
if (num_configs)
|
|
|
|
has_config = true;
|
|
|
|
|
|
|
|
num_pins = pins->length / sizeof(u32);
|
|
|
|
num_funcs = num_pins;
|
|
|
|
maps_per_pin = 0;
|
|
|
|
if (num_funcs)
|
|
|
|
maps_per_pin++;
|
|
|
|
if (has_config && num_pins >= 1)
|
|
|
|
maps_per_pin++;
|
|
|
|
|
|
|
|
if (!num_pins || !maps_per_pin) {
|
|
|
|
err = -EINVAL;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
reserve = num_pins * maps_per_pin;
|
|
|
|
|
|
|
|
err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
|
|
|
|
reserve);
|
|
|
|
if (err < 0)
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
for (i = 0; i < num_pins; i++) {
|
|
|
|
err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
|
|
|
|
if (err)
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
pin = MTK_GET_PIN_NO(pinfunc);
|
|
|
|
func = MTK_GET_PIN_FUNC(pinfunc);
|
|
|
|
|
|
|
|
if (pin >= hw->soc->npins ||
|
|
|
|
func >= ARRAY_SIZE(mtk_gpio_functions)) {
|
|
|
|
dev_err(hw->dev, "invalid pins value.\n");
|
|
|
|
err = -EINVAL;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
grp = mtk_pctrl_find_group_by_pin(hw, pin);
|
|
|
|
if (!grp) {
|
|
|
|
dev_err(hw->dev, "unable to match pin %d to group\n",
|
|
|
|
pin);
|
|
|
|
err = -EINVAL;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
|
|
|
|
reserved_maps, num_maps);
|
|
|
|
if (err < 0)
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
if (has_config) {
|
|
|
|
err = pinctrl_utils_add_map_configs(pctldev, map,
|
|
|
|
reserved_maps,
|
|
|
|
num_maps,
|
|
|
|
grp->name,
|
|
|
|
configs,
|
|
|
|
num_configs,
|
|
|
|
PIN_MAP_TYPE_CONFIGS_GROUP);
|
|
|
|
if (err < 0)
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
err = 0;
|
|
|
|
|
|
|
|
exit:
|
|
|
|
kfree(configs);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|
|
|
struct device_node *np_config,
|
|
|
|
struct pinctrl_map **map,
|
|
|
|
unsigned *num_maps)
|
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
unsigned reserved_maps;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*map = NULL;
|
|
|
|
*num_maps = 0;
|
|
|
|
reserved_maps = 0;
|
|
|
|
|
|
|
|
for_each_child_of_node(np_config, np) {
|
|
|
|
ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
|
|
|
|
&reserved_maps,
|
|
|
|
num_maps);
|
|
|
|
if (ret < 0) {
|
|
|
|
pinctrl_utils_free_map(pctldev, *map, *num_maps);
|
|
|
|
of_node_put(np);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
|
|
|
return hw->soc->ngrps;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned group)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
|
|
|
return hw->groups[group].name;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned group, const unsigned **pins,
|
|
|
|
unsigned *num_pins)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
|
|
|
*pins = (unsigned *)&hw->groups[group].pin;
|
|
|
|
*num_pins = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-22 14:53:14 +08:00
|
|
|
static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
|
|
|
|
{
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
int value, err;
|
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:14 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
|
|
|
|
err = mtk_hw_get_value(hw, desc, field, &value);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_pinmux(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_direction(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_out(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_in(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_smt(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_ies(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
|
|
|
|
|
|
|
|
#define mtk_pctrl_get_driving(hw, gpio) \
|
|
|
|
mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
|
|
|
|
|
|
|
|
ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
|
2021-09-24 16:06:30 +08:00
|
|
|
unsigned int gpio, char *buf, unsigned int buf_len)
|
2020-01-22 14:53:14 +08:00
|
|
|
{
|
2021-09-24 16:06:31 +08:00
|
|
|
int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1, rsel = -1;
|
2020-01-22 14:53:14 +08:00
|
|
|
const struct mtk_pin_desc *desc;
|
2021-11-27 22:07:50 +08:00
|
|
|
u32 try_all_type = 0;
|
2020-01-22 14:53:14 +08:00
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:14 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2022-03-08 18:09:51 +08:00
|
|
|
if (mtk_is_virt_gpio(hw, gpio))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2020-01-22 14:53:14 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
pinmux = mtk_pctrl_get_pinmux(hw, gpio);
|
|
|
|
if (pinmux >= hw->soc->nfuncs)
|
|
|
|
pinmux -= hw->soc->nfuncs;
|
|
|
|
|
|
|
|
mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
|
2021-09-24 16:06:31 +08:00
|
|
|
|
|
|
|
if (hw->soc->pull_type)
|
|
|
|
try_all_type = hw->soc->pull_type[desc->number];
|
|
|
|
|
|
|
|
if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
|
|
|
|
rsel = pullen;
|
2020-01-22 14:53:14 +08:00
|
|
|
pullen = 1;
|
2021-09-24 16:06:31 +08:00
|
|
|
} else {
|
|
|
|
/* Case for: R1R0 */
|
|
|
|
if (pullen == MTK_PUPD_SET_R1R0_00) {
|
|
|
|
pullen = 0;
|
|
|
|
r1 = 0;
|
|
|
|
r0 = 0;
|
|
|
|
} else if (pullen == MTK_PUPD_SET_R1R0_01) {
|
|
|
|
pullen = 1;
|
|
|
|
r1 = 0;
|
|
|
|
r0 = 1;
|
|
|
|
} else if (pullen == MTK_PUPD_SET_R1R0_10) {
|
|
|
|
pullen = 1;
|
|
|
|
r1 = 1;
|
|
|
|
r0 = 0;
|
|
|
|
} else if (pullen == MTK_PUPD_SET_R1R0_11) {
|
|
|
|
pullen = 1;
|
|
|
|
r1 = 1;
|
|
|
|
r0 = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Case for: RSEL */
|
|
|
|
if (pullen >= MTK_PULL_SET_RSEL_000 &&
|
|
|
|
pullen <= MTK_PULL_SET_RSEL_111) {
|
|
|
|
rsel = pullen - MTK_PULL_SET_RSEL_000;
|
|
|
|
pullen = 1;
|
|
|
|
}
|
2020-01-22 14:53:14 +08:00
|
|
|
}
|
2021-09-24 16:06:30 +08:00
|
|
|
len += scnprintf(buf + len, buf_len - len,
|
2020-01-22 14:53:14 +08:00
|
|
|
"%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
|
|
|
|
gpio,
|
|
|
|
pinmux,
|
|
|
|
mtk_pctrl_get_direction(hw, gpio),
|
|
|
|
mtk_pctrl_get_out(hw, gpio),
|
|
|
|
mtk_pctrl_get_in(hw, gpio),
|
|
|
|
mtk_pctrl_get_driving(hw, gpio),
|
|
|
|
mtk_pctrl_get_smt(hw, gpio),
|
|
|
|
mtk_pctrl_get_ies(hw, gpio),
|
|
|
|
pullen,
|
|
|
|
pullup);
|
|
|
|
|
2022-03-08 18:09:50 +08:00
|
|
|
if (r1 != -1)
|
|
|
|
len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
|
|
|
|
else if (rsel != -1)
|
|
|
|
len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
|
2020-01-22 14:53:14 +08:00
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
2020-04-08 04:08:16 +08:00
|
|
|
EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
|
2020-01-22 14:53:14 +08:00
|
|
|
|
|
|
|
#define PIN_DBG_BUF_SZ 96
|
|
|
|
static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
|
|
|
unsigned int gpio)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
char buf[PIN_DBG_BUF_SZ];
|
|
|
|
|
|
|
|
(void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
|
|
|
|
|
|
|
|
seq_printf(s, "%s", buf);
|
|
|
|
}
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
static const struct pinctrl_ops mtk_pctlops = {
|
|
|
|
.dt_node_to_map = mtk_pctrl_dt_node_to_map,
|
|
|
|
.dt_free_map = pinctrl_utils_free_map,
|
|
|
|
.get_groups_count = mtk_pctrl_get_groups_count,
|
|
|
|
.get_group_name = mtk_pctrl_get_group_name,
|
|
|
|
.get_group_pins = mtk_pctrl_get_group_pins,
|
2020-01-22 14:53:14 +08:00
|
|
|
.pin_dbg_show = mtk_pctrl_dbg_show,
|
2018-09-08 19:07:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
|
|
|
|
{
|
|
|
|
return ARRAY_SIZE(mtk_gpio_functions);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned selector)
|
|
|
|
{
|
|
|
|
return mtk_gpio_functions[selector];
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned function,
|
|
|
|
const char * const **groups,
|
|
|
|
unsigned * const num_groups)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
|
|
|
|
*groups = hw->grp_names;
|
|
|
|
*num_groups = hw->soc->ngrps;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
|
|
|
|
unsigned function,
|
|
|
|
unsigned group)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
struct mtk_pinctrl_group *grp = hw->groups + group;
|
|
|
|
const struct mtk_func_desc *desc_func;
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
|
|
|
|
if (!ret) {
|
|
|
|
dev_err(hw->dev, "invalid function %d on group %d .\n",
|
|
|
|
function, group);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
|
|
|
|
if (!desc_func)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
|
|
|
|
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pinmux_ops mtk_pmxops = {
|
|
|
|
.get_functions_count = mtk_pmx_get_funcs_cnt,
|
|
|
|
.get_function_name = mtk_pmx_get_func_name,
|
|
|
|
.get_function_groups = mtk_pmx_get_func_groups,
|
|
|
|
.set_mux = mtk_pmx_set_mux,
|
|
|
|
.gpio_set_direction = mtk_pinmux_gpio_set_direction,
|
|
|
|
.gpio_request_enable = mtk_pinmux_gpio_request_enable,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
|
|
|
|
unsigned long *config)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
2022-03-08 18:09:49 +08:00
|
|
|
struct mtk_pinctrl_group *grp = &hw->groups[group];
|
2018-09-08 19:07:33 +08:00
|
|
|
|
2022-03-08 18:09:49 +08:00
|
|
|
/* One pin per group only */
|
|
|
|
return mtk_pinconf_get(pctldev, grp->pin, config);
|
2018-09-08 19:07:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
|
|
|
|
unsigned long *configs, unsigned num_configs)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
struct mtk_pinctrl_group *grp = &hw->groups[group];
|
2022-03-08 18:09:53 +08:00
|
|
|
bool drive_strength_uA_found = false;
|
|
|
|
bool adv_drve_strength_found = false;
|
2018-09-08 19:07:33 +08:00
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < num_configs; i++) {
|
|
|
|
ret = mtk_pinconf_set(pctldev, grp->pin,
|
|
|
|
pinconf_to_config_param(configs[i]),
|
|
|
|
pinconf_to_config_argument(configs[i]));
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2022-03-08 18:09:53 +08:00
|
|
|
|
|
|
|
if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
|
|
|
|
drive_strength_uA_found = true;
|
|
|
|
if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
|
|
|
|
adv_drve_strength_found = true;
|
2018-09-08 19:07:33 +08:00
|
|
|
}
|
|
|
|
|
2022-03-08 18:09:53 +08:00
|
|
|
/*
|
|
|
|
* Disable advanced drive strength mode if drive-strength-microamp
|
|
|
|
* is not set. However, mediatek,drive-strength-adv takes precedence
|
|
|
|
* as its value can explicitly request the mode be enabled or not.
|
|
|
|
*/
|
|
|
|
if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
|
|
|
|
!adv_drve_strength_found)
|
|
|
|
hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pinconf_ops mtk_confops = {
|
|
|
|
.pin_config_get = mtk_pinconf_get,
|
|
|
|
.pin_config_group_get = mtk_pconf_group_get,
|
|
|
|
.pin_config_group_set = mtk_pconf_group_set,
|
2020-01-22 14:53:14 +08:00
|
|
|
.is_generic = true,
|
2018-09-08 19:07:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pinctrl_desc mtk_desc = {
|
|
|
|
.name = PINCTRL_PINCTRL_DEV,
|
|
|
|
.pctlops = &mtk_pctlops,
|
|
|
|
.pmxops = &mtk_pmxops,
|
|
|
|
.confops = &mtk_confops,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
int value, err;
|
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:09 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2020-07-23 19:19:53 +08:00
|
|
|
/*
|
|
|
|
* "Virtual" GPIOs are always and only used for interrupts
|
|
|
|
* Since they are only used for interrupts, they are always inputs
|
|
|
|
*/
|
|
|
|
if (mtk_is_virt_gpio(hw, gpio))
|
|
|
|
return 1;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2020-02-14 21:57:12 +08:00
|
|
|
if (value)
|
|
|
|
return GPIO_LINE_DIRECTION_OUT;
|
|
|
|
|
|
|
|
return GPIO_LINE_DIRECTION_IN;
|
2018-09-08 19:07:33 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
int value, err;
|
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:09 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
|
|
|
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
return !!value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:09 +08:00
|
|
|
return;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
|
|
|
|
|
|
|
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
|
|
|
|
{
|
2020-01-22 14:53:09 +08:00
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:09 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
return pinctrl_gpio_direction_input(chip->base + gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
|
|
|
|
int value)
|
|
|
|
{
|
2020-01-22 14:53:09 +08:00
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
|
2020-02-18 13:52:47 +08:00
|
|
|
if (gpio >= hw->soc->npins)
|
2020-01-22 14:53:09 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
mtk_gpio_set(chip, gpio, value);
|
|
|
|
|
|
|
|
return pinctrl_gpio_direction_output(chip->base + gpio);
|
|
|
|
}
|
|
|
|
|
2018-09-08 19:07:38 +08:00
|
|
|
static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
|
|
|
|
if (!hw->eint)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
|
|
|
|
|
|
|
|
if (desc->eint.eint_n == EINT_NA)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
|
|
|
|
}
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
|
|
|
|
unsigned long config)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
|
|
|
const struct mtk_pin_desc *desc;
|
|
|
|
u32 debounce;
|
|
|
|
|
|
|
|
desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
|
|
|
|
|
|
|
|
if (!hw->eint ||
|
|
|
|
pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
|
|
|
|
desc->eint.eint_n == EINT_NA)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
debounce = pinconf_to_config_argument(config);
|
|
|
|
|
|
|
|
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
|
|
|
|
}
|
|
|
|
|
2021-12-14 20:58:54 +08:00
|
|
|
static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
2018-09-08 19:07:33 +08:00
|
|
|
{
|
|
|
|
struct gpio_chip *chip = &hw->chip;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
chip->label = PINCTRL_PINCTRL_DEV;
|
|
|
|
chip->parent = hw->dev;
|
|
|
|
chip->request = gpiochip_generic_request;
|
|
|
|
chip->free = gpiochip_generic_free;
|
|
|
|
chip->get_direction = mtk_gpio_get_direction;
|
|
|
|
chip->direction_input = mtk_gpio_direction_input;
|
|
|
|
chip->direction_output = mtk_gpio_direction_output;
|
|
|
|
chip->get = mtk_gpio_get;
|
|
|
|
chip->set = mtk_gpio_set;
|
2020-12-11 16:47:17 +08:00
|
|
|
chip->to_irq = mtk_gpio_to_irq;
|
|
|
|
chip->set_config = mtk_gpio_set_config;
|
2018-09-08 19:07:33 +08:00
|
|
|
chip->base = -1;
|
|
|
|
chip->ngpio = hw->soc->npins;
|
|
|
|
chip->of_gpio_n_cells = 2;
|
|
|
|
|
|
|
|
ret = gpiochip_add_data(chip, hw);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_pctrl_build_state(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Allocate groups */
|
|
|
|
hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
|
|
|
|
sizeof(*hw->groups), GFP_KERNEL);
|
|
|
|
if (!hw->groups)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* We assume that one pin is one group, use pin name as group name. */
|
|
|
|
hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
|
|
|
|
sizeof(*hw->grp_names), GFP_KERNEL);
|
|
|
|
if (!hw->grp_names)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->npins; i++) {
|
|
|
|
const struct mtk_pin_desc *pin = hw->soc->pins + i;
|
|
|
|
struct mtk_pinctrl_group *group = hw->groups + i;
|
|
|
|
|
|
|
|
group->name = pin->name;
|
|
|
|
group->pin = pin->number;
|
|
|
|
|
|
|
|
hw->grp_names[i] = pin->name;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-02-22 19:11:40 +08:00
|
|
|
int mtk_paris_pinctrl_probe(struct platform_device *pdev)
|
2018-09-08 19:07:33 +08:00
|
|
|
{
|
2022-03-08 18:09:55 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
2018-09-08 19:07:33 +08:00
|
|
|
struct pinctrl_pin_desc *pins;
|
|
|
|
struct mtk_pinctrl *hw;
|
|
|
|
int err, i;
|
|
|
|
|
|
|
|
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
|
|
|
|
if (!hw)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, hw);
|
2022-02-22 19:11:40 +08:00
|
|
|
|
|
|
|
hw->soc = device_get_match_data(dev);
|
|
|
|
if (!hw->soc)
|
|
|
|
return -ENOENT;
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
hw->dev = &pdev->dev;
|
|
|
|
|
2022-03-08 18:09:55 +08:00
|
|
|
if (!hw->soc->nbase_names)
|
|
|
|
return dev_err_probe(dev, -EINVAL,
|
2018-09-08 19:07:33 +08:00
|
|
|
"SoC should be assigned at least one register base\n");
|
|
|
|
|
|
|
|
hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
|
|
|
|
sizeof(*hw->base), GFP_KERNEL);
|
2018-09-20 14:21:28 +08:00
|
|
|
if (!hw->base)
|
|
|
|
return -ENOMEM;
|
2018-09-08 19:07:33 +08:00
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->nbase_names; i++) {
|
2020-09-17 14:41:51 +08:00
|
|
|
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
|
|
|
|
hw->soc->base_names[i]);
|
2018-09-08 19:07:33 +08:00
|
|
|
if (IS_ERR(hw->base[i]))
|
|
|
|
return PTR_ERR(hw->base[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
hw->nbase = hw->soc->nbase_names;
|
|
|
|
|
2021-09-24 16:06:31 +08:00
|
|
|
if (of_find_property(hw->dev->of_node,
|
2022-02-16 11:21:24 +08:00
|
|
|
"mediatek,rsel-resistance-in-si-unit", NULL))
|
2021-09-24 16:06:31 +08:00
|
|
|
hw->rsel_si_unit = true;
|
|
|
|
else
|
|
|
|
hw->rsel_si_unit = false;
|
|
|
|
|
2021-04-19 17:34:49 +08:00
|
|
|
spin_lock_init(&hw->lock);
|
2021-03-21 11:31:50 +08:00
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
err = mtk_pctrl_build_state(pdev);
|
2022-03-08 18:09:55 +08:00
|
|
|
if (err)
|
|
|
|
return dev_err_probe(dev, err, "build state failed\n");
|
2018-09-08 19:07:33 +08:00
|
|
|
|
|
|
|
/* Copy from internal struct mtk_pin_desc to register to the core */
|
|
|
|
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
|
|
|
|
GFP_KERNEL);
|
2018-09-20 14:21:28 +08:00
|
|
|
if (!pins)
|
|
|
|
return -ENOMEM;
|
2018-09-08 19:07:33 +08:00
|
|
|
|
|
|
|
for (i = 0; i < hw->soc->npins; i++) {
|
|
|
|
pins[i].number = hw->soc->pins[i].number;
|
|
|
|
pins[i].name = hw->soc->pins[i].name;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup pins descriptions per SoC types */
|
|
|
|
mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
|
|
|
|
mtk_desc.npins = hw->soc->npins;
|
|
|
|
mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
|
|
|
|
mtk_desc.custom_params = mtk_custom_bindings;
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
mtk_desc.custom_conf_items = mtk_conf_items;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
|
|
|
|
&hw->pctrl);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = pinctrl_enable(hw->pctrl);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2018-09-08 19:07:38 +08:00
|
|
|
err = mtk_build_eint(hw, pdev);
|
|
|
|
if (err)
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
"Failed to add EINT, but pinctrl still can work\n");
|
|
|
|
|
2018-09-08 19:07:33 +08:00
|
|
|
/* Build gpiochip should be after pinctrl_enable is done */
|
2021-12-14 20:58:54 +08:00
|
|
|
err = mtk_build_gpiochip(hw);
|
2022-03-08 18:09:55 +08:00
|
|
|
if (err)
|
|
|
|
return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
|
2018-09-08 19:07:33 +08:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2020-04-08 04:08:16 +08:00
|
|
|
EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
|
2019-05-08 15:33:30 +08:00
|
|
|
|
|
|
|
static int mtk_paris_pinctrl_suspend(struct device *device)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *pctl = dev_get_drvdata(device);
|
|
|
|
|
|
|
|
return mtk_eint_do_suspend(pctl->eint);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mtk_paris_pinctrl_resume(struct device *device)
|
|
|
|
{
|
|
|
|
struct mtk_pinctrl *pctl = dev_get_drvdata(device);
|
|
|
|
|
|
|
|
return mtk_eint_do_resume(pctl->eint);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
|
|
|
|
.suspend_noirq = mtk_paris_pinctrl_suspend,
|
|
|
|
.resume_noirq = mtk_paris_pinctrl_resume,
|
|
|
|
};
|
2020-04-08 04:08:16 +08:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");
|