2019-05-29 22:17:56 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2013-02-02 08:26:00 +08:00
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/*
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* Copyright (C) 2012 Invensense, Inc.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/sysfs.h>
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#include <linux/jiffies.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/poll.h>
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2018-05-28 21:22:04 +08:00
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#include <linux/math64.h>
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2018-05-22 22:18:20 +08:00
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#include <asm/unaligned.h>
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2013-02-02 08:26:00 +08:00
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#include "inv_mpu_iio.h"
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2018-05-28 21:22:04 +08:00
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/**
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* inv_mpu6050_update_period() - Update chip internal period estimation
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*
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* @st: driver state
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* @timestamp: the interrupt timestamp
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* @nb: number of data set in the fifo
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*
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* This function uses interrupt timestamps to estimate the chip period and
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* to choose the data timestamp to come.
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*/
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static void inv_mpu6050_update_period(struct inv_mpu6050_state *st,
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s64 timestamp, size_t nb)
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{
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/* Period boundaries for accepting timestamp */
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const s64 period_min =
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(NSEC_PER_MSEC * (100 - INV_MPU6050_TS_PERIOD_JITTER)) / 100;
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const s64 period_max =
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(NSEC_PER_MSEC * (100 + INV_MPU6050_TS_PERIOD_JITTER)) / 100;
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const s32 divider = INV_MPU6050_FREQ_DIVIDER(st);
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s64 delta, interval;
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bool use_it_timestamp = false;
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if (st->it_timestamp == 0) {
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/* not initialized, forced to use it_timestamp */
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use_it_timestamp = true;
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} else if (nb == 1) {
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/*
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* Validate the use of it timestamp by checking if interrupt
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* has been delayed.
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* nb > 1 means interrupt was delayed for more than 1 sample,
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* so it's obviously not good.
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* Compute the chip period between 2 interrupts for validating.
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*/
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delta = div_s64(timestamp - st->it_timestamp, divider);
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if (delta > period_min && delta < period_max) {
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/* update chip period and use it timestamp */
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st->chip_period = (st->chip_period + delta) / 2;
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use_it_timestamp = true;
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}
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}
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if (use_it_timestamp) {
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/*
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* Manage case of multiple samples in the fifo (nb > 1):
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* compute timestamp corresponding to the first sample using
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* estimated chip period.
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*/
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interval = (nb - 1) * st->chip_period * divider;
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st->data_timestamp = timestamp - interval;
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}
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/* save it timestamp */
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st->it_timestamp = timestamp;
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}
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/**
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* inv_mpu6050_get_timestamp() - Return the current data timestamp
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*
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* @st: driver state
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* @return: current data timestamp
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*
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* This function returns the current data timestamp and prepares for next one.
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*/
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static s64 inv_mpu6050_get_timestamp(struct inv_mpu6050_state *st)
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{
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s64 ts;
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/* return current data timestamp and increment */
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ts = st->data_timestamp;
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st->data_timestamp += st->chip_period * INV_MPU6050_FREQ_DIVIDER(st);
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return ts;
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}
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2013-02-02 08:26:00 +08:00
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int inv_reset_fifo(struct iio_dev *indio_dev)
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{
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int result;
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u8 d;
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struct inv_mpu6050_state *st = iio_priv(indio_dev);
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2018-05-28 21:22:04 +08:00
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/* reset it timestamp validation */
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st->it_timestamp = 0;
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2013-02-02 08:26:00 +08:00
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/* disable interrupt */
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2016-02-12 19:44:43 +08:00
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result = regmap_write(st->map, st->reg->int_enable, 0);
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2013-02-02 08:26:00 +08:00
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if (result) {
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2016-02-12 19:44:44 +08:00
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dev_err(regmap_get_device(st->map), "int_enable failed %d\n",
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result);
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2013-02-02 08:26:00 +08:00
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return result;
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}
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/* disable the sensor output to FIFO */
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2016-02-12 19:44:43 +08:00
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result = regmap_write(st->map, st->reg->fifo_en, 0);
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2013-02-02 08:26:00 +08:00
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if (result)
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goto reset_fifo_fail;
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/* disable fifo reading */
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2018-04-30 18:14:11 +08:00
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result = regmap_write(st->map, st->reg->user_ctrl,
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st->chip_config.user_ctrl);
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2013-02-02 08:26:00 +08:00
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if (result)
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goto reset_fifo_fail;
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/* reset FIFO*/
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2018-04-30 18:14:11 +08:00
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d = st->chip_config.user_ctrl | INV_MPU6050_BIT_FIFO_RST;
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result = regmap_write(st->map, st->reg->user_ctrl, d);
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2013-02-02 08:26:00 +08:00
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if (result)
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goto reset_fifo_fail;
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2015-02-19 02:05:21 +08:00
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2013-02-02 08:26:00 +08:00
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/* enable interrupt */
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if (st->chip_config.accl_fifo_enable ||
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st->chip_config.gyro_fifo_enable) {
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2016-02-12 19:44:43 +08:00
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result = regmap_write(st->map, st->reg->int_enable,
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2016-02-18 23:53:12 +08:00
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INV_MPU6050_BIT_DATA_RDY_EN);
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2013-02-02 08:26:00 +08:00
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if (result)
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return result;
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}
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2018-04-30 18:14:11 +08:00
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/* enable FIFO reading */
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d = st->chip_config.user_ctrl | INV_MPU6050_BIT_FIFO_EN;
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result = regmap_write(st->map, st->reg->user_ctrl, d);
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2013-02-02 08:26:00 +08:00
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if (result)
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goto reset_fifo_fail;
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/* enable sensor output to FIFO */
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d = 0;
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if (st->chip_config.gyro_fifo_enable)
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d |= INV_MPU6050_BITS_GYRO_OUT;
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if (st->chip_config.accl_fifo_enable)
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d |= INV_MPU6050_BIT_ACCEL_OUT;
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2016-02-12 19:44:43 +08:00
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result = regmap_write(st->map, st->reg->fifo_en, d);
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2013-02-02 08:26:00 +08:00
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if (result)
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goto reset_fifo_fail;
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return 0;
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reset_fifo_fail:
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2016-02-12 19:44:44 +08:00
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dev_err(regmap_get_device(st->map), "reset fifo failed %d\n", result);
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2016-02-12 19:44:43 +08:00
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result = regmap_write(st->map, st->reg->int_enable,
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2016-02-18 23:53:12 +08:00
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INV_MPU6050_BIT_DATA_RDY_EN);
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2013-02-02 08:26:00 +08:00
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return result;
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}
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/**
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* inv_mpu6050_read_fifo() - Transfer data from hardware FIFO to KFIFO.
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*/
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irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct inv_mpu6050_state *st = iio_priv(indio_dev);
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size_t bytes_per_datum;
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int result;
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u8 data[INV_MPU6050_OUTPUT_DATA_SIZE];
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u16 fifo_count;
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2018-05-28 21:22:04 +08:00
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s64 timestamp;
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2018-04-21 00:54:00 +08:00
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int int_status;
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2018-05-22 22:18:20 +08:00
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size_t i, nb;
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2013-02-02 08:26:00 +08:00
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2017-06-07 21:41:42 +08:00
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mutex_lock(&st->lock);
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2018-04-21 00:54:00 +08:00
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/* ack interrupt and check status */
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result = regmap_read(st->map, st->reg->int_status, &int_status);
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if (result) {
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dev_err(regmap_get_device(st->map),
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"failed to ack interrupt\n");
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goto flush_fifo;
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}
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2018-05-22 22:18:21 +08:00
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/* handle fifo overflow by reseting fifo */
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if (int_status & INV_MPU6050_BIT_FIFO_OVERFLOW_INT)
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goto flush_fifo;
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2018-04-21 00:54:00 +08:00
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if (!(int_status & INV_MPU6050_BIT_RAW_DATA_RDY_INT)) {
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dev_warn(regmap_get_device(st->map),
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"spurious interrupt with status 0x%x\n", int_status);
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goto end_session;
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}
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2013-02-02 08:26:00 +08:00
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if (!(st->chip_config.accl_fifo_enable |
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st->chip_config.gyro_fifo_enable))
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goto end_session;
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bytes_per_datum = 0;
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if (st->chip_config.accl_fifo_enable)
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bytes_per_datum += INV_MPU6050_BYTES_PER_3AXIS_SENSOR;
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if (st->chip_config.gyro_fifo_enable)
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bytes_per_datum += INV_MPU6050_BYTES_PER_3AXIS_SENSOR;
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2019-04-03 14:28:56 +08:00
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if (st->chip_type == INV_ICM20602)
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bytes_per_datum += INV_ICM20602_BYTES_PER_TEMP_SENSOR;
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2013-02-02 08:26:00 +08:00
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/*
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2018-05-02 01:56:41 +08:00
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* read fifo_count register to know how many bytes are inside the FIFO
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2013-02-02 08:26:00 +08:00
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* right now
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*/
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2016-02-18 23:53:12 +08:00
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result = regmap_bulk_read(st->map, st->reg->fifo_count_h, data,
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INV_MPU6050_FIFO_COUNT_BYTE);
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2016-02-12 19:44:43 +08:00
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if (result)
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2013-02-02 08:26:00 +08:00
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goto end_session;
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2018-05-22 22:18:20 +08:00
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fifo_count = get_unaligned_be16(&data[0]);
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/* compute and process all complete datum */
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nb = fifo_count / bytes_per_datum;
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2018-05-28 21:22:04 +08:00
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inv_mpu6050_update_period(st, pf->timestamp, nb);
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2018-05-22 22:18:20 +08:00
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for (i = 0; i < nb; ++i) {
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2016-02-12 19:44:43 +08:00
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result = regmap_bulk_read(st->map, st->reg->fifo_r_w,
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data, bytes_per_datum);
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if (result)
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2013-02-02 08:26:00 +08:00
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goto flush_fifo;
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2018-04-30 18:14:10 +08:00
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/* skip first samples if needed */
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2018-05-22 22:18:20 +08:00
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if (st->skip_samples) {
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2018-04-30 18:14:10 +08:00
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st->skip_samples--;
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2018-05-22 22:18:20 +08:00
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continue;
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}
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2018-05-28 21:22:04 +08:00
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timestamp = inv_mpu6050_get_timestamp(st);
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2018-05-22 22:18:20 +08:00
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iio_push_to_buffers_with_timestamp(indio_dev, data, timestamp);
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}
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2013-02-02 08:26:00 +08:00
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end_session:
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2017-06-07 21:41:42 +08:00
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mutex_unlock(&st->lock);
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2013-02-02 08:26:00 +08:00
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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flush_fifo:
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/* Flush HW and SW FIFOs. */
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inv_reset_fifo(indio_dev);
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2017-06-07 21:41:42 +08:00
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mutex_unlock(&st->lock);
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2013-02-02 08:26:00 +08:00
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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