UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenCloudOS-Kernel/drivers/clk/mediatek/clk-mt8192-mm.c

110 lines
3.9 KiB
C
Raw Normal View History

clk: mediatek: Add MT8192 mmsys clock support Add MT8192 mmsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26 18:57:15 +08:00
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright (c) 2021 MediaTek Inc.
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt8192-clk.h>
static const struct mtk_gate_regs mm0_cg_regs = {
.set_ofs = 0x104,
.clr_ofs = 0x108,
.sta_ofs = 0x100,
};
static const struct mtk_gate_regs mm1_cg_regs = {
.set_ofs = 0x114,
.clr_ofs = 0x118,
.sta_ofs = 0x110,
};
static const struct mtk_gate_regs mm2_cg_regs = {
.set_ofs = 0x1a4,
.clr_ofs = 0x1a8,
.sta_ofs = 0x1a0,
};
#define GATE_MM0(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MM2(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
/* MM0 */
GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
/* MM1 */
GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
/* MM2 */
GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
};
static int clk_mt8192_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
clk: mediatek: Replace 'struct clk' with 'struct clk_hw' As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. Instead of adding new APIs to the MediaTek clk driver library mirroring the existing ones, moving all drivers to the new APIs, and then removing the old ones, just migrate everything at the same time. This involves replacing 'struct clk' with 'struct clk_hw', and 'struct clk_onecell_data' with 'struct clk_hw_onecell_data', and fixing up all usages. For now, the clk_register() and co. usage is retained, with __clk_get_hw() and (struct clk_hw *)->clk used to bridge the difference between the APIs. These will be replaced in subsequent patches. Fix up mtk_{alloc,free}_clk_data to use 'struct clk_hw' by hand. Fix up all other affected call sites with the following coccinelle script. // Replace type @@ @@ - struct clk_onecell_data + struct clk_hw_onecell_data // Replace of_clk_add_provider() & of_clk_src_simple_get() @@ expression NP, DATA; symbol of_clk_src_onecell_get; @@ - of_clk_add_provider( + of_clk_add_hw_provider( NP, - of_clk_src_onecell_get, + of_clk_hw_onecell_get, DATA ) // Fix register/unregister @@ identifier CD; expression E; identifier fn =~ "unregister"; @@ fn(..., - CD->clks[E] + CD->hws[E]->clk ,... ); // Fix calls to clk_prepare_enable() @@ identifier CD; expression E; @@ clk_prepare_enable( - CD->clks[E] + CD->hws[E]->clk ); // Fix pointer assignment @@ identifier CD; identifier CLK; expression E; @@ - CD->clks[E] + CD->hws[E] = ( - CLK + __clk_get_hw(CLK) | ERR_PTR(...) ) ; // Fix pointer usage @@ identifier CD; expression E; @@ - CD->clks[E] + CD->hws[E] // Fix mtk_clk_pll_get_base() @@ symbol clk, hw, data; @@ mtk_clk_pll_get_base( - struct clk *clk, + struct clk_hw *hw, const struct mtk_pll_data *data ) { - struct clk_hw *hw = __clk_get_hw(clk); ... } // Fix mtk_clk_pll_get_base() usage @@ identifier CD; expression E; @@ mtk_clk_pll_get_base( - CD->clks[E] + CD->hws[E]->clk ,... ); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19 15:16:08 +08:00
struct clk_hw_onecell_data *clk_data;
clk: mediatek: Add MT8192 mmsys clock support Add MT8192 mmsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26 18:57:15 +08:00
int r;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
if (!clk_data)
return -ENOMEM;
clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates() Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device") introduces a helper function for the sole purpose of propagating a struct device pointer to the clk API when registering the mtk-gate clocks to take advantage of Runtime PM when/where needed and where a power domain is defined in devicetree. Function mtk_clk_register_gates() then becomes a wrapper around the new mtk_clk_register_gates_with_dev() function that will simply pass NULL as struct device: this is essential when registering drivers with CLK_OF_DECLARE instead of as a platform device, as there will be no struct device to pass... but we can as well simply have only one function that always takes such pointer as a param and pass NULL when unavoidable. This commit removes the mtk_clk_register_gates() wrapper and renames mtk_clk_register_gates_with_dev() to the former and all of the calls to either of the two functions were fixed in all drivers in order to reflect this change; also, to improve consistency with other kernel functions, the pointer to struct device was moved as the first param. Since a lot of MediaTek clock drivers are actually registering as a platform device, but were still registering the mtk-gate clocks without passing any struct device to the clock framework, they've been changed to pass a valid one now, as to make all those platforms able to use runtime power management where available. While at it, some much needed indentation changes were also done. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com Tested-by: Mingming Su <mingming.su@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-01-20 17:20:33 +08:00
r = mtk_clk_register_gates(&pdev->dev, node, mm_clks,
ARRAY_SIZE(mm_clks), clk_data);
clk: mediatek: Add MT8192 mmsys clock support Add MT8192 mmsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26 18:57:15 +08:00
if (r)
return r;
clk: mediatek: Replace 'struct clk' with 'struct clk_hw' As part of the effort to improve the MediaTek clk drivers, the next step is to switch from the old 'struct clk' clk prodivder APIs to the new 'struct clk_hw' ones. Instead of adding new APIs to the MediaTek clk driver library mirroring the existing ones, moving all drivers to the new APIs, and then removing the old ones, just migrate everything at the same time. This involves replacing 'struct clk' with 'struct clk_hw', and 'struct clk_onecell_data' with 'struct clk_hw_onecell_data', and fixing up all usages. For now, the clk_register() and co. usage is retained, with __clk_get_hw() and (struct clk_hw *)->clk used to bridge the difference between the APIs. These will be replaced in subsequent patches. Fix up mtk_{alloc,free}_clk_data to use 'struct clk_hw' by hand. Fix up all other affected call sites with the following coccinelle script. // Replace type @@ @@ - struct clk_onecell_data + struct clk_hw_onecell_data // Replace of_clk_add_provider() & of_clk_src_simple_get() @@ expression NP, DATA; symbol of_clk_src_onecell_get; @@ - of_clk_add_provider( + of_clk_add_hw_provider( NP, - of_clk_src_onecell_get, + of_clk_hw_onecell_get, DATA ) // Fix register/unregister @@ identifier CD; expression E; identifier fn =~ "unregister"; @@ fn(..., - CD->clks[E] + CD->hws[E]->clk ,... ); // Fix calls to clk_prepare_enable() @@ identifier CD; expression E; @@ clk_prepare_enable( - CD->clks[E] + CD->hws[E]->clk ); // Fix pointer assignment @@ identifier CD; identifier CLK; expression E; @@ - CD->clks[E] + CD->hws[E] = ( - CLK + __clk_get_hw(CLK) | ERR_PTR(...) ) ; // Fix pointer usage @@ identifier CD; expression E; @@ - CD->clks[E] + CD->hws[E] // Fix mtk_clk_pll_get_base() @@ symbol clk, hw, data; @@ mtk_clk_pll_get_base( - struct clk *clk, + struct clk_hw *hw, const struct mtk_pll_data *data ) { - struct clk_hw *hw = __clk_get_hw(clk); ... } // Fix mtk_clk_pll_get_base() usage @@ identifier CD; expression E; @@ mtk_clk_pll_get_base( - CD->clks[E] + CD->hws[E]->clk ,... ); Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-05-19 15:16:08 +08:00
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
clk: mediatek: Add MT8192 mmsys clock support Add MT8192 mmsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26 18:57:15 +08:00
}
static struct platform_driver clk_mt8192_mm_drv = {
.probe = clk_mt8192_mm_probe,
.driver = {
.name = "clk-mt8192-mm",
},
};
builtin_platform_driver(clk_mt8192_mm_drv);