2010-10-07 21:08:49 +08:00
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/*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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2010-10-07 21:08:52 +08:00
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flags = hard_local_irq_save();
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2010-10-07 21:08:49 +08:00
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SICA_IWR0);
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iwr1 = bfin_read32(SICA_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SICA_IWR0, IWR_ENABLE(0));
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bfin_write32(SICA_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SICA_IWR0, iwr0);
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bfin_write32(SICA_IWR1, iwr1);
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2010-10-07 21:08:52 +08:00
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hard_local_irq_restore(flags);
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2010-10-07 21:08:49 +08:00
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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2010-10-07 21:08:52 +08:00
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flags = hard_local_irq_save();
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2010-10-07 21:08:49 +08:00
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SICA_IWR0);
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iwr1 = bfin_read32(SICA_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SICA_IWR0, IWR_ENABLE(0));
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bfin_write32(SICA_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SICA_IWR0, iwr0);
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bfin_write32(SICA_IWR1, iwr1);
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2010-10-07 21:08:52 +08:00
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hard_local_irq_restore(flags);
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2010-10-07 21:08:49 +08:00
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}
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#endif /* _MACH_PLL_H */
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