608 lines
19 KiB
C
608 lines
19 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _HWMGR_H_
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#define _HWMGR_H_
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#include "amd_powerplay.h"
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#include "pp_instance.h"
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#include "hardwaremanager.h"
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#include "pp_power_source.h"
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struct pp_instance;
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struct pp_hwmgr;
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struct pp_hw_power_state;
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struct pp_power_state;
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struct PP_VCEState;
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enum PP_Result {
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PP_Result_TableImmediateExit = 0x13,
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};
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#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
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#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
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#define PCIE_PERF_REQ_GEN1 2
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#define PCIE_PERF_REQ_GEN2 3
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#define PCIE_PERF_REQ_GEN3 4
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enum PHM_BackEnd_Magic {
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PHM_Dummy_Magic = 0xAA5555AA,
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PHM_RV770_Magic = 0xDCBAABCD,
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PHM_Kong_Magic = 0x239478DF,
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PHM_NIslands_Magic = 0x736C494E,
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PHM_Sumo_Magic = 0x8339FA11,
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PHM_SIslands_Magic = 0x369431AC,
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PHM_Trinity_Magic = 0x96751873,
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PHM_CIslands_Magic = 0x38AC78B0,
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PHM_Kv_Magic = 0xDCBBABC0,
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PHM_VIslands_Magic = 0x20130307,
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PHM_Cz_Magic = 0x67DCBA25
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};
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enum PP_DAL_POWERLEVEL {
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PP_DAL_POWERLEVEL_INVALID = 0,
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PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
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PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
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PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
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PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
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};
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#define PHM_PCIE_POWERGATING_TARGET_GFX 0
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#define PHM_PCIE_POWERGATING_TARGET_DDI 1
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#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
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#define PHM_PCIE_POWERGATING_TARGET_PHY 3
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typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
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void *output, void *storage, int result);
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typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
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struct phm_acp_arbiter {
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uint32_t acpclk;
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};
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struct phm_uvd_arbiter {
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uint32_t vclk;
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uint32_t dclk;
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uint32_t vclk_ceiling;
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uint32_t dclk_ceiling;
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};
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struct phm_vce_arbiter {
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uint32_t evclk;
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uint32_t ecclk;
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};
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struct phm_gfx_arbiter {
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uint32_t sclk;
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uint32_t mclk;
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uint32_t sclk_over_drive;
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uint32_t mclk_over_drive;
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uint32_t sclk_threshold;
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uint32_t num_cus;
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};
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/* Entries in the master tables */
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struct phm_master_table_item {
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phm_check_function isFunctionNeededInRuntimeTable;
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phm_table_function tableFunction;
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};
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enum phm_master_table_flag {
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PHM_MasterTableFlag_None = 0,
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PHM_MasterTableFlag_ExitOnError = 1,
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};
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/* The header of the master tables */
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struct phm_master_table_header {
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uint32_t storage_size;
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uint32_t flags;
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struct phm_master_table_item *master_list;
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};
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struct phm_runtime_table_header {
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uint32_t storage_size;
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bool exit_error;
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phm_table_function *function_list;
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};
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struct phm_clock_array {
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uint32_t count;
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uint32_t values[1];
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};
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struct phm_clock_voltage_dependency_record {
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uint32_t clk;
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uint32_t v;
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};
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struct phm_vceclock_voltage_dependency_record {
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uint32_t ecclk;
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uint32_t evclk;
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uint32_t v;
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};
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struct phm_uvdclock_voltage_dependency_record {
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uint32_t vclk;
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uint32_t dclk;
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uint32_t v;
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};
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struct phm_samuclock_voltage_dependency_record {
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uint32_t samclk;
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uint32_t v;
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};
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struct phm_acpclock_voltage_dependency_record {
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uint32_t acpclk;
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uint32_t v;
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};
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struct phm_clock_voltage_dependency_table {
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uint32_t count; /* Number of entries. */
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struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
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};
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struct phm_phase_shedding_limits_record {
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uint32_t Voltage;
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uint32_t Sclk;
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uint32_t Mclk;
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};
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extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
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struct phm_runtime_table_header *rt_table,
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void *input, void *output);
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extern int phm_construct_table(struct pp_hwmgr *hwmgr,
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struct phm_master_table_header *master_table,
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struct phm_runtime_table_header *rt_table);
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extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
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struct phm_runtime_table_header *rt_table);
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struct phm_uvd_clock_voltage_dependency_record {
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uint32_t vclk;
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uint32_t dclk;
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uint32_t v;
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};
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struct phm_uvd_clock_voltage_dependency_table {
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uint8_t count;
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struct phm_uvd_clock_voltage_dependency_record entries[1];
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};
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struct phm_acp_clock_voltage_dependency_record {
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uint32_t acpclk;
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uint32_t v;
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};
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struct phm_acp_clock_voltage_dependency_table {
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uint32_t count;
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struct phm_acp_clock_voltage_dependency_record entries[1];
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};
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struct phm_vce_clock_voltage_dependency_record {
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uint32_t ecclk;
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uint32_t evclk;
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uint32_t v;
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};
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struct phm_phase_shedding_limits_table {
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uint32_t count;
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struct phm_phase_shedding_limits_record entries[1];
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};
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struct phm_vceclock_voltage_dependency_table {
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uint8_t count; /* Number of entries. */
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struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
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};
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struct phm_uvdclock_voltage_dependency_table {
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uint8_t count; /* Number of entries. */
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struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
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};
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struct phm_samuclock_voltage_dependency_table {
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uint8_t count; /* Number of entries. */
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struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
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};
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struct phm_acpclock_voltage_dependency_table {
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uint32_t count; /* Number of entries. */
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struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
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};
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struct phm_vce_clock_voltage_dependency_table {
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uint8_t count;
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struct phm_vce_clock_voltage_dependency_record entries[1];
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};
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struct pp_hwmgr_func {
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int (*backend_init)(struct pp_hwmgr *hw_mgr);
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int (*backend_fini)(struct pp_hwmgr *hw_mgr);
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int (*asic_setup)(struct pp_hwmgr *hw_mgr);
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int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
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int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, enum amd_dpm_forced_level level);
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int (*dynamic_state_management_enable)(struct pp_hwmgr *hw_mgr);
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int (*patch_boot_state)(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps);
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int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, unsigned long, struct pp_power_state *);
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int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
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};
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struct pp_table_func {
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int (*pptable_init)(struct pp_hwmgr *hw_mgr);
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int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
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int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
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int (*pptable_get_vce_state_table_entry)(
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struct pp_hwmgr *hwmgr,
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unsigned long i,
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struct PP_VCEState *vce_state,
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void **clock_info,
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unsigned long *flag);
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};
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union phm_cac_leakage_record {
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struct {
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uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
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uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
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};
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struct {
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uint16_t Vddc1;
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uint16_t Vddc2;
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uint16_t Vddc3;
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};
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};
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struct phm_cac_leakage_table {
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uint32_t count;
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union phm_cac_leakage_record entries[1];
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};
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struct phm_samu_clock_voltage_dependency_record {
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uint32_t samclk;
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uint32_t v;
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};
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struct phm_samu_clock_voltage_dependency_table {
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uint8_t count;
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struct phm_samu_clock_voltage_dependency_record entries[1];
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};
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struct phm_cac_tdp_table {
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uint16_t usTDP;
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uint16_t usConfigurableTDP;
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uint16_t usTDC;
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uint16_t usBatteryPowerLimit;
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uint16_t usSmallPowerLimit;
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uint16_t usLowCACLeakage;
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uint16_t usHighCACLeakage;
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uint16_t usMaximumPowerDeliveryLimit;
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uint16_t usOperatingTempMinLimit;
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uint16_t usOperatingTempMaxLimit;
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uint16_t usOperatingTempStep;
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uint16_t usOperatingTempHyst;
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uint16_t usDefaultTargetOperatingTemp;
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uint16_t usTargetOperatingTemp;
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uint16_t usPowerTuneDataSetID;
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uint16_t usSoftwareShutdownTemp;
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uint16_t usClockStretchAmount;
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uint16_t usTemperatureLimitHotspot;
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uint16_t usTemperatureLimitLiquid1;
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uint16_t usTemperatureLimitLiquid2;
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uint16_t usTemperatureLimitVrVddc;
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uint16_t usTemperatureLimitVrMvdd;
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uint16_t usTemperatureLimitPlx;
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uint8_t ucLiquid1_I2C_address;
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uint8_t ucLiquid2_I2C_address;
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uint8_t ucLiquid_I2C_Line;
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uint8_t ucVr_I2C_address;
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uint8_t ucVr_I2C_Line;
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uint8_t ucPlx_I2C_address;
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uint8_t ucPlx_I2C_Line;
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};
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struct phm_ppm_table {
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uint8_t ppm_design;
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uint16_t cpu_core_number;
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uint32_t platform_tdp;
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uint32_t small_ac_platform_tdp;
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uint32_t platform_tdc;
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uint32_t small_ac_platform_tdc;
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uint32_t apu_tdp;
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uint32_t dgpu_tdp;
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uint32_t dgpu_ulv_power;
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uint32_t tj_max;
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};
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struct phm_vq_budgeting_record {
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uint32_t ulCUs;
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uint32_t ulSustainableSOCPowerLimitLow;
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uint32_t ulSustainableSOCPowerLimitHigh;
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uint32_t ulMinSclkLow;
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uint32_t ulMinSclkHigh;
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uint8_t ucDispConfig;
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uint32_t ulDClk;
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uint32_t ulEClk;
|
||
|
|
uint32_t ulSustainableSclk;
|
||
|
|
uint32_t ulSustainableCUs;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct phm_vq_budgeting_table {
|
||
|
|
uint8_t numEntries;
|
||
|
|
struct phm_vq_budgeting_record entries[1];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct phm_clock_and_voltage_limits {
|
||
|
|
uint32_t sclk;
|
||
|
|
uint32_t mclk;
|
||
|
|
uint16_t vddc;
|
||
|
|
uint16_t vddci;
|
||
|
|
uint16_t vddgfx;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
struct phm_dynamic_state_info {
|
||
|
|
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
|
||
|
|
struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
|
||
|
|
struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
|
||
|
|
struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
|
||
|
|
struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
|
||
|
|
struct phm_clock_array *valid_sclk_values;
|
||
|
|
struct phm_clock_array *valid_mclk_values;
|
||
|
|
struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
|
||
|
|
struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
|
||
|
|
uint32_t mclk_sclk_ratio;
|
||
|
|
uint32_t sclk_mclk_delta;
|
||
|
|
uint32_t vddc_vddci_delta;
|
||
|
|
uint32_t min_vddc_for_pcie_gen2;
|
||
|
|
struct phm_cac_leakage_table *cac_leakage_table;
|
||
|
|
struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
|
||
|
|
|
||
|
|
struct phm_vce_clock_voltage_dependency_table
|
||
|
|
*vce_clocl_voltage_dependency_table;
|
||
|
|
struct phm_uvd_clock_voltage_dependency_table
|
||
|
|
*uvd_clocl_voltage_dependency_table;
|
||
|
|
struct phm_acp_clock_voltage_dependency_table
|
||
|
|
*acp_clock_voltage_dependency_table;
|
||
|
|
struct phm_samu_clock_voltage_dependency_table
|
||
|
|
*samu_clock_voltage_dependency_table;
|
||
|
|
|
||
|
|
struct phm_ppm_table *ppm_parameter_table;
|
||
|
|
struct phm_cac_tdp_table *cac_dtp_table;
|
||
|
|
struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
|
||
|
|
struct phm_vq_budgeting_table *vq_budgeting_table;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct pp_hwmgr {
|
||
|
|
uint32_t chip_family;
|
||
|
|
uint32_t chip_id;
|
||
|
|
uint32_t hw_revision;
|
||
|
|
uint32_t sub_sys_id;
|
||
|
|
uint32_t sub_vendor_id;
|
||
|
|
|
||
|
|
void *device;
|
||
|
|
struct pp_smumgr *smumgr;
|
||
|
|
const void *soft_pp_table;
|
||
|
|
enum amd_dpm_forced_level dpm_level;
|
||
|
|
|
||
|
|
struct phm_gfx_arbiter gfx_arbiter;
|
||
|
|
struct phm_acp_arbiter acp_arbiter;
|
||
|
|
struct phm_uvd_arbiter uvd_arbiter;
|
||
|
|
struct phm_vce_arbiter vce_arbiter;
|
||
|
|
uint32_t usec_timeout;
|
||
|
|
void *pptable;
|
||
|
|
struct phm_platform_descriptor platform_descriptor;
|
||
|
|
void *backend;
|
||
|
|
enum PP_DAL_POWERLEVEL dal_power_level;
|
||
|
|
struct phm_dynamic_state_info dyn_state;
|
||
|
|
struct phm_runtime_table_header setup_asic;
|
||
|
|
struct phm_runtime_table_header disable_dynamic_state_management;
|
||
|
|
struct phm_runtime_table_header enable_dynamic_state_management;
|
||
|
|
const struct pp_hwmgr_func *hwmgr_func;
|
||
|
|
const struct pp_table_func *pptable_func;
|
||
|
|
struct pp_power_state *ps;
|
||
|
|
enum pp_power_source power_source;
|
||
|
|
uint32_t num_ps;
|
||
|
|
uint32_t ps_size;
|
||
|
|
struct pp_power_state *current_ps;
|
||
|
|
struct pp_power_state *request_ps;
|
||
|
|
struct pp_power_state *boot_ps;
|
||
|
|
struct pp_power_state *uvd_ps;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
extern int hwmgr_init(struct amd_pp_init *pp_init,
|
||
|
|
struct pp_instance *handle);
|
||
|
|
|
||
|
|
extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
|
||
|
|
|
||
|
|
extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
|
||
|
|
|
||
|
|
extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
|
||
|
|
uint32_t value, uint32_t mask);
|
||
|
|
|
||
|
|
extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
|
||
|
|
uint32_t index, uint32_t value, uint32_t mask);
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
|
||
|
|
uint32_t indirect_port,
|
||
|
|
uint32_t index,
|
||
|
|
uint32_t value,
|
||
|
|
uint32_t mask);
|
||
|
|
|
||
|
|
extern void phm_wait_for_indirect_register_unequal(
|
||
|
|
struct pp_hwmgr *hwmgr,
|
||
|
|
uint32_t indirect_port,
|
||
|
|
uint32_t index,
|
||
|
|
uint32_t value,
|
||
|
|
uint32_t mask);
|
||
|
|
|
||
|
|
#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
|
||
|
|
#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
|
||
|
|
|
||
|
|
#define PHM_SET_FIELD(origval, reg, field, fieldval) \
|
||
|
|
(((origval) & ~PHM_FIELD_MASK(reg, field)) | \
|
||
|
|
(PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
|
||
|
|
|
||
|
|
#define PHM_GET_FIELD(value, reg, field) \
|
||
|
|
(((value) & PHM_FIELD_MASK(reg, field)) >> \
|
||
|
|
PHM_FIELD_SHIFT(reg, field))
|
||
|
|
|
||
|
|
|
||
|
|
#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \
|
||
|
|
phm_wait_on_register(hwmgr, index, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \
|
||
|
|
phm_wait_for_register_unequal(hwmgr, index, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
|
||
|
|
phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
|
||
|
|
phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
|
||
|
|
phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
|
||
|
|
phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
|
||
|
|
|
||
|
|
/* Operations on named registers. */
|
||
|
|
|
||
|
|
#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \
|
||
|
|
PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
|
||
|
|
PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
|
||
|
|
PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
|
||
|
|
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
|
||
|
|
PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
|
||
|
|
PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
|
||
|
|
|
||
|
|
/* Operations on named fields. */
|
||
|
|
|
||
|
|
#define PHM_READ_FIELD(device, reg, field) \
|
||
|
|
PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
|
||
|
|
|
||
|
|
#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
|
||
|
|
PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
|
||
|
|
reg, field)
|
||
|
|
|
||
|
|
#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
|
||
|
|
PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
|
||
|
|
reg, field)
|
||
|
|
|
||
|
|
#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
|
||
|
|
cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
|
||
|
|
cgs_read_register(device, mm##reg), reg, field, fieldval))
|
||
|
|
|
||
|
|
#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
|
||
|
|
cgs_write_ind_register(device, port, ix##reg, \
|
||
|
|
PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
|
||
|
|
reg, field, fieldval))
|
||
|
|
|
||
|
|
#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
|
||
|
|
cgs_write_ind_register(device, port, ix##reg, \
|
||
|
|
PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
|
||
|
|
reg, field, fieldval))
|
||
|
|
|
||
|
|
#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \
|
||
|
|
PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \
|
||
|
|
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
|
||
|
|
PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
|
||
|
|
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
|
||
|
|
PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
|
||
|
|
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
|
||
|
|
PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \
|
||
|
|
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
|
||
|
|
PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
|
||
|
|
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
|
||
|
|
PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
|
||
|
|
<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
/* Operations on arrays of registers & fields. */
|
||
|
|
|
||
|
|
#define PHM_READ_ARRAY_REGISTER(device, reg, offset) \
|
||
|
|
cgs_read_register(device, mm##reg + (offset))
|
||
|
|
|
||
|
|
#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \
|
||
|
|
cgs_write_register(device, mm##reg + (offset), value)
|
||
|
|
|
||
|
|
#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \
|
||
|
|
PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
|
||
|
|
|
||
|
|
#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \
|
||
|
|
PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
|
||
|
|
|
||
|
|
#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
|
||
|
|
PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
|
||
|
|
|
||
|
|
#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
|
||
|
|
PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \
|
||
|
|
PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \
|
||
|
|
reg, field, fieldvalue))
|
||
|
|
|
||
|
|
#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
|
||
|
|
PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
|
||
|
|
(fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
|
||
|
|
PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \
|
||
|
|
PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
|
||
|
|
(fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
|
||
|
|
PHM_FIELD_MASK(reg, field))
|
||
|
|
|
||
|
|
#endif /* _HWMGR_H_ */
|