License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 22:07:57 +08:00
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# SPDX-License-Identifier: GPL-2.0
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2007-02-12 02:57:36 +08:00
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#
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# Makefile for MMC/SD host controller drivers
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#
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2017-08-30 20:22:12 +08:00
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obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
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armmmci-y := mmci.o
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armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
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2018-10-08 20:08:55 +08:00
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armmmci-$(CONFIG_MMC_STM32_SDMMC) += mmci_stm32_sdmmc.o
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2007-02-12 02:57:36 +08:00
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obj-$(CONFIG_MMC_PXA) += pxamci.o
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2009-01-07 00:04:14 +08:00
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obj-$(CONFIG_MMC_MXC) += mxcmmc.o
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2011-02-21 18:35:28 +08:00
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obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
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2007-02-12 02:57:36 +08:00
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obj-$(CONFIG_MMC_SDHCI) += sdhci.o
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2008-03-19 00:35:49 +08:00
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obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
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2018-07-11 15:56:17 +08:00
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sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
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2019-09-11 15:23:44 +08:00
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sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
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2011-12-27 21:48:43 +08:00
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obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o
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2012-11-24 04:17:34 +08:00
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obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
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2011-06-08 17:41:57 +08:00
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obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
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2011-06-08 17:41:58 +08:00
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obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
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2009-06-14 20:52:37 +08:00
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obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
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2013-03-21 16:27:19 +08:00
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obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
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2015-01-20 16:05:18 +08:00
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obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
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2019-09-10 09:41:06 +08:00
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obj-$(CONFIG_MMC_SDHCI_MILBEAUT) += sdhci-milbeaut.o
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2010-05-27 05:42:10 +08:00
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obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
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2018-12-11 02:35:07 +08:00
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obj-$(CONFIG_MMC_SDHCI_AM654) += sdhci_am654.o
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2007-02-12 02:57:36 +08:00
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obj-$(CONFIG_MMC_WBSD) += wbsd.o
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obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
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2018-12-02 18:30:46 +08:00
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obj-$(CONFIG_MMC_ALCOR) += alcor.o
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2015-06-15 19:20:48 +08:00
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obj-$(CONFIG_MMC_MTK) += mtk-sd.o
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2007-02-12 02:57:36 +08:00
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obj-$(CONFIG_MMC_OMAP) += omap.o
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2009-01-23 08:05:23 +08:00
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obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
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atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-07-01 00:35:03 +08:00
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obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
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2007-02-12 02:57:36 +08:00
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obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
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2009-02-14 16:07:26 +08:00
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obj-$(CONFIG_MMC_MVSDIO) += mvsdio.o
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2009-12-15 10:01:21 +08:00
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obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
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2013-01-22 07:43:46 +08:00
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obj-$(CONFIG_MMC_GOLDFISH) += android-goldfish.o
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2007-08-09 00:12:54 +08:00
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obj-$(CONFIG_MMC_SPI) += mmc_spi.o
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2008-12-30 23:15:28 +08:00
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ifeq ($(CONFIG_OF),y)
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obj-$(CONFIG_MMC_SPI) += of_mmc_spi.o
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endif
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2008-07-01 05:40:24 +08:00
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obj-$(CONFIG_MMC_S3C) += s3cmci.o
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2008-07-15 20:21:29 +08:00
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obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
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2008-07-15 23:02:21 +08:00
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obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
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2011-03-23 19:42:44 +08:00
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obj-$(CONFIG_MMC_TMIO_CORE) += tmio_mmc_core.o
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2017-06-21 22:00:29 +08:00
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obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_core.o
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2017-11-25 00:24:36 +08:00
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obj-$(CONFIG_MMC_SDHI_SYS_DMAC) += renesas_sdhi_sys_dmac.o
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obj-$(CONFIG_MMC_SDHI_INTERNAL_DMAC) += renesas_sdhi_internal_dmac.o
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mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
Here is another TMIO MMC variant found in Socionext UniPhier SoCs.
As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and
MFD glue") said, these MMC controllers use the IP from Panasonic.
However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip
was the first upstreamed user of this IP. The common driver code
for this IP is now called 'tmio-mmc-core' in Linux although it is a
historical misnomer.
Anyway, this driver select's MMC_TMIO_CORE to borrow the common code
from tmio-mmc-core.c
Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine
like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a
single DMA channel whereas Renesas chips request separate channels for
RX and TX.
Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine
like renesas_sdhi_internal_dmac.c The register map is almost the same,
so I guess Renesas and Socionext use the same internal DMA hardware.
The main difference is, the register offsets are doubled for Renesas.
Renesas Socionext
SDHI UniPhier
DM_CM_DTRAN_MODE 0x820 0x410
DM_CM_DTRAN_CTRL 0x828 0x414
DM_CM_RST 0x830 0x418
DM_CM_INFO1 0x840 0x420
DM_CM_INFO1_MASK 0x848 0x424
DM_CM_INFO2 0x850 0x428
DM_CM_INFO2_MASK 0x858 0x42c
DM_DTRAN_ADDR 0x880 0x440
DM_DTRAN_ADDREX --- 0x444
This comes from the difference of host->bus_shift; 2 for Renesas SoCs,
and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines
DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers.
It could be possible to factor out the DMA common code by introducing
some hooks to cope with platform quirks, but this patch does not touch
that for now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-08-23 12:44:18 +08:00
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obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
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2011-03-14 16:52:33 +08:00
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obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
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2009-06-18 02:22:39 +08:00
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obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
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2017-04-25 02:41:57 +08:00
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octeon-mmc-objs := cavium.o cavium-octeon.o
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obj-$(CONFIG_MMC_CAVIUM_OCTEON) += octeon-mmc.o
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2017-03-30 23:31:25 +08:00
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thunderx-mmc-objs := cavium.o cavium-thunderx.o
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obj-$(CONFIG_MMC_CAVIUM_THUNDERX) += thunderx-mmc.o
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2011-01-02 14:11:59 +08:00
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obj-$(CONFIG_MMC_DW) += dw_mmc.o
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2012-01-13 18:34:57 +08:00
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obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o
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2018-05-09 02:46:48 +08:00
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obj-$(CONFIG_MMC_DW_BLUEFIELD) += dw_mmc-bluefield.o
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2012-09-18 02:16:43 +08:00
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obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o
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2018-03-08 09:01:34 +08:00
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obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
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2014-01-09 22:35:11 +08:00
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obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
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2012-01-13 18:34:57 +08:00
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obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
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2014-08-19 12:36:14 +08:00
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obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
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2017-01-06 12:24:46 +08:00
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obj-$(CONFIG_MMC_DW_ZX) += dw_mmc-zx.o
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2010-05-27 05:41:59 +08:00
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obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
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2010-07-16 04:06:04 +08:00
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obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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2011-05-15 04:48:13 +08:00
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obj-$(CONFIG_MMC_VUB300) += vub300.o
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2010-09-02 22:15:08 +08:00
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obj-$(CONFIG_MMC_USHC) += ushc.o
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2012-11-18 10:33:06 +08:00
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obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
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2016-10-20 02:18:24 +08:00
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obj-$(CONFIG_MMC_MESON_GX) += meson-gx-mmc.o
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2020-05-13 04:41:47 +08:00
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obj-$(CONFIG_MMC_MESON_MX_SDHC) += meson-mx-sdhc-clkc.o meson-mx-sdhc.o
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mmc: meson-mx-sdio: Add a driver for the Amlogic Meson8 and Meson8b SoCs
Add a driver for the SDIO/MMC host found on the Amlogic Meson SoCs. This
is an MMC controller which provides an interface between the application
processor and various memory cards. It supports the SD specification
v2.0 and the eMMC specification v4.41.
The controller provides an internal "mux" which allows connecting up to
three MMC devices to it. Only one device can be used at a time though
since the registers are shared across all devices. The driver takes care
of synchronizing access (similar to the dw_mmc driver).
The maximum supported bus-width is 4-bits.
Amlogic's GPL kernel sources call the corresponding driver "aml_sdio" to
differentiate it from the other MMC controller in (at least the Meson8
and Meson8b) the SoCs (they call the other drivers aml_sdhc and
aml_sdhc_m8, which seem to support a bus-width of up to 8-bits). This
means that there are three different MMC host controller IP blocks from
Amlogic (each of them with completely own register layout and features):
- "SDIO": 1 and 4 bit bus width, support for high-speed modes up to
UHS-I SDR50, part of Meson6, Meson8 and Meson8b (the driver from this
patch targets this controller)
- "SDHC": 1, 4 and 8 bit bus width, compatible with standard iNAND
interface, support for speeds up to HS200 and MMC spec up to version
4.5x, part of Meson8 and Meson8b SoCs (there is no mainline driver
for this controller yet)
- "SDEMMC": 1, 4 and 8 bit bus width, support for speeds up to HS400
and MMC spec up to version 5.0, part of the Meson GX (64-bit) SoCs
(supported by the meson-gx MMC host driver)
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-03 19:24:17 +08:00
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obj-$(CONFIG_MMC_MESON_MX_SDIO) += meson-mx-sdio.o
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2014-04-09 21:54:11 +08:00
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obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o
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2014-05-12 20:04:48 +08:00
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obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
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2014-06-01 02:38:51 +08:00
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obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
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2014-11-12 00:54:55 +08:00
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obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o
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2017-03-08 17:19:03 +08:00
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obj-$(CONFIG_MMC_BCM2835) += bcm2835.o
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2019-09-16 23:45:44 +08:00
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obj-$(CONFIG_MMC_OWL) += owl-mmc.o
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2008-07-15 20:21:29 +08:00
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2012-11-09 20:53:34 +08:00
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obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
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2014-04-11 14:53:22 +08:00
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obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
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2012-11-09 20:53:34 +08:00
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2011-06-02 10:57:50 +08:00
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obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
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2016-12-08 20:50:55 +08:00
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obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
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2011-05-27 23:48:12 +08:00
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obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
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obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
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obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
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obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
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2013-12-03 02:02:36 +08:00
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obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o
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2019-08-07 08:36:29 +08:00
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obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o
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2015-07-29 22:22:47 +08:00
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obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
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2011-05-27 23:48:14 +08:00
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obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
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obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
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2018-07-06 15:23:55 +08:00
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obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
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2013-06-21 05:26:37 +08:00
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obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
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2015-02-10 08:06:30 +08:00
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obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
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2014-03-10 23:37:12 +08:00
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obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
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2014-07-09 23:07:32 +08:00
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|
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obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
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2016-01-14 09:15:45 +08:00
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obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o
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2016-06-17 00:47:16 +08:00
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|
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obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
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2017-09-06 19:45:55 +08:00
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|
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obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o
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2018-08-30 16:21:44 +08:00
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|
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obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o
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2017-11-29 21:41:05 +08:00
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|
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obj-$(CONFIG_MMC_CQHCI) += cqhci.o
|
mmc: Add MMC host software queue support
Now the MMC read/write stack will always wait for previous request is
completed by mmc_blk_rw_wait(), before sending a new request to hardware,
or queue a work to complete request, that will bring context switching
overhead and spend some extra time to poll the card for busy completion
for I/O writes via sending CMD13, especially for high I/O per second
rates, to affect the IO performance.
Thus this patch introduces MMC software queue interface based on the
hardware command queue engine's interfaces, which is similar with the
hardware command queue engine's idea, that can remove the context
switching. Moreover we set the default queue depth as 64 for software
queue, which allows more requests to be prepared, merged and inserted
into IO scheduler to improve performance, but we only allow 2 requests
in flight, that is enough to let the irq handler always trigger the
next request without a context switch, as well as avoiding a long latency.
Moreover the host controller should support HW busy detection for I/O
operations when enabling the host software queue. That means, the host
controller must not complete a data transfer request, until after the
card stops signals busy.
From the fio testing data in cover letter, we can see the software
queue can improve some performance with 4K block size, increasing
about 16% for random read, increasing about 90% for random write,
though no obvious improvement for sequential read and write.
Moreover we can expand the software queue interface to support MMC
packed request or packed command in future.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Baolin Wang <baolin.wang7@gmail.com>
Link: https://lore.kernel.org/r/4409c1586a9b3ed20d57ad2faf6c262fc3ccb6e2.1581478568.git.baolin.wang7@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-02-12 12:12:56 +08:00
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obj-$(CONFIG_MMC_HSQ) += mmc_hsq.o
|
2009-12-18 07:27:19 +08:00
|
|
|
|
2009-06-13 18:37:59 +08:00
|
|
|
ifeq ($(CONFIG_CB710_DEBUG),y)
|
|
|
|
|
CFLAGS-cb710-mmc += -DDEBUG
|
|
|
|
|
endif
|
2017-03-30 23:22:59 +08:00
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obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
|
2017-03-30 23:23:00 +08:00
|
|
|
sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o
|