2006-01-15 06:57:39 +08:00
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#
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# Makefile for the PowerPC 85xx linux kernel.
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#
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2008-11-19 23:35:56 +08:00
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obj-$(CONFIG_SMP) += smp.o
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2011-11-24 15:07:08 +08:00
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obj-y += common.o
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2011-11-18 01:56:16 +08:00
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powerpc/85xx: Add BSC9131 RDB Support
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte
shared L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel
Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
UP/DL Channel processing, and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
Inversion operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
with ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network
acceleration including IEEE 1588. v2 hardware support and
virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single
port) and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD
support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
BSC9131RDB Overview
----------------------
BSC9131 SoC
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
Linux runs on e500v2 core and access some DSP peripherals like AIC
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-03-22 12:54:15 +08:00
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obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
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2014-05-15 15:45:33 +08:00
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obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o
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2013-08-02 14:39:11 +08:00
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obj-$(CONFIG_C293_PCIE) += c293pcie.o
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2006-02-11 07:01:06 +08:00
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obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
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2006-09-22 02:31:26 +08:00
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obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
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2006-04-03 06:42:40 +08:00
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obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
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2008-07-02 14:36:15 +08:00
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obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
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2007-08-17 22:22:09 +08:00
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obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
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2007-02-18 06:29:36 +08:00
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obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
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2009-08-07 23:35:16 +08:00
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obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
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2011-06-03 04:28:08 +08:00
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obj-$(CONFIG_P1010_RDB) += p1010rdb.o
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2010-07-03 06:25:03 +08:00
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obj-$(CONFIG_P1022_DS) += p1022_ds.o
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2012-07-24 07:12:29 +08:00
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obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
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2014-05-06 02:23:15 +08:00
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obj-$(CONFIG_P1023_RDB) += p1023_rdb.o
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2013-11-06 17:08:03 +08:00
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obj-$(CONFIG_TWR_P102x) += twr_p102x.o
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2013-09-26 09:42:27 +08:00
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obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
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2008-01-24 13:42:44 +08:00
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obj-$(CONFIG_STX_GP3) += stx_gp3.o
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2008-01-25 13:53:03 +08:00
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obj-$(CONFIG_TQM85xx) += tqm85xx.o
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2008-01-25 07:41:27 +08:00
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obj-$(CONFIG_SBC8548) += sbc8548.o
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2013-02-13 22:09:00 +08:00
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obj-$(CONFIG_PPA8548) += ppa8548.o
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powerpc/85xx: Add support for the "socrates" board (MPC8544).
Supported are Ethernet, serial console, I2C, I2C-based RTC and
temperature sensors, NOR and NAND flash, PCI, USB, CAN and Lime
display controller.
The multiplexing of FPGA interrupts onto PowerPC interrupt lines is
supported through our own fpga_pic interrupt controller driver.
For example the SJA1000 controller is level low sensitive connected to
fpga_pic line 2 and is routed to the second (of three) irq lines to
the CPU:
can@3,100 {
compatible = "philips,sja1000";
reg = <3 0x100 0x80>;
interrupts = <2 2>;
interrupts = <2 8 1>; // number, type, routing
interrupt-parent = <&fpga_pic>;
};
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-22 21:58:43 +08:00
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obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
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2008-03-06 23:17:16 +08:00
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obj-$(CONFIG_KSI8560) += ksi8560.o
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2009-08-07 23:35:16 +08:00
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obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
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2012-03-13 01:13:00 +08:00
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obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
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2012-07-11 08:26:48 +08:00
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obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
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powerpc: Add support for CTS-1000 GPIO controlled system poweroff
CTS-1000 is based on P4080. GPIO 27 is used to signal the FPGA to
switch off power, and also associates IRQ 8 with front-panel button
press (which we use to call orderly_poweroff()).
The relevant device-tree looks like this:
gpio0: gpio@130000 {
compatible = "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
/* Allows powering off the system via GPIO signal. */
gpio-halt@27 {
compatible = "sgy,gpio-halt";
gpios = <&gpio0 27 0>;
interrupts = <8 1 0 0>;
};
};
Because the driver cannot match on sgy,gpio-halt (because the node is never
processed through of_platform), it matches on fsl,qoriq-gpio and then
checks child nodes for the matching sgy,gpio-halt. This also ensures that
the GPIO controller is detected prior to sgy_cts1000's probe callback,
since that node wont match via of_platform until the controller is
registered.
Also, because the GPIO handler for triggering system poweroff might sleep,
the IRQ uses a workqueue to call orderly_poweroff().
As a final note, this driver may be expanded for other features specific to
the CTS-1000.
Signed-off-by: Ben Collins <ben.c@servergy.com>
Cc: Jack Smith <jack.s@servergy.com>
Cc: Vihar Rai <vihar.r@servergy.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-12-17 12:19:28 +08:00
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obj-$(CONFIG_SGY_CTS1000) += sgy_cts1000.o
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