2009-09-01 13:25:57 +08:00
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#define R100_TRACK_MAX_TEXTURE 3
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#define R200_TRACK_MAX_TEXTURE 6
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#define R300_TRACK_MAX_TEXTURE 16
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#define R100_MAX_CB 1
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#define R300_MAX_CB 4
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/*
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* CS functions
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*/
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struct r100_cs_track_cb {
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2009-11-20 21:29:23 +08:00
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struct radeon_bo *robj;
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2009-09-01 13:25:57 +08:00
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unsigned pitch;
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unsigned cpp;
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unsigned offset;
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};
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struct r100_cs_track_array {
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2009-11-20 21:29:23 +08:00
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struct radeon_bo *robj;
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2009-09-01 13:25:57 +08:00
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unsigned esize;
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};
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struct r100_cs_cube_info {
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2009-11-20 21:29:23 +08:00
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struct radeon_bo *robj;
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unsigned offset;
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2009-09-01 13:25:57 +08:00
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unsigned width;
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unsigned height;
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};
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2009-12-07 11:16:06 +08:00
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#define R100_TRACK_COMP_NONE 0
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#define R100_TRACK_COMP_DXT1 1
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#define R100_TRACK_COMP_DXT35 2
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2009-09-01 13:25:57 +08:00
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struct r100_cs_track_texture {
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2009-11-20 21:29:23 +08:00
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struct radeon_bo *robj;
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2009-09-01 13:25:57 +08:00
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struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
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unsigned pitch;
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unsigned width;
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unsigned height;
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unsigned num_levels;
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unsigned cpp;
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unsigned tex_coord_type;
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unsigned txdepth;
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unsigned width_11;
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unsigned height_11;
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bool use_pitch;
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bool enabled;
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2010-10-27 13:02:35 +08:00
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bool lookup_disable;
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2009-09-01 13:25:57 +08:00
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bool roundup_w;
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bool roundup_h;
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2009-12-07 11:16:06 +08:00
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unsigned compress_format;
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2009-09-01 13:25:57 +08:00
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};
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struct r100_cs_track {
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unsigned num_cb;
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unsigned num_texture;
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unsigned maxy;
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unsigned vtx_size;
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unsigned vap_vf_cntl;
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2010-02-22 04:24:15 +08:00
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unsigned vap_alt_nverts;
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2009-09-01 13:25:57 +08:00
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unsigned immd_dwords;
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unsigned num_arrays;
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unsigned max_indx;
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2009-12-17 13:02:28 +08:00
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unsigned color_channel_mask;
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2011-06-10 22:41:26 +08:00
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struct r100_cs_track_array arrays[16];
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2009-09-01 13:25:57 +08:00
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struct r100_cs_track_cb cb[R300_MAX_CB];
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struct r100_cs_track_cb zb;
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2011-02-14 08:01:10 +08:00
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struct r100_cs_track_cb aa;
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2009-09-01 13:25:57 +08:00
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struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
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bool z_enabled;
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bool separate_cube;
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2010-04-13 08:33:36 +08:00
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bool zb_cb_clear;
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2009-12-17 13:02:28 +08:00
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bool blend_read_enable;
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2011-02-13 02:21:35 +08:00
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bool cb_dirty;
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bool zb_dirty;
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bool tex_dirty;
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2011-02-14 08:01:10 +08:00
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bool aa_dirty;
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bool aaresolve;
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2009-09-01 13:25:57 +08:00
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};
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int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
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void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
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int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
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int r200_packet0_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg);
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2011-10-14 07:08:46 +08:00
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int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx,
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unsigned reg);
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int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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int idx);
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