2019-05-29 00:57:18 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2014-06-10 20:23:10 +08:00
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/*
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* Copyright 2014, Michael Ellerman, IBM Corp.
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*/
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#ifndef _SELFTESTS_POWERPC_REG_H
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#define _SELFTESTS_POWERPC_REG_H
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#define __stringify_1(x) #x
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#define __stringify(x) __stringify_1(x)
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2015-12-23 13:49:50 +08:00
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#define mfspr(rn) ({unsigned long rval; \
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asm volatile("mfspr %0," _str(rn) \
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: "=r" (rval)); rval; })
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#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
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: "r" ((unsigned long)(v)) \
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: "memory")
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2014-06-10 20:23:10 +08:00
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#define mb() asm volatile("sync" : : : "memory");
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2018-07-24 13:53:22 +08:00
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#define barrier() asm volatile("" : : : "memory");
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2014-06-10 20:23:10 +08:00
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#define SPRN_MMCR2 769
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#define SPRN_MMCRA 770
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#define SPRN_MMCR0 779
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#define MMCR0_PMAO 0x00000080
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#define MMCR0_PMAE 0x04000000
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#define MMCR0_FC 0x80000000
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#define SPRN_EBBHR 804
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#define SPRN_EBBRR 805
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#define SPRN_BESCR 806 /* Branch event status & control register */
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#define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */
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#define SPRN_BESCRSU 801 /* Branch event status & control set upper */
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#define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
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#define SPRN_BESCRRU 803 /* Branch event status & control REset upper */
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#define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
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#define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
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#define SPRN_PMC1 771
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#define SPRN_PMC2 772
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#define SPRN_PMC3 773
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#define SPRN_PMC4 774
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#define SPRN_PMC5 775
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#define SPRN_PMC6 776
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#define SPRN_SIAR 780
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#define SPRN_SDAR 781
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#define SPRN_SIER 768
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2016-09-30 10:32:50 +08:00
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#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
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2015-12-23 13:49:50 +08:00
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#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
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#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
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2016-09-30 10:32:50 +08:00
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#define SPRN_TAR 0x32f /* Target Address Register */
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#define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */
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#define SPRN_DSCR 0x03 /* Data Stream Control Register */
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#define SPRN_PPR 896 /* Program Priority Register */
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2018-05-25 10:11:44 +08:00
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#define SPRN_AMR 13 /* Authority Mask Register - problem state */
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2016-09-30 10:32:50 +08:00
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2020-06-04 20:56:08 +08:00
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#define set_amr(v) asm volatile("isync;" \
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"mtspr " __stringify(SPRN_AMR) ",%0;" \
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"isync" : \
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: "r" ((unsigned long)(v)) \
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: "memory")
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2016-09-30 10:32:50 +08:00
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/* TEXASR register bits */
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#define TEXASR_FC 0xFE00000000000000
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#define TEXASR_FP 0x0100000000000000
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#define TEXASR_DA 0x0080000000000000
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#define TEXASR_NO 0x0040000000000000
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#define TEXASR_FO 0x0020000000000000
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#define TEXASR_SIC 0x0010000000000000
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#define TEXASR_NTC 0x0008000000000000
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#define TEXASR_TC 0x0004000000000000
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#define TEXASR_TIC 0x0002000000000000
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#define TEXASR_IC 0x0001000000000000
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#define TEXASR_IFC 0x0000800000000000
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#define TEXASR_ABT 0x0000000100000000
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#define TEXASR_SPD 0x0000000080000000
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#define TEXASR_HV 0x0000000020000000
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#define TEXASR_PR 0x0000000010000000
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#define TEXASR_FS 0x0000000008000000
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#define TEXASR_TE 0x0000000004000000
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#define TEXASR_ROT 0x0000000002000000
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selftests/powerpc: New TM signal self test
A new self test that forces MSR[TS] to be set without calling any TM
instruction. This test also tries to cause a page fault at a signal
handler, exactly between MSR[TS] set and tm_recheckpoint(), forcing
thread->texasr to be rewritten with TEXASR[FS] = 0, which will cause a BUG
when tm_recheckpoint() is called.
This test is not deterministic, since it is hard to guarantee that the page
access will cause a page fault. In order to force more page faults at
signal context, the signal handler and the ucontext are being mapped into a
MADV_DONTNEED memory chunks.
Tests have shown that the bug could be exposed with few interactions in a
buggy kernel. This test is configured to loop 5000x, having a good chance
to hit the kernel issue in just one run. This self test takes less than
two seconds to run.
This test uses set/getcontext because the kernel will recheckpoint
zeroed structures, causing the test to segfault, which is undesired because
the test needs to rerun, so, there is a signal handler for SIGSEGV which
will restart the test.
v2: Uses the MADV_DONTNEED memory advice
v3: Fix memcpy and 32-bits compilation
v4: Does not define unused macros
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-08 19:31:21 +08:00
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/* MSR register bits */
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#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
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selftests/powerpc: Add a signal fuzzer selftest
This is a new selftest that raises SIGUSR1 signals and handles it in a
set of different ways, trying to create different scenario for testing
purpose.
This test works raising a signal and calling sigreturn interleaved
with TM operations, as starting, suspending and terminating a
transaction. The test depends on random numbers, and, based on them,
it sets different TM states.
Other than that, the test fills out the user context struct that is
passed to the sigreturn system call with random data, in order to make
sure that the signal handler syscall can handle different and invalid
states properly.
This selftest has command line parameters to control what kind of
tests the user wants to run, as for example, if a transaction should
be started prior to signal being raised, or, after the signal being
raised and before the sigreturn. If no parameter is given, the default
is enabling all options.
This test does not check if the user context is being read and set
properly by the kernel. Its purpose, at this time, is basically
guaranteeing that the kernel does not crash on invalid scenarios.
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-18 01:01:54 +08:00
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#define MSR_TS_T_LG 34 /* Trans Mem state: Active */
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selftests/powerpc: New TM signal self test
A new self test that forces MSR[TS] to be set without calling any TM
instruction. This test also tries to cause a page fault at a signal
handler, exactly between MSR[TS] set and tm_recheckpoint(), forcing
thread->texasr to be rewritten with TEXASR[FS] = 0, which will cause a BUG
when tm_recheckpoint() is called.
This test is not deterministic, since it is hard to guarantee that the page
access will cause a page fault. In order to force more page faults at
signal context, the signal handler and the ucontext are being mapped into a
MADV_DONTNEED memory chunks.
Tests have shown that the bug could be exposed with few interactions in a
buggy kernel. This test is configured to loop 5000x, having a good chance
to hit the kernel issue in just one run. This self test takes less than
two seconds to run.
This test uses set/getcontext because the kernel will recheckpoint
zeroed structures, causing the test to segfault, which is undesired because
the test needs to rerun, so, there is a signal handler for SIGSEGV which
will restart the test.
v2: Uses the MADV_DONTNEED memory advice
v3: Fix memcpy and 32-bits compilation
v4: Does not define unused macros
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-08 19:31:21 +08:00
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#define __MASK(X) (1UL<<(X))
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/* macro to check TM MSR bits */
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#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
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selftests/powerpc: Add a signal fuzzer selftest
This is a new selftest that raises SIGUSR1 signals and handles it in a
set of different ways, trying to create different scenario for testing
purpose.
This test works raising a signal and calling sigreturn interleaved
with TM operations, as starting, suspending and terminating a
transaction. The test depends on random numbers, and, based on them,
it sets different TM states.
Other than that, the test fills out the user context struct that is
passed to the sigreturn system call with random data, in order to make
sure that the signal handler syscall can handle different and invalid
states properly.
This selftest has command line parameters to control what kind of
tests the user wants to run, as for example, if a transaction should
be started prior to signal being raised, or, after the signal being
raised and before the sigreturn. If no parameter is given, the default
is enabling all options.
This test does not check if the user context is being read and set
properly by the kernel. Its purpose, at this time, is basically
guaranteeing that the kernel does not crash on invalid scenarios.
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-18 01:01:54 +08:00
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#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
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selftests/powerpc: New TM signal self test
A new self test that forces MSR[TS] to be set without calling any TM
instruction. This test also tries to cause a page fault at a signal
handler, exactly between MSR[TS] set and tm_recheckpoint(), forcing
thread->texasr to be rewritten with TEXASR[FS] = 0, which will cause a BUG
when tm_recheckpoint() is called.
This test is not deterministic, since it is hard to guarantee that the page
access will cause a page fault. In order to force more page faults at
signal context, the signal handler and the ucontext are being mapped into a
MADV_DONTNEED memory chunks.
Tests have shown that the bug could be exposed with few interactions in a
buggy kernel. This test is configured to loop 5000x, having a good chance
to hit the kernel issue in just one run. This self test takes less than
two seconds to run.
This test uses set/getcontext because the kernel will recheckpoint
zeroed structures, causing the test to segfault, which is undesired because
the test needs to rerun, so, there is a signal handler for SIGSEGV which
will restart the test.
v2: Uses the MADV_DONTNEED memory advice
v3: Fix memcpy and 32-bits compilation
v4: Does not define unused macros
Signed-off-by: Breno Leitao <leitao@debian.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-08 19:31:21 +08:00
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2016-09-30 10:32:50 +08:00
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/* Vector Instructions */
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#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
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((rb) << 11) | (((xs) >> 5)))
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#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
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#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
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2015-12-23 13:49:50 +08:00
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2016-09-30 10:32:52 +08:00
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#define ASM_LOAD_GPR_IMMED(_asm_symbol_name_immed) \
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"li 14, %[" #_asm_symbol_name_immed "];" \
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"li 15, %[" #_asm_symbol_name_immed "];" \
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"li 16, %[" #_asm_symbol_name_immed "];" \
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"li 17, %[" #_asm_symbol_name_immed "];" \
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"li 18, %[" #_asm_symbol_name_immed "];" \
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"li 19, %[" #_asm_symbol_name_immed "];" \
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"li 20, %[" #_asm_symbol_name_immed "];" \
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"li 21, %[" #_asm_symbol_name_immed "];" \
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"li 22, %[" #_asm_symbol_name_immed "];" \
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"li 23, %[" #_asm_symbol_name_immed "];" \
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"li 24, %[" #_asm_symbol_name_immed "];" \
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"li 25, %[" #_asm_symbol_name_immed "];" \
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"li 26, %[" #_asm_symbol_name_immed "];" \
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"li 27, %[" #_asm_symbol_name_immed "];" \
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"li 28, %[" #_asm_symbol_name_immed "];" \
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"li 29, %[" #_asm_symbol_name_immed "];" \
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"li 30, %[" #_asm_symbol_name_immed "];" \
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"li 31, %[" #_asm_symbol_name_immed "];"
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#define ASM_LOAD_FPR_SINGLE_PRECISION(_asm_symbol_name_addr) \
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"lfs 0, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 1, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 2, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 3, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 4, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 5, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 6, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 7, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 8, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 9, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 10, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 11, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 12, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 13, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 14, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 15, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 16, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 17, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 18, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 19, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 20, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 21, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 22, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 23, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 24, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 25, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 26, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 27, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 28, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 29, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 30, 0(%[" #_asm_symbol_name_addr "]);" \
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"lfs 31, 0(%[" #_asm_symbol_name_addr "]);"
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#ifndef __ASSEMBLER__
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void store_gpr(unsigned long *addr);
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void load_gpr(unsigned long *addr);
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void load_fpr_single_precision(float *addr);
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void store_fpr_single_precision(float *addr);
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#endif /* end of __ASSEMBLER__ */
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2014-06-10 20:23:10 +08:00
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#endif /* _SELFTESTS_POWERPC_REG_H */
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