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OpenCloudOS-Kernel/drivers/clk/ingenic/jz4725b-cgu.c

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clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
// SPDX-License-Identifier: GPL-2.0
/*
* Ingenic JZ4725B SoC CGU driver
*
* Copyright (C) 2018 Paul Cercueil
* Author: Paul Cercueil <paul@crapouillou.net>
*/
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/of.h>
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 11:15:44 +08:00
dt-bindings: Rename Ingenic CGU headers to ingenic,*.h Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
2021-10-16 21:33:21 +08:00
#include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 11:15:44 +08:00
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
#include "cgu.h"
clk: ingenic: Handle setting the Low-Power Mode bit The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-12 02:07:54 +08:00
#include "pm.h"
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
/* CGU register offsets */
#define CGU_REG_CPCCR 0x00
#define CGU_REG_LCR 0x04
#define CGU_REG_CPPCR 0x10
#define CGU_REG_CLKGR 0x20
#define CGU_REG_OPCR 0x24
#define CGU_REG_I2SCDR 0x60
#define CGU_REG_LPCDR 0x64
#define CGU_REG_MSCCDR 0x68
#define CGU_REG_SSICDR 0x74
#define CGU_REG_CIMCDR 0x78
/* bits within the LCR register */
#define LCR_SLEEP BIT(0)
static struct ingenic_cgu *cgu;
static const s8 pll_od_encoding[4] = {
0x0, 0x1, -1, 0x3,
};
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
static const u8 jz4725b_cgu_cpccr_div_table[] = {
1, 2, 3, 4, 6, 8,
};
clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:02 +08:00
static const u8 jz4725b_cgu_pll_half_div_table[] = {
2, 1,
};
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
/* External clocks */
[JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
[JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
[JZ4725B_CLK_PLL] = {
"pll", CGU_CLK_PLL,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.pll = {
.reg = CGU_REG_CPPCR,
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 11:15:44 +08:00
.rate_multiplier = 1,
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
.m_shift = 23,
.m_bits = 9,
.m_offset = 2,
.n_shift = 18,
.n_bits = 5,
.n_offset = 2,
.od_shift = 16,
.od_bits = 2,
.od_max = 4,
.od_encoding = pll_od_encoding,
.stable_bit = 10,
clk: Ingenic: Adjust cgu code to make it compatible with X1830. The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 11:15:44 +08:00
.bypass_reg = CGU_REG_CPPCR,
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
.bypass_bit = 9,
.enable_bit = 8,
},
},
/* Muxes & dividers */
[JZ4725B_CLK_PLL_HALF] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:02 +08:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31 00:49:19 +08:00
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly The code was setting the bit 21 of the CPCCR register to use a divider of 2 for the "pll half" clock, and clearing the bit to use a divider of 1. This is the opposite of how this register field works: a cleared bit means that the /2 divider is used, and a set bit means that the divider is 1. Restore the correct behaviour using the newly introduced .div_table field. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:02 +08:00
jz4725b_cgu_pll_half_div_table,
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
},
[JZ4725B_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31 00:49:19 +08:00
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
jz4725b_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
},
[JZ4725B_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31 00:49:19 +08:00
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
jz4725b_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
},
[JZ4725B_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31 00:49:19 +08:00
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
jz4725b_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
},
[JZ4725B_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31 00:49:19 +08:00
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
jz4725b_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
},
[JZ4725B_CLK_IPU] = {
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
.div = {
clk: Support bypassing dividers When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-05-31 00:49:19 +08:00
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks The main clocks (cclk, hclk, pclk, mclk, ipu) were using incorrect dividers, and thus reported an incorrect rate. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-05-03 05:25:01 +08:00
jz4725b_cgu_cpccr_div_table,
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
.gate = { CGU_REG_CLKGR, 13 },
},
[JZ4725B_CLK_LCD] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 9 },
},
[JZ4725B_CLK_I2S] = {
clk: jz4725b: fix mmc0 clock gating The mmc0 clock gate bit was mistakenly assigned to "i2s" clock. You can find that the same bit is assigned to "mmc0" too. It leads to mmc0 hang for a long time after any sound activity also it prevented PM_SLEEP to work properly. I guess it was introduced by copy-paste from jz4740 driver where it is really controls I2S clock gate. Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver") Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Tested-by: Siarhei Volkau <lis8215@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220205171849.687805-2-lis8215@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-02-06 01:18:49 +08:00
"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
.mux = { CGU_REG_CPCCR, 31, 1 },
.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
},
[JZ4725B_CLK_SPI] = {
"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
.mux = { CGU_REG_SSICDR, 31, 1 },
.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 4 },
},
[JZ4725B_CLK_MMC_MUX] = {
"mmc_mux", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
},
[JZ4725B_CLK_UDC] = {
"udc", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
.mux = { CGU_REG_CPCCR, 29, 1 },
.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
},
/* Gate-only clocks */
[JZ4725B_CLK_UART] = {
"uart", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 0 },
},
[JZ4725B_CLK_DMA] = {
"dma", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 12 },
},
[JZ4725B_CLK_ADC] = {
"adc", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 7 },
},
[JZ4725B_CLK_I2C] = {
"i2c", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 3 },
},
[JZ4725B_CLK_AIC] = {
"aic", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 5 },
},
[JZ4725B_CLK_MMC0] = {
"mmc0", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 6 },
},
[JZ4725B_CLK_MMC1] = {
"mmc1", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 16 },
},
[JZ4725B_CLK_BCH] = {
"bch", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 11 },
},
[JZ4725B_CLK_TCU] = {
"tcu", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 1 },
},
[JZ4725B_CLK_EXT512] = {
"ext/512", CGU_CLK_FIXDIV,
.parents = { JZ4725B_CLK_EXT },
/* Doc calls it EXT512, but it seems to be /256... */
.fixdiv = { 256 },
},
[JZ4725B_CLK_RTC] = {
"rtc", CGU_CLK_MUX,
.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
.mux = { CGU_REG_OPCR, 2, 1},
},
clk: ingenic: jz4725b: Add UDC PHY clock Add clock for the USB Device Controller PHY. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-03-19 22:05:36 +08:00
[JZ4725B_CLK_UDC_PHY] = {
"udc_phy", CGU_CLK_GATE,
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.gate = { CGU_REG_OPCR, 6, true },
},
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
};
static void __init jz4725b_cgu_init(struct device_node *np)
{
int retval;
cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
ARRAY_SIZE(jz4725b_cgu_clocks), np);
if (!cgu) {
pr_err("%s: failed to initialise CGU\n", __func__);
return;
}
retval = ingenic_cgu_register_clocks(cgu);
if (retval)
pr_err("%s: failed to register CGU Clocks\n", __func__);
clk: ingenic: Handle setting the Low-Power Mode bit The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-12 02:07:54 +08:00
ingenic_cgu_register_syscore_ops(cgu);
clk: Add Ingenic jz4725b CGU driver Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-08-23 21:17:44 +08:00
}
clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro By using CLK_OF_DECLARE_DRIVER instead of the CLK_OF_DECLARE macro, we allow the driver to probe also as a platform driver. While this driver does not have code to probe as a platform driver, this is still useful for probing children devices in the case where the device node is compatible with "simple-mfd". Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20190810123620.27238-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-10 20:36:20 +08:00
CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);