2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* S390 low-level entry points.
|
|
|
|
|
*
|
2012-07-20 17:15:04 +08:00
|
|
|
* Copyright IBM Corp. 1999, 2012
|
2005-04-17 06:20:36 +08:00
|
|
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
|
2006-09-28 22:56:37 +08:00
|
|
|
* Hartmut Penner (hp@de.ibm.com),
|
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|
* Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
|
2005-06-26 05:55:30 +08:00
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|
|
* Heiko Carstens <heiko.carstens@de.ibm.com>
|
2005-04-17 06:20:36 +08:00
|
|
|
*/
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|
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|
|
2008-02-05 23:50:40 +08:00
|
|
|
#include <linux/init.h>
|
2011-07-24 16:48:19 +08:00
|
|
|
#include <linux/linkage.h>
|
2012-09-05 19:26:11 +08:00
|
|
|
#include <asm/processor.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/cache.h>
|
|
|
|
|
#include <asm/errno.h>
|
|
|
|
|
#include <asm/ptrace.h>
|
|
|
|
|
#include <asm/thread_info.h>
|
2005-09-10 02:57:26 +08:00
|
|
|
#include <asm/asm-offsets.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
#include <asm/unistd.h>
|
|
|
|
|
#include <asm/page.h>
|
2012-06-04 21:05:43 +08:00
|
|
|
#include <asm/sigp.h>
|
2013-06-27 15:01:09 +08:00
|
|
|
#include <asm/irq.h>
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
#include <asm/vx-insn.h>
|
2015-10-01 23:02:48 +08:00
|
|
|
#include <asm/setup.h>
|
|
|
|
|
#include <asm/nmi.h>
|
2016-01-13 02:30:03 +08:00
|
|
|
#include <asm/export.h>
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-12-27 18:27:15 +08:00
|
|
|
__PT_R0 = __PT_GPRS
|
|
|
|
|
__PT_R1 = __PT_GPRS + 8
|
|
|
|
|
__PT_R2 = __PT_GPRS + 16
|
|
|
|
|
__PT_R3 = __PT_GPRS + 24
|
|
|
|
|
__PT_R4 = __PT_GPRS + 32
|
|
|
|
|
__PT_R5 = __PT_GPRS + 40
|
|
|
|
|
__PT_R6 = __PT_GPRS + 48
|
|
|
|
|
__PT_R7 = __PT_GPRS + 56
|
|
|
|
|
__PT_R8 = __PT_GPRS + 64
|
|
|
|
|
__PT_R9 = __PT_GPRS + 72
|
|
|
|
|
__PT_R10 = __PT_GPRS + 80
|
|
|
|
|
__PT_R11 = __PT_GPRS + 88
|
|
|
|
|
__PT_R12 = __PT_GPRS + 96
|
|
|
|
|
__PT_R13 = __PT_GPRS + 104
|
|
|
|
|
__PT_R14 = __PT_GPRS + 112
|
|
|
|
|
__PT_R15 = __PT_GPRS + 120
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2016-11-14 21:39:16 +08:00
|
|
|
STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
|
2005-04-17 06:20:36 +08:00
|
|
|
STACK_SIZE = 1 << STACK_SHIFT
|
2013-04-24 16:20:43 +08:00
|
|
|
STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2014-09-22 22:39:06 +08:00
|
|
|
_TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
|
2017-05-03 09:24:16 +08:00
|
|
|
_TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
|
2014-04-15 18:55:07 +08:00
|
|
|
_TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
|
|
|
|
|
_TIF_SYSCALL_TRACEPOINT)
|
2017-02-17 15:13:28 +08:00
|
|
|
_CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
|
|
|
|
|
_CIF_ASCE_SECONDARY | _CIF_FPU)
|
2017-06-07 20:10:24 +08:00
|
|
|
_PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
#define BASED(name) name-cleanup_critical(%r13)
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-07-03 15:24:46 +08:00
|
|
|
.macro TRACE_IRQS_ON
|
2011-12-27 18:27:15 +08:00
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
2010-05-17 16:00:02 +08:00
|
|
|
basr %r2,%r0
|
|
|
|
|
brasl %r14,trace_hardirqs_on_caller
|
2011-12-27 18:27:15 +08:00
|
|
|
#endif
|
2006-07-03 15:24:46 +08:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro TRACE_IRQS_OFF
|
2011-12-27 18:27:15 +08:00
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
2010-05-17 16:00:02 +08:00
|
|
|
basr %r2,%r0
|
|
|
|
|
brasl %r14,trace_hardirqs_off_caller
|
2007-11-20 18:13:32 +08:00
|
|
|
#endif
|
2011-12-27 18:27:15 +08:00
|
|
|
.endm
|
2007-11-20 18:13:32 +08:00
|
|
|
|
|
|
|
|
.macro LOCKDEP_SYS_EXIT
|
2011-12-27 18:27:15 +08:00
|
|
|
#ifdef CONFIG_LOCKDEP
|
|
|
|
|
tm __PT_PSW+1(%r11),0x01 # returning to user ?
|
|
|
|
|
jz .+10
|
2007-11-20 18:13:32 +08:00
|
|
|
brasl %r14,lockdep_sys_exit
|
2006-07-03 15:24:46 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
.endm
|
|
|
|
|
|
2011-12-27 18:27:15 +08:00
|
|
|
.macro CHECK_STACK stacksize,savearea
|
2006-06-29 20:58:05 +08:00
|
|
|
#ifdef CONFIG_CHECK_STACK
|
2011-12-27 18:27:15 +08:00
|
|
|
tml %r15,\stacksize - CONFIG_STACK_GUARD
|
|
|
|
|
lghi %r14,\savearea
|
|
|
|
|
jz stack_overflow
|
2006-06-29 20:58:05 +08:00
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-06-22 23:28:14 +08:00
|
|
|
.macro SWITCH_ASYNC savearea,timer
|
2011-12-27 18:27:15 +08:00
|
|
|
tmhh %r8,0x0001 # interrupting from user ?
|
|
|
|
|
jnz 1f
|
|
|
|
|
lgr %r14,%r9
|
|
|
|
|
slg %r14,BASED(.Lcritical_start)
|
|
|
|
|
clg %r14,BASED(.Lcritical_length)
|
2005-04-17 06:20:36 +08:00
|
|
|
jhe 0f
|
2011-12-27 18:27:15 +08:00
|
|
|
lghi %r11,\savearea # inside critical section, do cleanup
|
2005-04-17 06:20:36 +08:00
|
|
|
brasl %r14,cleanup_critical
|
2011-12-27 18:27:15 +08:00
|
|
|
tmhh %r8,0x0001 # retest problem state after cleanup
|
2005-04-17 06:20:36 +08:00
|
|
|
jnz 1f
|
2015-06-22 23:28:14 +08:00
|
|
|
0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack?
|
2005-04-17 06:20:36 +08:00
|
|
|
slgr %r14,%r15
|
2015-06-22 23:28:14 +08:00
|
|
|
srag %r14,%r14,STACK_SHIFT
|
2015-06-22 23:27:48 +08:00
|
|
|
jnz 2f
|
2015-06-22 23:28:14 +08:00
|
|
|
CHECK_STACK 1<<STACK_SHIFT,\savearea
|
2013-04-24 16:20:43 +08:00
|
|
|
aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
|
2015-06-22 23:27:48 +08:00
|
|
|
j 3f
|
2017-01-25 19:54:17 +08:00
|
|
|
1: UPDATE_VTIME %r14,%r15,\timer
|
2015-06-22 23:28:14 +08:00
|
|
|
2: lg %r15,__LC_ASYNC_STACK # load async stack
|
2015-06-22 23:27:48 +08:00
|
|
|
3: la %r11,STACK_FRAME_OVERHEAD(%r15)
|
2006-09-28 22:56:37 +08:00
|
|
|
.endm
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2015-06-22 23:27:48 +08:00
|
|
|
.macro UPDATE_VTIME w1,w2,enter_timer
|
|
|
|
|
lg \w1,__LC_EXIT_TIMER
|
|
|
|
|
lg \w2,__LC_LAST_UPDATE_TIMER
|
|
|
|
|
slg \w1,\enter_timer
|
|
|
|
|
slg \w2,__LC_EXIT_TIMER
|
|
|
|
|
alg \w1,__LC_USER_TIMER
|
|
|
|
|
alg \w2,__LC_SYSTEM_TIMER
|
|
|
|
|
stg \w1,__LC_USER_TIMER
|
|
|
|
|
stg \w2,__LC_SYSTEM_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
|
2005-04-17 06:20:36 +08:00
|
|
|
.endm
|
|
|
|
|
|
2010-10-25 22:10:37 +08:00
|
|
|
.macro REENABLE_IRQS
|
2011-12-27 18:27:15 +08:00
|
|
|
stg %r8,__LC_RETURN_PSW
|
|
|
|
|
ni __LC_RETURN_PSW,0xbf
|
|
|
|
|
ssm __LC_RETURN_PSW
|
2010-10-25 22:10:37 +08:00
|
|
|
.endm
|
|
|
|
|
|
2012-05-09 22:27:39 +08:00
|
|
|
.macro STCK savearea
|
2012-05-14 16:35:22 +08:00
|
|
|
#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
|
2012-05-09 22:27:39 +08:00
|
|
|
.insn s,0xb27c0000,\savearea # store clock fast
|
|
|
|
|
#else
|
|
|
|
|
.insn s,0xb2050000,\savearea # store clock
|
|
|
|
|
#endif
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-10-01 23:02:48 +08:00
|
|
|
/*
|
|
|
|
|
* The TSTMSK macro generates a test-under-mask instruction by
|
|
|
|
|
* calculating the memory offset for the specified mask value.
|
|
|
|
|
* Mask value can be any constant. The macro shifts the mask
|
|
|
|
|
* value to calculate the memory offset for the test-under-mask
|
|
|
|
|
* instruction.
|
|
|
|
|
*/
|
|
|
|
|
.macro TSTMSK addr, mask, size=8, bytepos=0
|
|
|
|
|
.if (\bytepos < \size) && (\mask >> 8)
|
|
|
|
|
.if (\mask & 0xff)
|
|
|
|
|
.error "Mask exceeds byte boundary"
|
|
|
|
|
.endif
|
|
|
|
|
TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
|
|
|
|
|
.exitm
|
|
|
|
|
.endif
|
|
|
|
|
.ifeq \mask
|
|
|
|
|
.error "Mask must not be zero"
|
|
|
|
|
.endif
|
|
|
|
|
off = \size - \bytepos - 1
|
|
|
|
|
tm off+\addr, \mask
|
|
|
|
|
.endm
|
|
|
|
|
|
2011-01-05 19:47:25 +08:00
|
|
|
.section .kprobes.text, "ax"
|
2016-06-30 18:40:25 +08:00
|
|
|
.Ldummy:
|
|
|
|
|
/*
|
|
|
|
|
* This nop exists only in order to avoid that __switch_to starts at
|
|
|
|
|
* the beginning of the kprobes text section. In that case we would
|
|
|
|
|
* have several symbols at the same address. E.g. objdump would take
|
|
|
|
|
* an arbitrary symbol name when disassembling this code.
|
|
|
|
|
* With the added nop in between the __switch_to symbol is unique
|
|
|
|
|
* again.
|
|
|
|
|
*/
|
|
|
|
|
nop 0
|
2011-01-05 19:47:25 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* Scheduler resume function, called by switch_to
|
|
|
|
|
* gpr2 = (task_struct *) prev
|
|
|
|
|
* gpr3 = (task_struct *) next
|
|
|
|
|
* Returns:
|
|
|
|
|
* gpr2 = prev
|
|
|
|
|
*/
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(__switch_to)
|
2012-05-15 15:20:06 +08:00
|
|
|
stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
|
2015-07-20 16:01:46 +08:00
|
|
|
lgr %r1,%r2
|
|
|
|
|
aghi %r1,__TASK_thread # thread_struct of prev task
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r5,__TASK_stack(%r3) # start of kernel stack of next
|
2015-07-20 16:01:46 +08:00
|
|
|
stg %r15,__THREAD_ksp(%r1) # store kernel stack of prev
|
|
|
|
|
lgr %r1,%r3
|
|
|
|
|
aghi %r1,__TASK_thread # thread_struct of next task
|
2012-05-15 15:20:06 +08:00
|
|
|
lgr %r15,%r5
|
2013-04-24 16:20:43 +08:00
|
|
|
aghi %r15,STACK_INIT # end of kernel stack of next
|
2012-05-15 15:20:06 +08:00
|
|
|
stg %r3,__LC_CURRENT # store task struct of next
|
|
|
|
|
stg %r15,__LC_KERNEL_STACK # store end of kernel stack
|
2015-07-20 16:01:46 +08:00
|
|
|
lg %r15,__THREAD_ksp(%r1) # load kernel stack of next
|
2015-10-07 00:06:15 +08:00
|
|
|
mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
|
2014-04-15 18:55:07 +08:00
|
|
|
lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
|
2015-10-07 00:06:15 +08:00
|
|
|
TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
|
|
|
|
|
bzr %r14
|
|
|
|
|
.insn s,0xb2800000,__LC_LPP # set program parameter
|
2005-04-17 06:20:36 +08:00
|
|
|
br %r14
|
|
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.L__critical_start:
|
2015-06-22 23:26:40 +08:00
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_KVM)
|
|
|
|
|
/*
|
|
|
|
|
* sie64a calling convention:
|
|
|
|
|
* %r2 pointer to sie control block
|
|
|
|
|
* %r3 guest register save area
|
|
|
|
|
*/
|
|
|
|
|
ENTRY(sie64a)
|
|
|
|
|
stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
|
|
|
|
|
stg %r2,__SF_EMPTY(%r15) # save control block pointer
|
|
|
|
|
stg %r3,__SF_EMPTY+8(%r15) # save guest register save area
|
2015-10-07 00:06:15 +08:00
|
|
|
xc __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
|
2015-06-22 23:26:40 +08:00
|
|
|
jno .Lsie_load_guest_gprs
|
|
|
|
|
brasl %r14,load_fpu_regs # load guest fp/vx regs
|
|
|
|
|
.Lsie_load_guest_gprs:
|
|
|
|
|
lmg %r0,%r13,0(%r3) # load guest gprs 0-13
|
|
|
|
|
lg %r14,__LC_GMAP # get gmap pointer
|
|
|
|
|
ltgr %r14,%r14
|
|
|
|
|
jz .Lsie_gmap
|
|
|
|
|
lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
|
|
|
|
|
.Lsie_gmap:
|
|
|
|
|
lg %r14,__SF_EMPTY(%r15) # get control block pointer
|
|
|
|
|
oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
|
|
|
|
|
tm __SIE_PROG20+3(%r14),3 # last exit...
|
|
|
|
|
jnz .Lsie_skip
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_FPU
|
2015-06-22 23:26:40 +08:00
|
|
|
jo .Lsie_skip # exit if fp/vx regs changed
|
2017-06-07 17:30:42 +08:00
|
|
|
.Lsie_entry:
|
2015-06-22 23:26:40 +08:00
|
|
|
sie 0(%r14)
|
|
|
|
|
.Lsie_skip:
|
|
|
|
|
ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
|
|
|
|
|
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
|
|
|
|
|
.Lsie_done:
|
|
|
|
|
# some program checks are suppressing. C code (e.g. do_protection_exception)
|
2017-05-15 20:11:03 +08:00
|
|
|
# will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
|
|
|
|
|
# are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
|
|
|
|
|
# Other instructions between sie64a and .Lsie_done should not cause program
|
|
|
|
|
# interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
|
2015-06-22 23:26:40 +08:00
|
|
|
# See also .Lcleanup_sie
|
2017-05-15 20:11:03 +08:00
|
|
|
.Lrewind_pad6:
|
|
|
|
|
nopr 7
|
|
|
|
|
.Lrewind_pad4:
|
|
|
|
|
nopr 7
|
|
|
|
|
.Lrewind_pad2:
|
|
|
|
|
nopr 7
|
2015-06-22 23:26:40 +08:00
|
|
|
.globl sie_exit
|
|
|
|
|
sie_exit:
|
|
|
|
|
lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
|
|
|
|
|
stmg %r0,%r13,0(%r14) # save guest gprs 0-13
|
|
|
|
|
lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
|
2015-10-07 00:06:15 +08:00
|
|
|
lg %r2,__SF_EMPTY+16(%r15) # return exit reason code
|
2015-06-22 23:26:40 +08:00
|
|
|
br %r14
|
|
|
|
|
.Lsie_fault:
|
|
|
|
|
lghi %r14,-EFAULT
|
2015-10-07 00:06:15 +08:00
|
|
|
stg %r14,__SF_EMPTY+16(%r15) # set exit reason code
|
2015-06-22 23:26:40 +08:00
|
|
|
j sie_exit
|
|
|
|
|
|
2017-05-15 20:11:03 +08:00
|
|
|
EX_TABLE(.Lrewind_pad6,.Lsie_fault)
|
|
|
|
|
EX_TABLE(.Lrewind_pad4,.Lsie_fault)
|
|
|
|
|
EX_TABLE(.Lrewind_pad2,.Lsie_fault)
|
2015-06-22 23:26:40 +08:00
|
|
|
EX_TABLE(sie_exit,.Lsie_fault)
|
2016-01-13 02:30:03 +08:00
|
|
|
EXPORT_SYMBOL(sie64a)
|
|
|
|
|
EXPORT_SYMBOL(sie_exit)
|
2015-06-22 23:26:40 +08:00
|
|
|
#endif
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* SVC interrupt handler routine. System calls are synchronous events and
|
|
|
|
|
* are executed with interrupts enabled.
|
|
|
|
|
*/
|
|
|
|
|
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(system_call)
|
2008-12-25 20:39:25 +08:00
|
|
|
stpt __LC_SYNC_ENTER_TIMER
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_stmg:
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r8,%r15,__LC_SAVE_AREA_SYNC
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r12,__LC_CURRENT
|
2017-01-25 19:54:17 +08:00
|
|
|
lghi %r13,__TASK_thread
|
2014-04-15 18:55:07 +08:00
|
|
|
lghi %r14,_PIF_SYSCALL
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_per:
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r15,__LC_KERNEL_STACK
|
|
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
|
2015-06-22 23:27:48 +08:00
|
|
|
.Lsysc_vtime:
|
2017-01-25 19:54:17 +08:00
|
|
|
UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
|
|
|
mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
|
|
|
|
|
mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
|
2011-12-27 18:27:18 +08:00
|
|
|
mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
|
2014-04-15 18:55:07 +08:00
|
|
|
stg %r14,__PT_FLAGS(%r11)
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_do_svc:
|
2016-11-08 19:33:38 +08:00
|
|
|
# load address of system call table
|
|
|
|
|
lg %r10,__THREAD_sysc_table(%r13,%r12)
|
2011-12-27 18:27:18 +08:00
|
|
|
llgh %r8,__PT_INT_CODE+2(%r11)
|
2011-12-27 18:27:15 +08:00
|
|
|
slag %r8,%r8,2 # shift and test for svc 0
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lsysc_nr_ok
|
2005-04-17 06:20:36 +08:00
|
|
|
# svc 0: system call number in %r1
|
2011-12-27 18:27:15 +08:00
|
|
|
llgfr %r1,%r1 # clear high word in r1
|
2010-05-17 16:00:05 +08:00
|
|
|
cghi %r1,NR_syscalls
|
2014-12-04 00:00:08 +08:00
|
|
|
jnl .Lsysc_nr_ok
|
2011-12-27 18:27:18 +08:00
|
|
|
sth %r1,__PT_INT_CODE+2(%r11)
|
2011-12-27 18:27:15 +08:00
|
|
|
slag %r8,%r1,2
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_nr_ok:
|
2011-12-27 18:27:15 +08:00
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
|
|
|
stg %r2,__PT_ORIG_GPR2(%r11)
|
|
|
|
|
stg %r7,STACK_FRAME_OVERHEAD(%r15)
|
|
|
|
|
lgf %r9,0(%r8,%r10) # get system call add.
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_TRACE
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lsysc_tracesys
|
2011-12-27 18:27:15 +08:00
|
|
|
basr %r14,%r9 # call sys_xxxx
|
|
|
|
|
stg %r2,__PT_R2(%r11) # store return value
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_return:
|
2010-05-17 16:00:02 +08:00
|
|
|
LOCKDEP_SYS_EXIT
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_tif:
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __PT_FLAGS(%r11),_PIF_WORK
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lsysc_work
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_WORK
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lsysc_work # check for work
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_WORK
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lsysc_work
|
|
|
|
|
.Lsysc_restore:
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r14,__LC_VDSO_PER_CPU
|
|
|
|
|
lmg %r0,%r10,__PT_R0(%r11)
|
|
|
|
|
mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
|
2017-05-02 19:36:00 +08:00
|
|
|
.Lsysc_exit_timer:
|
2011-12-27 18:27:15 +08:00
|
|
|
stpt __LC_EXIT_TIMER
|
|
|
|
|
mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
|
|
|
|
|
lmg %r11,%r15,__PT_R11(%r11)
|
|
|
|
|
lpswe __LC_RETURN_PSW
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_done:
|
2007-11-20 18:13:32 +08:00
|
|
|
|
2010-05-17 16:00:01 +08:00
|
|
|
#
|
|
|
|
|
# One of the work bits is on. Find out which one.
|
|
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_work:
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lsysc_mcck_pending
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lsysc_reschedule
|
2017-06-07 20:10:24 +08:00
|
|
|
TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
|
|
|
|
|
jo .Lsysc_syscall_restart
|
2014-09-22 22:39:06 +08:00
|
|
|
#ifdef CONFIG_UPROBES
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_UPROBE
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lsysc_uprobe_notify
|
2014-09-22 22:39:06 +08:00
|
|
|
#endif
|
2016-01-26 21:10:34 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
|
|
|
|
|
jo .Lsysc_guarded_storage
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lsysc_singlestep
|
2017-02-14 09:42:34 +08:00
|
|
|
#ifdef CONFIG_LIVEPATCH
|
|
|
|
|
TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
|
|
|
|
|
jo .Lsysc_patch_pending # handle live patching just before
|
|
|
|
|
# signals and possible syscall restart
|
|
|
|
|
#endif
|
2017-06-07 20:10:24 +08:00
|
|
|
TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
|
|
|
|
|
jo .Lsysc_syscall_restart
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lsysc_sigpending
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lsysc_notify_resume
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_FPU
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
jo .Lsysc_vxrs
|
2017-02-17 15:13:28 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
|
|
|
|
|
jnz .Lsysc_asce
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lsysc_return # beware of critical section cleanup
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# _TIF_NEED_RESCHED is set, call schedule
|
2006-09-28 22:56:37 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_reschedule:
|
|
|
|
|
larl %r14,.Lsysc_return
|
2011-12-27 18:27:15 +08:00
|
|
|
jg schedule
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-06-26 05:55:30 +08:00
|
|
|
#
|
2014-04-15 18:55:07 +08:00
|
|
|
# _CIF_MCCK_PENDING is set, call handler
|
2005-06-26 05:55:30 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_mcck_pending:
|
|
|
|
|
larl %r14,.Lsysc_return
|
2006-09-28 22:56:37 +08:00
|
|
|
jg s390_handle_mcck # TIF bit will be cleared by handler
|
2005-06-26 05:55:30 +08:00
|
|
|
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
#
|
2017-02-17 15:13:28 +08:00
|
|
|
# _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
#
|
2017-02-17 15:13:28 +08:00
|
|
|
.Lsysc_asce:
|
2017-02-17 15:12:30 +08:00
|
|
|
ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
|
2017-02-17 15:13:28 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_SECONDARY
|
|
|
|
|
jz .Lsysc_return
|
|
|
|
|
larl %r14,.Lsysc_return
|
|
|
|
|
jg set_fs_fixup
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
#
|
|
|
|
|
# CIF_FPU is set, restore floating-point controls and floating-point registers.
|
|
|
|
|
#
|
|
|
|
|
.Lsysc_vxrs:
|
|
|
|
|
larl %r14,.Lsysc_return
|
|
|
|
|
jg load_fpu_regs
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2008-04-30 15:53:08 +08:00
|
|
|
# _TIF_SIGPENDING is set, call do_signal
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_sigpending:
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
|
|
|
brasl %r14,do_signal
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
|
2014-12-04 00:00:08 +08:00
|
|
|
jno .Lsysc_return
|
2016-03-22 17:54:24 +08:00
|
|
|
.Lsysc_do_syscall:
|
|
|
|
|
lghi %r13,__TASK_thread
|
2011-12-27 18:27:15 +08:00
|
|
|
lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
|
2016-03-22 17:54:24 +08:00
|
|
|
lghi %r1,0 # svc 0 returns -ENOSYS
|
|
|
|
|
j .Lsysc_do_svc
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-10-11 03:33:20 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_NOTIFY_RESUME is set, call do_notify_resume
|
|
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_notify_resume:
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r14,.Lsysc_return
|
2011-12-27 18:27:15 +08:00
|
|
|
jg do_notify_resume
|
2008-10-11 03:33:20 +08:00
|
|
|
|
2014-09-22 22:39:06 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_UPROBE is set, call uprobe_notify_resume
|
|
|
|
|
#
|
|
|
|
|
#ifdef CONFIG_UPROBES
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_uprobe_notify:
|
2014-09-22 22:39:06 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r14,.Lsysc_return
|
2014-09-22 22:39:06 +08:00
|
|
|
jg uprobe_notify_resume
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-01-26 21:10:34 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
|
|
|
|
|
#
|
|
|
|
|
.Lsysc_guarded_storage:
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
|
|
|
larl %r14,.Lsysc_return
|
|
|
|
|
jg gs_load_bc_cb
|
2017-02-14 09:42:34 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_PATCH_PENDING is set, call klp_update_patch_state
|
|
|
|
|
#
|
|
|
|
|
#ifdef CONFIG_LIVEPATCH
|
|
|
|
|
.Lsysc_patch_pending:
|
|
|
|
|
lg %r2,__LC_CURRENT # pass pointer to task struct
|
|
|
|
|
larl %r14,.Lsysc_return
|
|
|
|
|
jg klp_update_patch_state
|
|
|
|
|
#endif
|
2016-01-26 21:10:34 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2014-04-15 18:55:07 +08:00
|
|
|
# _PIF_PER_TRAP is set, call do_per_trap
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_singlestep:
|
2014-04-15 18:55:07 +08:00
|
|
|
ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r14,.Lsysc_return
|
2011-01-05 19:48:10 +08:00
|
|
|
jg do_per_trap
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2017-06-07 20:10:24 +08:00
|
|
|
#
|
|
|
|
|
# _PIF_SYSCALL_RESTART is set, repeat the current system call
|
|
|
|
|
#
|
|
|
|
|
.Lsysc_syscall_restart:
|
|
|
|
|
ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
|
|
|
|
|
lmg %r1,%r7,__PT_R1(%r11) # load svc arguments
|
|
|
|
|
lg %r2,__PT_ORIG_GPR2(%r11)
|
|
|
|
|
j .Lsysc_do_svc
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2008-10-11 03:33:20 +08:00
|
|
|
# call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
|
|
|
|
|
# and after the system call
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_tracesys:
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2005-04-17 06:20:36 +08:00
|
|
|
la %r3,0
|
2011-12-27 18:27:18 +08:00
|
|
|
llgh %r0,__PT_INT_CODE+2(%r11)
|
2011-12-27 18:27:15 +08:00
|
|
|
stg %r0,__PT_R2(%r11)
|
2008-10-11 03:33:20 +08:00
|
|
|
brasl %r14,do_syscall_trace_enter
|
2005-04-17 06:20:36 +08:00
|
|
|
lghi %r0,NR_syscalls
|
2008-10-11 03:33:20 +08:00
|
|
|
clgr %r0,%r2
|
2014-12-04 00:00:08 +08:00
|
|
|
jnh .Lsysc_tracenogo
|
2011-12-27 18:27:15 +08:00
|
|
|
sllg %r8,%r2,2
|
|
|
|
|
lgf %r9,0(%r8,%r10)
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_tracego:
|
2011-12-27 18:27:15 +08:00
|
|
|
lmg %r3,%r7,__PT_R3(%r11)
|
|
|
|
|
stg %r7,STACK_FRAME_OVERHEAD(%r15)
|
|
|
|
|
lg %r2,__PT_ORIG_GPR2(%r11)
|
|
|
|
|
basr %r14,%r9 # call sys_xxx
|
|
|
|
|
stg %r2,__PT_R2(%r11) # store return value
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lsysc_tracenogo:
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_TRACE
|
2014-12-04 00:00:08 +08:00
|
|
|
jz .Lsysc_return
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r14,.Lsysc_return
|
2008-10-11 03:33:20 +08:00
|
|
|
jg do_syscall_trace_exit
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# a new process exits the kernel with ret_from_fork
|
|
|
|
|
#
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(ret_from_fork)
|
2011-12-27 18:27:15 +08:00
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15)
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r12,__LC_CURRENT
|
2012-09-11 06:03:41 +08:00
|
|
|
brasl %r14,schedule_tail
|
|
|
|
|
TRACE_IRQS_ON
|
|
|
|
|
ssm __LC_SVC_NEW_PSW # reenable interrupts
|
2012-10-12 03:30:14 +08:00
|
|
|
tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
|
2014-12-04 00:00:08 +08:00
|
|
|
jne .Lsysc_tracenogo
|
2012-10-12 03:30:14 +08:00
|
|
|
# it's a kernel thread
|
|
|
|
|
lmg %r9,%r10,__PT_R9(%r11) # load gprs
|
2012-09-11 06:03:41 +08:00
|
|
|
ENTRY(kernel_thread_starter)
|
|
|
|
|
la %r2,0(%r10)
|
|
|
|
|
basr %r14,%r9
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lsysc_tracenogo
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Program check handler routine
|
|
|
|
|
*/
|
|
|
|
|
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(pgm_check_handler)
|
2008-12-25 20:39:25 +08:00
|
|
|
stpt __LC_SYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r8,%r15,__LC_SAVE_AREA_SYNC
|
|
|
|
|
lg %r10,__LC_LAST_BREAK
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r12,__LC_CURRENT
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
larl %r13,cleanup_critical
|
2011-12-27 18:27:15 +08:00
|
|
|
lmg %r8,%r9,__LC_PGM_OLD_PSW
|
|
|
|
|
tmhh %r8,0x0001 # test problem state bit
|
2015-06-22 23:26:40 +08:00
|
|
|
jnz 2f # -> fault in user space
|
|
|
|
|
#if IS_ENABLED(CONFIG_KVM)
|
|
|
|
|
# cleanup critical section for sie64a
|
|
|
|
|
lgr %r14,%r9
|
|
|
|
|
slg %r14,BASED(.Lsie_critical_start)
|
|
|
|
|
clg %r14,BASED(.Lsie_critical_length)
|
|
|
|
|
jhe 0f
|
|
|
|
|
brasl %r14,.Lcleanup_sie
|
|
|
|
|
#endif
|
|
|
|
|
0: tmhh %r8,0x4000 # PER bit set in old PSW ?
|
|
|
|
|
jnz 1f # -> enabled, can't be a double fault
|
2011-12-27 18:27:15 +08:00
|
|
|
tm __LC_PGM_ILC+3,0x80 # check for per exception
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lpgm_svcper # -> single stepped svc
|
2015-06-22 23:26:40 +08:00
|
|
|
1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
|
2013-04-24 16:20:43 +08:00
|
|
|
aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
|
2017-02-28 14:42:01 +08:00
|
|
|
j 4f
|
2017-01-25 19:54:17 +08:00
|
|
|
2: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r15,__LC_KERNEL_STACK
|
2016-11-08 18:08:26 +08:00
|
|
|
lgr %r14,%r12
|
2015-07-20 16:01:46 +08:00
|
|
|
aghi %r14,__TASK_thread # pointer to thread_struct
|
2012-07-31 17:03:04 +08:00
|
|
|
lghi %r13,__LC_PGM_TDB
|
|
|
|
|
tm __LC_PGM_ILC+2,0x02 # check for transaction abort
|
2015-06-22 23:26:40 +08:00
|
|
|
jz 3f
|
2012-07-31 17:03:04 +08:00
|
|
|
mvc __THREAD_trap_tdb(256,%r14),0(%r13)
|
2017-02-28 14:42:01 +08:00
|
|
|
3: stg %r10,__THREAD_last_break(%r14)
|
|
|
|
|
4: la %r11,STACK_FRAME_OVERHEAD(%r15)
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
|
|
|
mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
|
|
|
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
2011-12-27 18:27:18 +08:00
|
|
|
mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
|
|
|
|
|
mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
|
2014-04-15 18:55:07 +08:00
|
|
|
xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
|
2011-12-27 18:27:15 +08:00
|
|
|
stg %r10,__PT_ARGS(%r11)
|
|
|
|
|
tm __LC_PGM_ILC+3,0x80 # check for per exception
|
2017-02-28 14:42:01 +08:00
|
|
|
jz 5f
|
2011-12-27 18:27:15 +08:00
|
|
|
tmhh %r8,0x0001 # kernel per event ?
|
2014-12-04 00:00:08 +08:00
|
|
|
jz .Lpgm_kprobe
|
2014-04-15 18:55:07 +08:00
|
|
|
oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
|
2012-07-31 17:03:04 +08:00
|
|
|
mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
|
2014-02-26 23:32:46 +08:00
|
|
|
mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
|
|
|
|
|
mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
|
2017-02-28 14:42:01 +08:00
|
|
|
5: REENABLE_IRQS
|
2011-12-27 18:27:15 +08:00
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
2010-07-28 01:29:37 +08:00
|
|
|
larl %r1,pgm_check_table
|
2011-12-27 18:27:18 +08:00
|
|
|
llgh %r10,__PT_INT_CODE+2(%r11)
|
|
|
|
|
nill %r10,0x007f
|
2012-10-19 00:10:06 +08:00
|
|
|
sll %r10,2
|
2015-06-22 23:27:48 +08:00
|
|
|
je .Lpgm_return
|
2012-10-19 00:10:06 +08:00
|
|
|
lgf %r1,0(%r10,%r1) # load address of handler routine
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2010-07-28 01:29:37 +08:00
|
|
|
basr %r14,%r1 # branch to interrupt-handler
|
2015-06-22 23:27:48 +08:00
|
|
|
.Lpgm_return:
|
|
|
|
|
LOCKDEP_SYS_EXIT
|
|
|
|
|
tm __PT_PSW+1(%r11),0x01 # returning to user ?
|
|
|
|
|
jno .Lsysc_restore
|
2016-03-22 17:54:24 +08:00
|
|
|
TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
|
|
|
|
|
jo .Lsysc_do_syscall
|
2015-06-22 23:27:48 +08:00
|
|
|
j .Lsysc_tif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
|
#
|
2011-12-27 18:27:15 +08:00
|
|
|
# PER event in supervisor state, must be kprobes
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lpgm_kprobe:
|
2011-12-27 18:27:15 +08:00
|
|
|
REENABLE_IRQS
|
|
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
|
|
|
brasl %r14,do_per_trap
|
2015-06-22 23:27:48 +08:00
|
|
|
j .Lpgm_return
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-09-20 21:58:39 +08:00
|
|
|
#
|
2011-12-27 18:27:15 +08:00
|
|
|
# single stepped system call
|
2006-09-20 21:58:39 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lpgm_svcper:
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
|
2017-02-20 16:51:36 +08:00
|
|
|
lghi %r13,__TASK_thread
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r14,.Lsysc_per
|
2011-12-27 18:27:15 +08:00
|
|
|
stg %r14,__LC_RETURN_PSW+8
|
2014-04-15 18:55:07 +08:00
|
|
|
lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
|
2014-12-04 00:00:08 +08:00
|
|
|
lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
|
2006-09-20 21:58:39 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* IO interrupt handler routine
|
|
|
|
|
*/
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(io_int_handler)
|
2012-05-09 22:27:39 +08:00
|
|
|
STCK __LC_INT_CLOCK
|
2008-12-31 22:11:41 +08:00
|
|
|
stpt __LC_ASYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r12,__LC_CURRENT
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
larl %r13,cleanup_critical
|
2011-12-27 18:27:15 +08:00
|
|
|
lmg %r8,%r9,__LC_IO_OLD_PSW
|
2015-06-22 23:28:14 +08:00
|
|
|
SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
|
|
|
mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
|
|
|
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
2013-06-17 20:54:02 +08:00
|
|
|
mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
|
2014-04-15 18:55:07 +08:00
|
|
|
xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
|
2015-08-15 17:42:21 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
|
|
|
|
|
jo .Lio_restore
|
2006-07-03 15:24:46 +08:00
|
|
|
TRACE_IRQS_OFF
|
2011-12-27 18:27:15 +08:00
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_loop:
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2013-06-27 15:01:09 +08:00
|
|
|
lghi %r3,IO_INTERRUPT
|
|
|
|
|
tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
|
2014-12-04 00:00:08 +08:00
|
|
|
jz .Lio_call
|
2013-06-27 15:01:09 +08:00
|
|
|
lghi %r3,THIN_INTERRUPT
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_call:
|
2011-12-27 18:27:15 +08:00
|
|
|
brasl %r14,do_IRQ
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
|
2014-12-04 00:00:08 +08:00
|
|
|
jz .Lio_return
|
2013-06-17 20:54:02 +08:00
|
|
|
tpi 0
|
2014-12-04 00:00:08 +08:00
|
|
|
jz .Lio_return
|
2013-06-17 20:54:02 +08:00
|
|
|
mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_loop
|
|
|
|
|
.Lio_return:
|
2010-05-17 16:00:02 +08:00
|
|
|
LOCKDEP_SYS_EXIT
|
|
|
|
|
TRACE_IRQS_ON
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_tif:
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_WORK
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lio_work # there is work to do (signals etc.)
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_WORK
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lio_work
|
|
|
|
|
.Lio_restore:
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r14,__LC_VDSO_PER_CPU
|
|
|
|
|
lmg %r0,%r10,__PT_R0(%r11)
|
|
|
|
|
mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
|
2017-05-02 19:36:00 +08:00
|
|
|
.Lio_exit_timer:
|
2011-12-27 18:27:15 +08:00
|
|
|
stpt __LC_EXIT_TIMER
|
|
|
|
|
mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
|
|
|
|
|
lmg %r11,%r15,__PT_R11(%r11)
|
|
|
|
|
lpswe __LC_RETURN_PSW
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_done:
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-05-07 15:22:52 +08:00
|
|
|
#
|
2010-05-17 16:00:01 +08:00
|
|
|
# There is work todo, find out in which context we have been interrupted:
|
2014-04-15 18:55:07 +08:00
|
|
|
# 1) if we return to user space we can do all _TIF_WORK work
|
2010-05-17 16:00:01 +08:00
|
|
|
# 2) if we return to kernel code and kvm is enabled check if we need to
|
|
|
|
|
# modify the psw to leave SIE
|
|
|
|
|
# 3) if we return to kernel code and preemptive scheduling is enabled check
|
|
|
|
|
# the preemption counter and if it is zero call preempt_schedule_irq
|
|
|
|
|
# Before any work can be done, a switch to the kernel stack is required.
|
2008-05-07 15:22:52 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_work:
|
2011-12-27 18:27:15 +08:00
|
|
|
tm __PT_PSW+1(%r11),0x01 # returning to user ?
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lio_work_user # yes -> do resched & signal
|
2010-05-17 16:00:01 +08:00
|
|
|
#ifdef CONFIG_PREEMPT
|
2008-05-07 15:22:52 +08:00
|
|
|
# check for preemptive scheduling
|
2016-10-25 18:21:44 +08:00
|
|
|
icm %r0,15,__LC_PREEMPT_COUNT
|
2014-12-04 00:00:08 +08:00
|
|
|
jnz .Lio_restore # preemption is disabled
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
|
2014-12-04 00:00:08 +08:00
|
|
|
jno .Lio_restore
|
2005-04-17 06:20:36 +08:00
|
|
|
# switch to kernel stack
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r1,__PT_R15(%r11)
|
|
|
|
|
aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
|
|
|
|
|
mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
|
|
|
|
|
xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
|
|
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r1)
|
2005-04-17 06:20:36 +08:00
|
|
|
lgr %r15,%r1
|
2014-12-04 00:00:08 +08:00
|
|
|
# TRACE_IRQS_ON already done at .Lio_return, call
|
2010-05-17 16:00:02 +08:00
|
|
|
# TRACE_IRQS_OFF to keep things symmetrical
|
|
|
|
|
TRACE_IRQS_OFF
|
|
|
|
|
brasl %r14,preempt_schedule_irq
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return
|
2010-05-17 16:00:02 +08:00
|
|
|
#else
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_restore
|
2010-05-17 16:00:02 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2010-05-17 16:00:01 +08:00
|
|
|
#
|
|
|
|
|
# Need to do work before returning to userspace, switch to kernel stack
|
|
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_work_user:
|
2005-04-17 06:20:36 +08:00
|
|
|
lg %r1,__LC_KERNEL_STACK
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
|
|
|
|
|
xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
|
|
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r1)
|
2005-04-17 06:20:36 +08:00
|
|
|
lgr %r15,%r1
|
2010-05-17 16:00:01 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
|
|
|
|
# One of the work bits is on. Find out which one.
|
|
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_work_tif:
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lio_mcck_pending
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lio_reschedule
|
2017-02-14 09:42:34 +08:00
|
|
|
#ifdef CONFIG_LIVEPATCH
|
|
|
|
|
TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
|
|
|
|
|
jo .Lio_patch_pending
|
|
|
|
|
#endif
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lio_sigpending
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lio_notify_resume
|
2016-01-26 21:10:34 +08:00
|
|
|
TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
|
|
|
|
|
jo .Lio_guarded_storage
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_FPU
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
jo .Lio_vxrs
|
2017-02-17 15:13:28 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
|
|
|
|
|
jnz .Lio_asce
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return # beware of critical section cleanup
|
2008-05-07 15:22:53 +08:00
|
|
|
|
2005-06-26 05:55:30 +08:00
|
|
|
#
|
2014-04-15 18:55:07 +08:00
|
|
|
# _CIF_MCCK_PENDING is set, call handler
|
2005-06-26 05:55:30 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_mcck_pending:
|
|
|
|
|
# TRACE_IRQS_ON already done at .Lio_return
|
2007-07-27 18:29:18 +08:00
|
|
|
brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
|
2010-05-17 16:00:02 +08:00
|
|
|
TRACE_IRQS_OFF
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return
|
2005-06-26 05:55:30 +08:00
|
|
|
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
#
|
2017-02-17 15:13:28 +08:00
|
|
|
# _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
#
|
2017-02-17 15:13:28 +08:00
|
|
|
.Lio_asce:
|
2017-02-17 15:12:30 +08:00
|
|
|
ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
|
2017-02-17 15:13:28 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_SECONDARY
|
|
|
|
|
jz .Lio_return
|
|
|
|
|
larl %r14,.Lio_return
|
|
|
|
|
jg set_fs_fixup
|
s390/uaccess: rework uaccess code - fix locking issues
The current uaccess code uses a page table walk in some circumstances,
e.g. in case of the in atomic futex operations or if running on old
hardware which doesn't support the mvcos instruction.
However it turned out that the page table walk code does not correctly
lock page tables when accessing page table entries.
In other words: a different cpu may invalidate a page table entry while
the current cpu inspects the pte. This may lead to random data corruption.
Adding correct locking however isn't trivial for all uaccess operations.
Especially copy_in_user() is problematic since that requires to hold at
least two locks, but must be protected against ABBA deadlock when a
different cpu also performs a copy_in_user() operation.
So the solution is a different approach where we change address spaces:
User space runs in primary address mode, or access register mode within
vdso code, like it currently already does.
The kernel usually also runs in home space mode, however when accessing
user space the kernel switches to primary or secondary address mode if
the mvcos instruction is not available or if a compare-and-swap (futex)
instruction on a user space address is performed.
KVM however is special, since that requires the kernel to run in home
address space while implicitly accessing user space with the sie
instruction.
So we end up with:
User space:
- runs in primary or access register mode
- cr1 contains the user asce
- cr7 contains the user asce
- cr13 contains the kernel asce
Kernel space:
- runs in home space mode
- cr1 contains the user or kernel asce
-> the kernel asce is loaded when a uaccess requires primary or
secondary address mode
- cr7 contains the user or kernel asce, (changed with set_fs())
- cr13 contains the kernel asce
In case of uaccess the kernel changes to:
- primary space mode in case of a uaccess (copy_to_user) and uses
e.g. the mvcp instruction to access user space. However the kernel
will stay in home space mode if the mvcos instruction is available
- secondary space mode in case of futex atomic operations, so that the
instructions come from primary address space and data from secondary
space
In case of kvm the kernel runs in home space mode, but cr1 gets switched
to contain the gmap asce before the sie instruction gets executed. When
the sie instruction is finished cr1 will be switched back to contain the
user asce.
A context switch between two processes will always load the kernel asce
for the next process in cr1. So the first exit to user space is a bit
more expensive (one extra load control register instruction) than before,
however keeps the code rather simple.
In sum this means there is no need to perform any error prone page table
walks anymore when accessing user space.
The patch seems to be rather large, however it mainly removes the
the page table walk code and restores the previously deleted "standard"
uaccess code, with a couple of changes.
The uaccess without mvcos mode can be enforced with the "uaccess_primary"
kernel parameter.
Reported-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2014-03-21 17:42:25 +08:00
|
|
|
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
#
|
|
|
|
|
# CIF_FPU is set, restore floating-point controls and floating-point registers.
|
|
|
|
|
#
|
|
|
|
|
.Lio_vxrs:
|
|
|
|
|
larl %r14,.Lio_return
|
|
|
|
|
jg load_fpu_regs
|
|
|
|
|
|
2016-01-26 21:10:34 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_GUARDED_STORAGE is set, call guarded_storage_load
|
|
|
|
|
#
|
|
|
|
|
.Lio_guarded_storage:
|
|
|
|
|
# TRACE_IRQS_ON already done at .Lio_return
|
|
|
|
|
ssm __LC_SVC_NEW_PSW # reenable interrupts
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
|
|
|
brasl %r14,gs_load_bc_cb
|
|
|
|
|
ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
|
|
|
|
|
TRACE_IRQS_OFF
|
|
|
|
|
j .Lio_return
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_NEED_RESCHED is set, call schedule
|
2006-09-28 22:56:37 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_reschedule:
|
|
|
|
|
# TRACE_IRQS_ON already done at .Lio_return
|
2011-12-27 18:27:15 +08:00
|
|
|
ssm __LC_SVC_NEW_PSW # reenable interrupts
|
2006-09-28 22:56:37 +08:00
|
|
|
brasl %r14,schedule # call scheduler
|
2011-12-27 18:27:15 +08:00
|
|
|
ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
|
2007-11-20 18:13:32 +08:00
|
|
|
TRACE_IRQS_OFF
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2017-02-14 09:42:34 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_PATCH_PENDING is set, call klp_update_patch_state
|
|
|
|
|
#
|
|
|
|
|
#ifdef CONFIG_LIVEPATCH
|
|
|
|
|
.Lio_patch_pending:
|
|
|
|
|
lg %r2,__LC_CURRENT # pass pointer to task struct
|
|
|
|
|
larl %r14,.Lio_return
|
|
|
|
|
jg klp_update_patch_state
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2008-04-30 15:53:08 +08:00
|
|
|
# _TIF_SIGPENDING or is set, call do_signal
|
2005-04-17 06:20:36 +08:00
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_sigpending:
|
|
|
|
|
# TRACE_IRQS_ON already done at .Lio_return
|
2011-12-27 18:27:15 +08:00
|
|
|
ssm __LC_SVC_NEW_PSW # reenable interrupts
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
|
|
|
brasl %r14,do_signal
|
|
|
|
|
ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
|
2007-11-20 18:13:32 +08:00
|
|
|
TRACE_IRQS_OFF
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2008-10-11 03:33:20 +08:00
|
|
|
#
|
|
|
|
|
# _TIF_NOTIFY_RESUME or is set, call do_notify_resume
|
|
|
|
|
#
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lio_notify_resume:
|
|
|
|
|
# TRACE_IRQS_ON already done at .Lio_return
|
2011-12-27 18:27:15 +08:00
|
|
|
ssm __LC_SVC_NEW_PSW # reenable interrupts
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
|
|
|
|
brasl %r14,do_notify_resume
|
|
|
|
|
ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
|
2008-10-11 03:33:20 +08:00
|
|
|
TRACE_IRQS_OFF
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return
|
2008-10-11 03:33:20 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* External interrupt handler routine
|
|
|
|
|
*/
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(ext_int_handler)
|
2012-05-09 22:27:39 +08:00
|
|
|
STCK __LC_INT_CLOCK
|
2008-12-31 22:11:41 +08:00
|
|
|
stpt __LC_ASYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r12,__LC_CURRENT
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
larl %r13,cleanup_critical
|
2011-12-27 18:27:15 +08:00
|
|
|
lmg %r8,%r9,__LC_EXT_OLD_PSW
|
2015-06-22 23:28:14 +08:00
|
|
|
SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
|
|
|
mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
|
|
|
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
2013-06-17 20:54:02 +08:00
|
|
|
lghi %r1,__LC_EXT_PARAMS2
|
|
|
|
|
mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
|
|
|
|
|
mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
|
|
|
|
|
mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
|
2014-04-15 18:55:07 +08:00
|
|
|
xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
|
2015-08-15 17:42:21 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
|
|
|
|
|
jo .Lio_restore
|
2006-07-03 15:24:46 +08:00
|
|
|
TRACE_IRQS_OFF
|
2012-05-09 22:27:35 +08:00
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
2011-12-27 18:27:15 +08:00
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2013-06-27 15:01:09 +08:00
|
|
|
lghi %r3,EXT_INTERRUPT
|
|
|
|
|
brasl %r14,do_IRQ
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lio_return
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2012-03-11 23:59:27 +08:00
|
|
|
/*
|
2014-12-04 00:00:08 +08:00
|
|
|
* Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
|
2012-03-11 23:59:27 +08:00
|
|
|
*/
|
|
|
|
|
ENTRY(psw_idle)
|
2012-07-20 17:15:08 +08:00
|
|
|
stg %r3,__SF_EMPTY(%r15)
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r1,.Lpsw_idle_lpsw+4
|
2012-03-11 23:59:27 +08:00
|
|
|
stg %r1,__SF_EMPTY+8(%r15)
|
2015-09-18 22:41:36 +08:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
larl %r1,smp_cpu_mtid
|
|
|
|
|
llgf %r1,0(%r1)
|
|
|
|
|
ltgr %r1,%r1
|
|
|
|
|
jz .Lpsw_idle_stcctm
|
|
|
|
|
.insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
|
|
|
|
|
.Lpsw_idle_stcctm:
|
|
|
|
|
#endif
|
2015-11-19 18:09:45 +08:00
|
|
|
oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
|
2012-07-20 17:15:08 +08:00
|
|
|
STCK __CLOCK_IDLE_ENTER(%r2)
|
|
|
|
|
stpt __TIMER_IDLE_ENTER(%r2)
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lpsw_idle_lpsw:
|
2012-03-11 23:59:27 +08:00
|
|
|
lpswe __SF_EMPTY(%r15)
|
|
|
|
|
br %r14
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lpsw_idle_end:
|
2012-03-11 23:59:27 +08:00
|
|
|
|
2015-09-29 16:04:41 +08:00
|
|
|
/*
|
|
|
|
|
* Store floating-point controls and floating-point or vector register
|
|
|
|
|
* depending whether the vector facility is available. A critical section
|
|
|
|
|
* cleanup assures that the registers are stored even if interrupted for
|
|
|
|
|
* some other work. The CIF_FPU flag is set to trigger a lazy restore
|
|
|
|
|
* of the register contents at return from io or a system call.
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
*/
|
|
|
|
|
ENTRY(save_fpu_regs)
|
2015-06-29 22:43:06 +08:00
|
|
|
lg %r2,__LC_CURRENT
|
|
|
|
|
aghi %r2,__TASK_thread
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_FPU
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
bor %r14
|
2015-06-29 22:43:06 +08:00
|
|
|
stfpc __THREAD_FPU_fpc(%r2)
|
|
|
|
|
lg %r3,__THREAD_FPU_regs(%r2)
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
jz .Lsave_fpu_regs_fp # no -> store FP regs
|
|
|
|
|
VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
|
|
|
|
|
VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
|
|
|
|
|
j .Lsave_fpu_regs_done # -> set CIF_FPU flag
|
|
|
|
|
.Lsave_fpu_regs_fp:
|
|
|
|
|
std 0,0(%r3)
|
|
|
|
|
std 1,8(%r3)
|
|
|
|
|
std 2,16(%r3)
|
|
|
|
|
std 3,24(%r3)
|
|
|
|
|
std 4,32(%r3)
|
|
|
|
|
std 5,40(%r3)
|
|
|
|
|
std 6,48(%r3)
|
|
|
|
|
std 7,56(%r3)
|
|
|
|
|
std 8,64(%r3)
|
|
|
|
|
std 9,72(%r3)
|
|
|
|
|
std 10,80(%r3)
|
|
|
|
|
std 11,88(%r3)
|
|
|
|
|
std 12,96(%r3)
|
|
|
|
|
std 13,104(%r3)
|
|
|
|
|
std 14,112(%r3)
|
|
|
|
|
std 15,120(%r3)
|
|
|
|
|
.Lsave_fpu_regs_done:
|
|
|
|
|
oi __LC_CPU_FLAGS+7,_CIF_FPU
|
|
|
|
|
br %r14
|
|
|
|
|
.Lsave_fpu_regs_end:
|
2016-01-13 02:30:03 +08:00
|
|
|
EXPORT_SYMBOL(save_fpu_regs)
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
|
2015-09-29 16:04:41 +08:00
|
|
|
/*
|
|
|
|
|
* Load floating-point controls and floating-point or vector registers.
|
|
|
|
|
* A critical section cleanup assures that the register contents are
|
|
|
|
|
* loaded even if interrupted for some other work.
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
*
|
|
|
|
|
* There are special calling conventions to fit into sysc and io return work:
|
|
|
|
|
* %r15: <kernel stack>
|
|
|
|
|
* The function requires:
|
2015-09-29 16:04:41 +08:00
|
|
|
* %r4
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
*/
|
|
|
|
|
load_fpu_regs:
|
2015-06-29 22:43:06 +08:00
|
|
|
lg %r4,__LC_CURRENT
|
|
|
|
|
aghi %r4,__TASK_thread
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_FPU
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
bnor %r14
|
2015-06-29 22:43:06 +08:00
|
|
|
lfpc __THREAD_FPU_fpc(%r4)
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
|
2015-06-29 22:43:06 +08:00
|
|
|
lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
|
2015-09-29 16:04:41 +08:00
|
|
|
jz .Lload_fpu_regs_fp # -> no VX, load FP regs
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
VLM %v0,%v15,0,%r4
|
|
|
|
|
VLM %v16,%v31,256,%r4
|
|
|
|
|
j .Lload_fpu_regs_done
|
|
|
|
|
.Lload_fpu_regs_fp:
|
|
|
|
|
ld 0,0(%r4)
|
|
|
|
|
ld 1,8(%r4)
|
|
|
|
|
ld 2,16(%r4)
|
|
|
|
|
ld 3,24(%r4)
|
|
|
|
|
ld 4,32(%r4)
|
|
|
|
|
ld 5,40(%r4)
|
|
|
|
|
ld 6,48(%r4)
|
|
|
|
|
ld 7,56(%r4)
|
|
|
|
|
ld 8,64(%r4)
|
|
|
|
|
ld 9,72(%r4)
|
|
|
|
|
ld 10,80(%r4)
|
|
|
|
|
ld 11,88(%r4)
|
|
|
|
|
ld 12,96(%r4)
|
|
|
|
|
ld 13,104(%r4)
|
|
|
|
|
ld 14,112(%r4)
|
|
|
|
|
ld 15,120(%r4)
|
|
|
|
|
.Lload_fpu_regs_done:
|
|
|
|
|
ni __LC_CPU_FLAGS+7,255-_CIF_FPU
|
|
|
|
|
br %r14
|
|
|
|
|
.Lload_fpu_regs_end:
|
|
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.L__critical_end:
|
2005-09-04 06:57:56 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* Machine check handler routines
|
|
|
|
|
*/
|
2011-07-24 16:48:19 +08:00
|
|
|
ENTRY(mcck_int_handler)
|
2012-05-09 22:27:39 +08:00
|
|
|
STCK __LC_MCCK_CLOCK
|
2005-06-26 05:55:30 +08:00
|
|
|
la %r1,4095 # revalidate r1
|
|
|
|
|
spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
|
2006-09-28 22:56:37 +08:00
|
|
|
lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
|
2016-11-08 18:08:26 +08:00
|
|
|
lg %r12,__LC_CURRENT
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
larl %r13,cleanup_critical
|
2011-12-27 18:27:15 +08:00
|
|
|
lmg %r8,%r9,__LC_MCK_OLD_PSW
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
|
2014-12-04 00:00:08 +08:00
|
|
|
jo .Lmcck_panic # yes -> rest of mcck code invalid
|
2011-12-27 18:27:15 +08:00
|
|
|
lghi %r14,__LC_CPU_TIMER_SAVE_AREA
|
|
|
|
|
mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
|
2011-12-27 18:27:15 +08:00
|
|
|
jo 3f
|
2006-06-29 20:58:05 +08:00
|
|
|
la %r14,__LC_SYNC_ENTER_TIMER
|
|
|
|
|
clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
|
|
|
|
|
jl 0f
|
|
|
|
|
la %r14,__LC_ASYNC_ENTER_TIMER
|
|
|
|
|
0: clc 0(8,%r14),__LC_EXIT_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
jl 1f
|
2006-06-29 20:58:05 +08:00
|
|
|
la %r14,__LC_EXIT_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
|
|
|
|
|
jl 2f
|
2006-06-29 20:58:05 +08:00
|
|
|
la %r14,__LC_LAST_UPDATE_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
2: spt 0(%r14)
|
2010-05-17 16:00:03 +08:00
|
|
|
mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
|
2015-10-01 23:02:48 +08:00
|
|
|
3: TSTMSK __LC_MCCK_CODE,(MCCK_CODE_PSW_MWP_VALID|MCCK_CODE_PSW_IA_VALID)
|
2014-12-04 00:00:08 +08:00
|
|
|
jno .Lmcck_panic # no -> skip cleanup critical
|
2015-06-22 23:28:14 +08:00
|
|
|
SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lmcck_skip:
|
2013-02-28 23:28:41 +08:00
|
|
|
lghi %r14,__LC_GPREGS_SAVE_AREA+64
|
|
|
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
|
|
|
mvc __PT_R8(64,%r11),0(%r14)
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
2014-04-15 18:55:07 +08:00
|
|
|
xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
|
2011-12-27 18:27:15 +08:00
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2005-06-26 05:55:30 +08:00
|
|
|
brasl %r14,s390_do_machine_check
|
2011-12-27 18:27:15 +08:00
|
|
|
tm __PT_PSW+1(%r11),0x01 # returning to user ?
|
2014-12-04 00:00:08 +08:00
|
|
|
jno .Lmcck_return
|
2005-06-26 05:55:30 +08:00
|
|
|
lg %r1,__LC_KERNEL_STACK # switch to kernel stack
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
|
|
|
|
|
xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
|
|
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r1)
|
2005-06-26 05:55:30 +08:00
|
|
|
lgr %r15,%r1
|
2011-12-27 18:27:15 +08:00
|
|
|
ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
|
2015-10-01 23:02:48 +08:00
|
|
|
TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
|
2014-12-04 00:00:08 +08:00
|
|
|
jno .Lmcck_return
|
2006-07-03 15:24:46 +08:00
|
|
|
TRACE_IRQS_OFF
|
2005-06-26 05:55:30 +08:00
|
|
|
brasl %r14,s390_handle_mcck
|
2006-07-03 15:24:46 +08:00
|
|
|
TRACE_IRQS_ON
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lmcck_return:
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r14,__LC_VDSO_PER_CPU
|
|
|
|
|
lmg %r0,%r10,__PT_R0(%r11)
|
|
|
|
|
mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
|
2006-06-29 20:58:05 +08:00
|
|
|
tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
|
|
|
|
|
jno 0f
|
|
|
|
|
stpt __LC_EXIT_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
|
|
|
|
|
0: lmg %r11,%r15,__PT_R11(%r11)
|
|
|
|
|
lpswe __LC_RETURN_MCCK_PSW
|
|
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lmcck_panic:
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r15,__LC_PANIC_STACK
|
2016-12-02 20:29:22 +08:00
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15)
|
2014-12-04 00:00:08 +08:00
|
|
|
j .Lmcck_skip
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-08-03 22:44:19 +08:00
|
|
|
#
|
|
|
|
|
# PSW restart interrupt handler
|
|
|
|
|
#
|
2012-03-11 23:59:26 +08:00
|
|
|
ENTRY(restart_int_handler)
|
2015-10-07 00:06:15 +08:00
|
|
|
TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
|
|
|
|
|
jz 0f
|
|
|
|
|
.insn s,0xb2800000,__LC_LPP
|
|
|
|
|
0: stg %r15,__LC_SAVE_AREA_RESTART
|
2012-03-11 23:59:26 +08:00
|
|
|
lg %r15,__LC_RESTART_STACK
|
2011-12-27 18:27:15 +08:00
|
|
|
aghi %r15,-__PT_SIZE # create pt_regs on stack
|
2012-03-11 23:59:26 +08:00
|
|
|
xc 0(__PT_SIZE,%r15),0(%r15)
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r0,%r14,__PT_R0(%r15)
|
|
|
|
|
mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
|
|
|
|
|
mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
|
2012-03-11 23:59:26 +08:00
|
|
|
aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack
|
|
|
|
|
xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
|
2012-06-05 15:59:52 +08:00
|
|
|
lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
|
|
|
|
|
lg %r2,__LC_RESTART_DATA
|
|
|
|
|
lg %r3,__LC_RESTART_SOURCE
|
2012-03-11 23:59:26 +08:00
|
|
|
ltgr %r3,%r3 # test source cpu address
|
|
|
|
|
jm 1f # negative -> skip source stop
|
2012-06-04 21:05:43 +08:00
|
|
|
0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
|
2012-03-11 23:59:26 +08:00
|
|
|
brc 10,0b # wait for status stored
|
|
|
|
|
1: basr %r14,%r1 # call function
|
|
|
|
|
stap __SF_EMPTY(%r15) # store cpu address
|
|
|
|
|
llgh %r3,__SF_EMPTY(%r15)
|
2012-06-04 21:05:43 +08:00
|
|
|
2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
|
2012-03-11 23:59:26 +08:00
|
|
|
brc 2,2b
|
|
|
|
|
3: j 3b
|
2011-08-03 22:44:19 +08:00
|
|
|
|
2011-01-05 19:47:25 +08:00
|
|
|
.section .kprobes.text, "ax"
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#ifdef CONFIG_CHECK_STACK
|
|
|
|
|
/*
|
|
|
|
|
* The synchronous or the asynchronous stack overflowed. We are dead.
|
|
|
|
|
* No need to properly save the registers, we are going to panic anyway.
|
|
|
|
|
* Setup a pt_regs so that show_trace can provide a good call trace.
|
|
|
|
|
*/
|
|
|
|
|
stack_overflow:
|
2013-04-24 16:20:43 +08:00
|
|
|
lg %r15,__LC_PANIC_STACK # change to panic stack
|
|
|
|
|
la %r11,STACK_FRAME_OVERHEAD(%r15)
|
2011-12-27 18:27:15 +08:00
|
|
|
stmg %r0,%r7,__PT_R0(%r11)
|
|
|
|
|
stmg %r8,%r9,__PT_PSW(%r11)
|
|
|
|
|
mvc __PT_R8(64,%r11),0(%r14)
|
|
|
|
|
stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
|
|
|
|
|
xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
|
|
|
|
|
lgr %r2,%r11 # pass pointer to pt_regs
|
2005-04-17 06:20:36 +08:00
|
|
|
jg kernel_stack_overflow
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
cleanup_critical:
|
2015-06-22 23:26:40 +08:00
|
|
|
#if IS_ENABLED(CONFIG_KVM)
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
|
|
|
|
|
jl 0f
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
|
|
|
|
|
jl .Lcleanup_sie
|
|
|
|
|
#endif
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_table) # system_call
|
2005-04-17 06:20:36 +08:00
|
|
|
jl 0f
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
|
|
|
|
|
jl .Lcleanup_system_call
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
|
2005-04-17 06:20:36 +08:00
|
|
|
jl 0f
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
|
|
|
|
|
jl .Lcleanup_sysc_tif
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
|
|
|
|
|
jl .Lcleanup_sysc_restore
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
|
2006-06-29 20:58:05 +08:00
|
|
|
jl 0f
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
|
|
|
|
|
jl .Lcleanup_io_tif
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
|
|
|
|
|
jl .Lcleanup_io_restore
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+64) # psw_idle
|
2012-03-11 23:59:27 +08:00
|
|
|
jl 0f
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
|
|
|
|
|
jl .Lcleanup_idle
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
|
|
|
|
|
jl 0f
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
|
|
|
|
|
jl .Lcleanup_save_fpu_regs
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
|
|
|
|
|
jl 0f
|
|
|
|
|
clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
|
|
|
|
|
jl .Lcleanup_load_fpu_regs
|
2011-12-27 18:27:15 +08:00
|
|
|
0: br %r14
|
|
|
|
|
|
2015-06-22 23:26:40 +08:00
|
|
|
.align 8
|
|
|
|
|
.Lcleanup_table:
|
|
|
|
|
.quad system_call
|
|
|
|
|
.quad .Lsysc_do_svc
|
|
|
|
|
.quad .Lsysc_tif
|
|
|
|
|
.quad .Lsysc_restore
|
|
|
|
|
.quad .Lsysc_done
|
|
|
|
|
.quad .Lio_tif
|
|
|
|
|
.quad .Lio_restore
|
|
|
|
|
.quad .Lio_done
|
|
|
|
|
.quad psw_idle
|
|
|
|
|
.quad .Lpsw_idle_end
|
|
|
|
|
.quad save_fpu_regs
|
|
|
|
|
.quad .Lsave_fpu_regs_end
|
|
|
|
|
.quad load_fpu_regs
|
|
|
|
|
.quad .Lload_fpu_regs_end
|
|
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_KVM)
|
|
|
|
|
.Lcleanup_table_sie:
|
|
|
|
|
.quad .Lsie_gmap
|
|
|
|
|
.quad .Lsie_done
|
|
|
|
|
|
|
|
|
|
.Lcleanup_sie:
|
2017-06-07 17:30:42 +08:00
|
|
|
cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt?
|
|
|
|
|
je 1f
|
|
|
|
|
slg %r9,BASED(.Lsie_crit_mcck_start)
|
|
|
|
|
clg %r9,BASED(.Lsie_crit_mcck_length)
|
|
|
|
|
jh 1f
|
|
|
|
|
oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
|
|
|
|
|
1: lg %r9,__SF_EMPTY(%r15) # get control block pointer
|
2015-10-07 00:06:15 +08:00
|
|
|
ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
|
2015-06-22 23:26:40 +08:00
|
|
|
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
|
|
|
|
|
larl %r9,sie_exit # skip forward to sie_exit
|
|
|
|
|
br %r14
|
|
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_system_call:
|
2011-12-27 18:27:15 +08:00
|
|
|
# check if stpt has been executed
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_system_call_insn)
|
2005-04-17 06:20:36 +08:00
|
|
|
jh 0f
|
|
|
|
|
mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
2011-12-27 18:27:15 +08:00
|
|
|
cghi %r11,__LC_SAVE_AREA_ASYNC
|
2010-05-17 16:00:03 +08:00
|
|
|
je 0f
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
|
|
|
|
|
0: # check if stmg has been executed
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_system_call_insn+8)
|
2005-04-17 06:20:36 +08:00
|
|
|
jh 0f
|
2011-12-27 18:27:15 +08:00
|
|
|
mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
|
|
|
|
|
0: # check if base register setup + TIF bit load has been done
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_system_call_insn+16)
|
2011-12-27 18:27:15 +08:00
|
|
|
jhe 0f
|
2017-01-25 19:54:17 +08:00
|
|
|
# set up saved register r12 task struct pointer
|
|
|
|
|
stg %r12,32(%r11)
|
|
|
|
|
# set up saved register r13 __TASK_thread offset
|
|
|
|
|
mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
|
2011-12-27 18:27:15 +08:00
|
|
|
0: # check if the user time update has been done
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_system_call_insn+24)
|
2011-12-27 18:27:15 +08:00
|
|
|
jh 0f
|
|
|
|
|
lg %r15,__LC_EXIT_TIMER
|
|
|
|
|
slg %r15,__LC_SYNC_ENTER_TIMER
|
|
|
|
|
alg %r15,__LC_USER_TIMER
|
|
|
|
|
stg %r15,__LC_USER_TIMER
|
|
|
|
|
0: # check if the system time update has been done
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_system_call_insn+32)
|
2011-12-27 18:27:15 +08:00
|
|
|
jh 0f
|
|
|
|
|
lg %r15,__LC_LAST_UPDATE_TIMER
|
|
|
|
|
slg %r15,__LC_EXIT_TIMER
|
|
|
|
|
alg %r15,__LC_SYSTEM_TIMER
|
|
|
|
|
stg %r15,__LC_SYSTEM_TIMER
|
|
|
|
|
0: # update accounting time stamp
|
2005-04-17 06:20:36 +08:00
|
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
|
2017-01-25 19:54:17 +08:00
|
|
|
# set up saved register r11
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r15,__LC_KERNEL_STACK
|
2013-04-24 16:20:43 +08:00
|
|
|
la %r9,STACK_FRAME_OVERHEAD(%r15)
|
|
|
|
|
stg %r9,24(%r11) # r11 pt_regs pointer
|
2011-12-27 18:27:15 +08:00
|
|
|
# fill pt_regs
|
2013-04-24 16:20:43 +08:00
|
|
|
mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
|
|
|
|
|
stmg %r0,%r7,__PT_R0(%r9)
|
|
|
|
|
mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
|
|
|
|
|
mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
|
2014-04-15 18:55:07 +08:00
|
|
|
xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
|
|
|
|
|
mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
|
2011-12-27 18:27:15 +08:00
|
|
|
# setup saved register r15
|
|
|
|
|
stg %r15,56(%r11) # r15 stack pointer
|
|
|
|
|
# set new psw address and exit
|
2014-12-04 00:00:08 +08:00
|
|
|
larl %r9,.Lsysc_do_svc
|
2005-04-17 06:20:36 +08:00
|
|
|
br %r14
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_system_call_insn:
|
2006-09-28 22:56:37 +08:00
|
|
|
.quad system_call
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .Lsysc_stmg
|
|
|
|
|
.quad .Lsysc_per
|
2015-06-22 23:27:48 +08:00
|
|
|
.quad .Lsysc_vtime+36
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .Lsysc_vtime+42
|
2017-01-25 19:54:17 +08:00
|
|
|
.Lcleanup_system_call_const:
|
|
|
|
|
.quad __TASK_thread
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_sysc_tif:
|
|
|
|
|
larl %r9,.Lsysc_tif
|
2005-04-17 06:20:36 +08:00
|
|
|
br %r14
|
|
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_sysc_restore:
|
2017-05-02 19:36:00 +08:00
|
|
|
# check if stpt has been executed
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_sysc_restore_insn)
|
2017-05-02 19:36:00 +08:00
|
|
|
jh 0f
|
|
|
|
|
mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
|
|
|
|
|
cghi %r11,__LC_SAVE_AREA_ASYNC
|
2010-05-17 16:00:03 +08:00
|
|
|
je 0f
|
2017-05-02 19:36:00 +08:00
|
|
|
mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
|
|
|
|
|
0: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
|
|
|
|
|
je 1f
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r9,24(%r11) # get saved pointer to pt_regs
|
|
|
|
|
mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
|
|
|
|
|
mvc 0(64,%r11),__PT_R8(%r9)
|
|
|
|
|
lmg %r0,%r7,__PT_R0(%r9)
|
2017-05-02 19:36:00 +08:00
|
|
|
1: lmg %r8,%r9,__LC_RETURN_PSW
|
2005-04-17 06:20:36 +08:00
|
|
|
br %r14
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_sysc_restore_insn:
|
2017-05-02 19:36:00 +08:00
|
|
|
.quad .Lsysc_exit_timer
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .Lsysc_done - 4
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_io_tif:
|
|
|
|
|
larl %r9,.Lio_tif
|
2010-04-09 19:43:00 +08:00
|
|
|
br %r14
|
|
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_io_restore:
|
2017-05-02 19:36:00 +08:00
|
|
|
# check if stpt has been executed
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_io_restore_insn)
|
2017-05-02 19:36:00 +08:00
|
|
|
jh 0f
|
|
|
|
|
mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
|
|
|
|
|
0: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
|
|
|
|
|
je 1f
|
2011-12-27 18:27:15 +08:00
|
|
|
lg %r9,24(%r11) # get saved r11 pointer to pt_regs
|
|
|
|
|
mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
|
|
|
|
|
mvc 0(64,%r11),__PT_R8(%r9)
|
|
|
|
|
lmg %r0,%r7,__PT_R0(%r9)
|
2017-05-02 19:36:00 +08:00
|
|
|
1: lmg %r8,%r9,__LC_RETURN_PSW
|
2005-09-04 06:57:56 +08:00
|
|
|
br %r14
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_io_restore_insn:
|
2017-05-02 19:36:00 +08:00
|
|
|
.quad .Lio_exit_timer
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .Lio_done - 4
|
2005-09-04 06:57:56 +08:00
|
|
|
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_idle:
|
2015-11-19 18:09:45 +08:00
|
|
|
ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
|
2012-03-11 23:59:27 +08:00
|
|
|
# copy interrupt clock & cpu timer
|
2012-07-20 17:15:08 +08:00
|
|
|
mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
|
|
|
|
|
mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
|
2012-03-11 23:59:27 +08:00
|
|
|
cghi %r11,__LC_SAVE_AREA_ASYNC
|
|
|
|
|
je 0f
|
2012-07-20 17:15:08 +08:00
|
|
|
mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
|
|
|
|
|
mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
|
2012-03-11 23:59:27 +08:00
|
|
|
0: # check if stck & stpt have been executed
|
2014-12-04 00:00:08 +08:00
|
|
|
clg %r9,BASED(.Lcleanup_idle_insn)
|
2012-03-11 23:59:27 +08:00
|
|
|
jhe 1f
|
2012-07-20 17:15:08 +08:00
|
|
|
mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
|
|
|
|
|
mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
|
2015-09-18 22:41:36 +08:00
|
|
|
1: # calculate idle cycles
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
clg %r9,BASED(.Lcleanup_idle_insn)
|
|
|
|
|
jl 3f
|
|
|
|
|
larl %r1,smp_cpu_mtid
|
|
|
|
|
llgf %r1,0(%r1)
|
|
|
|
|
ltgr %r1,%r1
|
|
|
|
|
jz 3f
|
|
|
|
|
.insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
|
|
|
|
|
larl %r3,mt_cycles
|
|
|
|
|
ag %r3,__LC_PERCPU_OFFSET
|
|
|
|
|
la %r4,__SF_EMPTY+16(%r15)
|
|
|
|
|
2: lg %r0,0(%r3)
|
|
|
|
|
slg %r0,0(%r4)
|
|
|
|
|
alg %r0,64(%r4)
|
|
|
|
|
stg %r0,0(%r3)
|
|
|
|
|
la %r3,8(%r3)
|
|
|
|
|
la %r4,8(%r4)
|
|
|
|
|
brct %r1,2b
|
|
|
|
|
#endif
|
|
|
|
|
3: # account system time going idle
|
2012-03-11 23:59:27 +08:00
|
|
|
lg %r9,__LC_STEAL_TIMER
|
2012-07-20 17:15:08 +08:00
|
|
|
alg %r9,__CLOCK_IDLE_ENTER(%r2)
|
2012-03-11 23:59:27 +08:00
|
|
|
slg %r9,__LC_LAST_UPDATE_CLOCK
|
|
|
|
|
stg %r9,__LC_STEAL_TIMER
|
2012-07-20 17:15:08 +08:00
|
|
|
mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
|
2012-03-11 23:59:27 +08:00
|
|
|
lg %r9,__LC_SYSTEM_TIMER
|
|
|
|
|
alg %r9,__LC_LAST_UPDATE_TIMER
|
2012-07-20 17:15:08 +08:00
|
|
|
slg %r9,__TIMER_IDLE_ENTER(%r2)
|
2012-03-11 23:59:27 +08:00
|
|
|
stg %r9,__LC_SYSTEM_TIMER
|
2012-07-20 17:15:08 +08:00
|
|
|
mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
|
2012-03-11 23:59:27 +08:00
|
|
|
# prepare return psw
|
2013-08-23 20:45:58 +08:00
|
|
|
nihh %r8,0xfcfd # clear irq & wait state bits
|
2012-03-11 23:59:27 +08:00
|
|
|
lg %r9,48(%r11) # return from psw_idle
|
|
|
|
|
br %r14
|
2014-12-04 00:00:08 +08:00
|
|
|
.Lcleanup_idle_insn:
|
|
|
|
|
.quad .Lpsw_idle_lpsw
|
2012-03-11 23:59:27 +08:00
|
|
|
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
.Lcleanup_save_fpu_regs:
|
2016-03-10 16:52:55 +08:00
|
|
|
larl %r9,save_fpu_regs
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
br %r14
|
|
|
|
|
|
|
|
|
|
.Lcleanup_load_fpu_regs:
|
2016-03-10 16:52:55 +08:00
|
|
|
larl %r9,load_fpu_regs
|
s390/kernel: lazy restore fpu registers
Improve the save and restore behavior of FPU register contents to use the
vector extension within the kernel.
The kernel does not use floating-point or vector registers and, therefore,
saving and restoring the FPU register contents are performed for handling
signals or switching processes only. To prepare for using vector
instructions and vector registers within the kernel, enhance the save
behavior and implement a lazy restore at return to user space from a
system call or interrupt.
To implement the lazy restore, the save_fpu_regs() sets a CPU information
flag, CIF_FPU, to indicate that the FPU registers must be restored.
Saving and setting CIF_FPU is performed in an atomic fashion to be
interrupt-safe. When the kernel wants to use the vector extension or
wants to change the FPU register state for a task during signal handling,
the save_fpu_regs() must be called first. The CIF_FPU flag is also set at
process switch. At return to user space, the FPU state is restored. In
particular, the FPU state includes the floating-point or vector register
contents, as well as, vector-enablement and floating-point control. The
FPU state restore and clearing CIF_FPU is also performed in an atomic
fashion.
For KVM, the restore of the FPU register state is performed when restoring
the general-purpose guest registers before the SIE instructions is started.
Because the path towards the SIE instruction is interruptible, the CIF_FPU
flag must be checked again right before going into SIE. If set, the guest
registers must be reloaded again by re-entering the outer SIE loop. This
is the same behavior as if the SIE critical section is interrupted.
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2015-06-10 18:53:42 +08:00
|
|
|
br %r14
|
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/*
|
|
|
|
|
* Integer constants
|
|
|
|
|
*/
|
2011-12-27 18:27:15 +08:00
|
|
|
.align 8
|
2005-04-17 06:20:36 +08:00
|
|
|
.Lcritical_start:
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .L__critical_start
|
2011-12-27 18:27:15 +08:00
|
|
|
.Lcritical_length:
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .L__critical_end - .L__critical_start
|
2013-11-01 17:08:20 +08:00
|
|
|
#if IS_ENABLED(CONFIG_KVM)
|
2015-06-22 23:26:40 +08:00
|
|
|
.Lsie_critical_start:
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .Lsie_gmap
|
2013-05-17 20:41:37 +08:00
|
|
|
.Lsie_critical_length:
|
2014-12-04 00:00:08 +08:00
|
|
|
.quad .Lsie_done - .Lsie_gmap
|
2017-06-07 17:30:42 +08:00
|
|
|
.Lsie_crit_mcck_start:
|
|
|
|
|
.quad .Lsie_entry
|
|
|
|
|
.Lsie_crit_mcck_length:
|
|
|
|
|
.quad .Lsie_skip - .Lsie_entry
|
2011-07-24 16:48:18 +08:00
|
|
|
#endif
|
|
|
|
|
|
2015-02-13 21:44:29 +08:00
|
|
|
.section .rodata, "a"
|
|
|
|
|
#define SYSCALL(esame,emu) .long esame
|
2009-06-12 16:26:47 +08:00
|
|
|
.globl sys_call_table
|
2005-04-17 06:20:36 +08:00
|
|
|
sys_call_table:
|
|
|
|
|
#include "syscalls.S"
|
|
|
|
|
#undef SYSCALL
|
|
|
|
|
|
2006-01-06 16:19:28 +08:00
|
|
|
#ifdef CONFIG_COMPAT
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2015-02-13 21:44:29 +08:00
|
|
|
#define SYSCALL(esame,emu) .long emu
|
2013-04-24 18:58:39 +08:00
|
|
|
.globl sys_call_table_emu
|
2005-04-17 06:20:36 +08:00
|
|
|
sys_call_table_emu:
|
|
|
|
|
#include "syscalls.S"
|
|
|
|
|
#undef SYSCALL
|
|
|
|
|
#endif
|